JP3221616B2 - Semiconductor integrated device and electronic system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for generating a highly accurate and stabilized reference delay and an electronic device using the same.

[0002] Delay circuits have a wide range of applications, such as for phase matching between signals. The higher the speed of the circuit, the more the delay time is required to be determined more precisely and to be stable without being changed by the power supply voltage or the temperature. The present invention relates to such a delay (DELA).
Y).

[0003]

2. Description of the Related Art Among the quantities that can be handled by a semiconductor device, relatively stable ones include a voltage by a band gap reference circuit and a frequency by crystal oscillation. In both cases, the influence of the temperature dependence and the power supply voltage dependence of the semiconductor is prevented from appearing, and the utility value thereof is high. The latter crystal oscillation is mainly used as a stable clock, but it can be combined with PLL (Phase Locked Loop) technology to synthesize signals of many frequencies almost freely. A remarkable development has been made to stabilize the operation by locking the operation to the accuracy of crystal oscillation.

[0004] Stable timing can be obtained by this crystal oscillation or a combination thereof with a PLL. For example, a shift register is a typical digital delay circuit. If this shift clock is obtained by crystal oscillation, a highly stable and accurate delay time can be obtained.

[0005]

Problem to be Solved by the Invention Crystal Oscillation and Its PL
The delay timing can be obtained by the combination of L, which is a delay synchronized with the clock. That is, for example, as in a shift register, a change from one state to another state is performed at a predetermined timing such as rising / falling, every clock cycle, and is not synchronized with the clock and does not become free. In other words, event driven
Instead, only a synchronous operation can be realized.

An object of the present invention is to provide a reference delay generator capable of improving the above-mentioned points, operating asynchronously, and providing a highly stable and highly accurate delay.

[0007]

According to the present invention, as shown in FIG. 1, a delay unit (hereinafter referred to as VCD) controlled by a voltage or a current, a phase difference detection circuit PDD,
(In this case the charge pump circuit CP and a capacitor C) to the control signal V _C to supply the control circuit CT CD constituting the reference delay generator out with.

[0008] A high stability and high precision external clock ECK and EXCK obtained by a crystal oscillator or the like are supplied to the VCD.

The phase difference detection circuit PDD is connected to the clock EC.
K, EXCK (CK ₀ , XCK ₀ ) and clocks DCK, XDCK delayed by VCD, and signals UP, DN indicating the phase difference between them are generated.

The charge pump circuit CP receives the signals UP, D
The capacitor C is charged and discharged by receiving N, produces the control signal V _C of the VCD.

The reference delay generator constructed as described above can be applied to various controls as described later. For example, the delay circuit DLC of FIG. 1 can be controlled. The delay circuit DLC is V
The same delay elements E _a to E _m delay elements E ₁ to E _n of the CD is constituted by M pieces cascaded, receives the control signal V _C of these delay elements.

As shown in FIG. 2, a single-ended external clock ECK can be similarly configured in place of the complementary external clocks ECK and EXCK.

[0013]

In FIG. 1, VCD, PDD and CT constitute a PLL, and delayed clocks DCK and XDCK are non-delayed clocks CK ₀ and XCK with an integer multiple of 90 °, for example, one cycle delayed.
So that the ₀ in phase, changing the delay time of each delay element E ₁ to E _n in accordance with the control signal V _C. Therefore, in the in-phase state, if the cycle of the input clock ECK is T, the number of the delay elements E ₁ , E ₂ ,... Of the VCD is N, and the delay time of each delay element is τ, N · τ = T, Therefore, τ = T / N. Since T is exactly constant, τ is also exactly constant. It is affected by fluctuations in ambient temperature and power supply voltage, varies from lot to lot, and is not affected by aging. Each delay element E _a of the control signal V _C of the delay circuit DLC, E _b,
.., These delay times are automatically adjusted to τ. If there are M delays, a delay of M · τ can be given to the input signal S _in . The input signal S _in may be asynchronous with the clock.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG.
The CD is composed of N cascade-connected delay elements E having variable delay times under voltage control. When a high-precision and high-stability reference clock ECK and EXCK (X indicates inversion) obtained from a crystal oscillator or the like are added to VCD via a buffer BUF, a delay clock DCF (D indicates delay), XDCK
Is obtained. The delay time of one of the N delay elements E is τ
Then, the delay added by the VCD is N · τ. However, strictly speaking, the delay time of each element is different and fluctuates depending on the power supply voltage and the ambient temperature, so the above N · τ is an approximate value. The delay clock DCK,
XDCK and clocks CK ₀ and XCK ₀ that do not pass through the VCD and thus have no delay are added, and the phase difference between them is obtained.

The phase difference detection circuit PDD has a delay clock DC.
K, XDCK and no delay clock CK ₀, XCK₀Phase of
Find the difference, and if the delayed clock is more advanced,
Delay is large, do nothing if in phase, no delay
If the clock is ahead, the delay in VCD will be small
Output UP, DN. Charge pump times
The path CP charges and discharges the capacitor C according to the signals UP and DN.
And the voltage V _CIs increased or decreased. This voltage V_CIs
In addition to the N delay elements E, the delay adjustment is performed.

As a result, in the converged state, the delayed clock and the non-delayed clock have the same phase, but are delayed by one cycle (even if delayed by a plurality of cycles, the delay clock is adjusted to be one cycle delayed). In this state, the delay time τ per element
Is τ = T / N where T is the clock cycle, which is extremely high precision and high stability determined by the precision of the clocks ECK and EXCK. Note that, here, an average value is used without considering the variation of each element of τ.

When M similar delay elements E are connected in cascade and a capacitor voltage V _C is applied thereto, that is, when the same delay circuit is operated in the same state as the N delay elements E of the VCD, the delay of each of the M number of elements E is delayed. The time becomes the above τ, and M times becomes M · τ.
Therefore, when the input signal S _in is added to the delay circuit DLC, M
An output S _out delayed by τ is obtained. The delay time M · τ or T · M / N is stabilized by a PLL constituted by VCD, PDD, and CT, and τ = T. It is a high precision variable in N units. In addition, it is event driven, and neither input nor output is clock synchronized.

FIG. 3 shows a configuration example of each delay element E of the phase difference detection circuit PDD and the control circuits CT and VCD shown in FIG.
Since the configuration of FIG. 2 is simpler than the configuration of FIG.
The details of the configuration will be described. In the figure, a phase difference detection circuit PDD is composed of an AND gate AND, an OR gate OR, and D-type flip-flops DFF ₁ and DFF ₂ , and a charge pump circuit is a p-channel MOS transistor Q ₁ ,
An n-channel MOS transistor Q ₂ , resistors R ₁ , R ₂ ,
It is composed of capacitors C ₁ and C ₂ . The delay element E is composed of p-channel MOS transistor Q ₃ ~Q _5, n-channel MOS transistor Q ₆ to Q _8.

The operation will be described with reference to the waveform diagram of FIG.
Then, (a) shows that the delayed clock DCK is the non-delayed clock C
K₀If it is more advanced (one cycle terminal is late)
Then, the output CK of the AND gate AND at this time₀. DC
K, output CK of OR gate OR ₀+ DCK output is shown
And the former is CK₀With DFF₁CK the latter₀
With DFF_TwoAnd outputs UP and DN are as shown in the figure.
Both become H level.

When CK ₀ and DCK are in phase as shown in FIG. 4B, the AND output and OR output become the same, the UP output becomes H, and the DN output becomes L. Also, as shown in FIG.
When CK is later than CK ₀ , the AND output and the OR output become as shown, and both the UP output and the DN output become L.

[0021] The output signal UP, when DN is applied to the transistors Q _1, Q ₂ of the charge pump circuit CP, decreases voltage V _c in (a) above if Q ₁ off, Q ₂ on, the capacitor C ₂ is discharged I do. This reduces the current of the transistor Q _8, Q ₇ of the delay elements E _i, the transistors Q ₃
Thus current Q ₄ is also the same (these form a current mirror), delay element E _i delay time (signal propagation time) to atmospheric.

As shown in FIG. 4B, when the signal UP is H and the signal DN is L, the transistors Q ₁ and Q _{2 of the} charge pump circuit CP are off, and the control circuit CT is in a high impedance state. Become. Therefore, capacitors C ₁ ,
There is no charge / discharge of C ₂ , and the voltage V _C enters a hold state.
As shown in FIG. 4C, DCK is delayed and UP is L and DN is L
, Q ₁ turns on and Q ₂ turns off, and the capacitor C ₂
The V _C is worth being charged. This increases the currents of Q ₈ and Q ₇ , increases the currents of Q _{3 and} thus Q ₄ , and reduces the delay time of the delay element E.

FIG. 5 is a detailed circuit diagram of the configuration of FIG.
As shown, the phase difference detection circuit PDD includes two OR gates OR1 and OR2 and two D-type flip-flops D.
It has FF3 and DFF4. The control circuit CT has a bipolar transistor Q ₁₁ to Q ₂₀ resistors R ₁₁ to R ₁₆ and capacitors C11, C12. The capacitor C in FIG. 1 is connected between the emitter of the transistor Q20 and the low potential side power supply line. Each delay element E of the VCD has bipolar transistors Q21 to Q25 and resistors R17 to R19.

FIG. 6 is a waveform chart showing the operation of the circuit of FIG. Since the reference voltage VR1 is applied to the base of the transistor Q14, a reference current flows through the transistor Q14, the resistor R13, and the transistor Q16. Since the transistors Q16, Q17 and Q12 form a current mirror circuit, the same current as the reference current flows through any of the transistor Q11, the resistor R11 and the transistor Q12 or the transistor Q15, the resistor R16 and the transistor 17. As a result, both the detection signals UP and DN are level-shifted and appear at the bases of the transistors Q19 and Q13, respectively. The transistor Q13 inverts the shifted detection signal DN to drive the transistor Q18.

FIG. 6A shows a case where the phase of the delayed clock DCK is ahead of the phase of the non-delayed clock CKO. In this case, the output signals of the OR gates OR1 and OR2 are as shown in FIG. At this time, both the detection signals UP and DN are L. In this case, the transistor Q18 is on and the transistor Q19 is off.

Therefore, transistor Q20 gradually becomes conductive, and capacitor C is charged. As a result, the control voltage V _C is increased, the collector current of the transistor Q25 increases. As a result, the delay time of the delay element E decreases.

FIG. 6B is a waveform diagram in which the delayed clock and the non-delayed clock CKO have the same phase. As shown, the detection signals UP and DN are at L and H levels, respectively. Therefore, the transistor Q13 is on. At this time, the transistors Q18 and Q19 are off. Therefore, the base of the transistor Q20 enters a high impedance state, and the control voltage V _C is held.

FIG. 6C shows a case where the phase of the non-delayed clock CKO is ahead of the phase of the delayed clock DCK. At this time, the detection signals UP and DN are both H. Therefore, the transistor Q18 is turned off and the transistor Q19 is turned on. Thereby, the transistor Q20
Is off and the capacitor C is discharged. As a result, the control voltage V _C decreases, the delay amount of the delay elements E is increased.

FIG. 7 is a block diagram of a modified example of the control circuit CT shown in the above-mentioned figure. As shown, the control circuit CT has an up / down counter UDC, a driver DV, and a D / A converter DAC. The up / down counter UDC has three modes according to the combination of the detection signals UP and DN. The first mode is an up-count mode, the second mode is a down-count mode,
The third mode is a sleep mode. The up / down counter UDC outputs the analog control voltage V from the capacitor C.
Outputs a digital value corresponding to _C. This digital value is supplied to D by a driver DV functioning as a buffer.
Input to the / A converter DAC. The D / A converter DAC is
Converting the digital values received on an analog control voltage V _C. The analog control voltage V _C is VCD and the delay circuit DL
C. Note that a PLL having another configuration can be used.

FIG. 8 is a block diagram showing a second embodiment of the present invention. As shown, a first reference delay generator RDG1, a second reference delay generator RDG2, D / A
Converter DAC2, controller CTL, memory MEM
And the above-described delay circuit DLC. Delay circuit DLC
Is the first or second reference delay generator RDG1 or RD
Controlled by G2. The first reference delay generator RDG1 has the same configuration as that of FIG. That is, the first reference delay generator RDG1 is VCD and the phase difference detection circuit P
DD, up / down counter UDC, driver DV,
And a D / A converter (DAC1 in FIG. 8). VC
D has N1 delay elements E. D / A converter DAC
1 generates the control voltage V _c 1.

The second reference delay generator RDG2 has a first
Is configured in the same manner as the reference delay generator RDG1.
Delay unit VCD of second reference delay generator RDG2
Has N2 delay elements E, D / A converter generates a control voltage V _c 2.

The output count value of the up / down counter UDC of the first reference delay generator RDG1 is input to the D / A converter DAC2 via the driver DV. Similarly, the output count value of the up / down counter (not shown) of the second reference delay generator RDG2 is provided to the D / A converter DAC2 via a driver (not shown). The controller CTL controls a bus that interconnects the reference delay generators RDG1 and RDG2 and the memory MEM, selects one of them, and supplies its count value to the D / A converter DAC2. D / A converter DA
C2 outputs the corresponding analog control signal to each of the M delay elements E
Output to

Each delay element E of the first reference delay generator RDG1 is controlled to have a delay time τ1, and each delay element E of the second reference delay generator RDG2 has a delay time τ2
Is controlled to have Controller CTL is RDG
When 1 is selected, the delay circuit DLC has a delay time of Mτ1. On the other hand, when the controller CTL selects RDG2, the delay circuit DLC has a delay time of Mτ2.

Under the bus control of the controller CTL,
The digital count values from the reference delay generators RDG1 and RDG2 can be stored in the memory MEM. In addition, with the bus control of the controller CTL,
The digital value generated by the external device can be stored in the memory MEM.

The digitized control circuit CT shown in FIG. 7 or FIG. 8 is superior to the analog control circuit CT shown in FIG. 1 or FIG. Signal lines between the control circuit CT and VCD, and respectively control circuit CT is a signal line between the delay circuit DLC, in order to prevent unnecessary variation of the control voltage V _C, to have a parasitic capacitance Is formed. Therefore,
It is somewhat difficult to switch the control voltage V _C rapidly. On the other hand, the digitized control circuit CT does not have such a problem.

FIG. 9 shows three reference delay generators RDG.
FIG. 3 is a block diagram showing a configuration for generating three different control signals using RDG1, RDG2 and RDG3. This configuration includes five voltage control delay units VCD1 to VCD5, 3
It has two PLL circuits PLL1 to PLL3, two D / A converters DAC2 and DAC3, and a selector SEL. Each of the PLL circuits PLL1 to PLL3 includes a phase difference detection circuit PDD, an up / down counter UDC, and a driver D.
It has a V and D / A converter DAC. PLL circuit PLL
VCD2 and VCD3 related to 2 are cascaded. Similarly, VCD4 and VCD5 related to the PLL circuit PLL3 are cascaded. As shown in FIG.
CD1 to VCD5 are N1 to N5 delay elements E, respectively.
have. External complementary clocks ECK and EXCK are V
Input to CD1, VCD2 and VCD4. PLL circuit PLL1 receives clocks DCK and XDCK from VCD1. PLL circuit PLL2 receives clocks DCK and XDCK from VCD3. The PLL circuit PLL3 has V
The clock DCK and XDCK are received from CD5.

The PLL circuit PLL1 outputs a control voltage V _C1 for determining the delay time τ1 of each delay element E to the VCD1, and outputs a digital count value A / Dout1 to the D / A.
Output to the converter DAC2. PLL circuit PLL2 is VC
To D3, and outputs the control voltage V _c 2 for determining the delay time τ2 of each delay element E, also outputs the digital count value A / Dout2 to the D / A converter DAC 3. The PLL circuit PLL3 adds the delay time τ3 of each delay element E to the VCD5.
And outputs the control voltage V _C 3 to determine. The PLL circuit PLL3 outputs a digital count value A / Dout3 not used in the configuration of FIG. Selectorco S
EL is one of the control voltage V _C 3 from the control voltage V _C 2 and DAC3 from DAC2, according to the selection signal from the circuit such as the controller CTL shown in FIG. 8, selecting.

The D / A converters DAC2 and DAC3 can be omitted. In this case, the analog control signal V _C 1
And V _C2 are directly supplied to the selector SEL from the PLL circuits PLL1 and PLL2.

VCD1 has a delay time of N1τ1, and
The delay unit consisting of CD2 and VCD3 is N2τ1 +
It has a delay time of N3τ2. In addition, VCD4 and VCD
5, the selector SEL has the DAC
When 3 is selected, the delay time is N4τ2 + N5τ3.

When N1 = 20, the external clock ECK (EXC
When K) is 500 MHz, τ1 = 100 ps.
When N2 = 9 and N3 = 10, 9 × 100 + 10τ2 =
At 2000, τ2 = 110 ps. N4 = N5 = 1
When the delay time τ2 is selected at 0, 10 × 110 + 1
00τ3 = 2000 and τ3 = 99 ps.

The VCD 4 shown in FIG. 9 may be configured as shown in FIG. The delay elements E of the VCD 4 are divided into two groups. One group receives the control voltage V _C1 from the D / A converter DAC2, and the other group receives the control voltage V _C2 from the D / A converter DAC3. When N4 = N5 = 10, various delay times τ3
Is obtained as follows.

N ₄ ... Τ ₃ = 99 at 9 × 100 ps + 1 × 110 ps
ps N ₄ … ₃ × 98 at 8 × 100 ps + 2 × 110 ps
ps N ₄ … ₃ = 97 at 7 × 100 ps + 3 × 110 ps
ps N ₄ ... 6 × 100 ps + 4 × 110 ps and τ ₃ = 96
_{ps N 4 ...... 5 × 100ps +} 5 in × 110ps τ ₃ = 95
ps N ₄ ... τ ₃ = 94 at 4 × 100 ps + 6 × 110 ps
_{ps N 4 ...... 3 × 100ps +} 7 × τ in 110ps ₃ = 93
ps N ₄ τ ₃ = 92 at 2 × 100 ps + 8 × 110 ps
ps N ₄ … ₃ = 91 at 1 × 100 ps + 9 × 110 ps
_{ps N 4 ...... 0 × 100ps +} 10 × τ in 110ps ₃ = 90
ps Although the delay circuit DLC is not shown in FIG. 3, if each element of the delay circuit is adjusted to the various delays τ ₁ , τ ₂ , τ ₃ , 309 ps, τ ₁ + at τ ₁ + τ ₂ + τ ₃ (99)
With τ ₂ + τ ₃ (91), a precise delay time such as 301 ps can be provided.

The input signal S _in of the delay circuit DLC is asynchronous with the clock, but of course there is no problem even with the clock synchronization.

The VCD 4 can be configured as shown in FIG. The selector SEL is provided for each delay element E. Each selector SEL selects one of the control voltages V _{C1 and} V _C 2 according to a selection signal composed of a plurality of bits. The selection signal includes data relating to the address of each selector SEL and data indicating which control voltage should be selected. The selection signal can be generated by a circuit such as a controller shown in FIG.

FIG. 11A is a block diagram showing a first application example in which the present invention is applied to pulse edge adjustment. This configuration includes a buffer BUF, four delay elements Ea, Eb,
Ec, Ed (not limited to four), a gate circuit G, and the above-described reference delay generator RDG. The delay elements Ea,
Eb,... Are adjusted to the same delay time τ ₁ by receiving the same control signal, and are also τ ₁ , τ ₂ ,.
... may be adjusted. Here, if it is adjusted to τ ₁ to τ ₄ , a delay time of Στ _i is given to the input signal S _in as a whole. Therefore, if the gate G is an OR gate, the fall is Στ _i
Been variously adjusted according to the rise if NOR gate Shigumatau _i
Are adjusted in accordance with These are rear end adjustments,
The front end adjustment is obtained by an AND gate, a NAND gate, and the like. The reference delay generator RDG may be asynchronous with the input signal S _in .

FIG. 12A is a block diagram showing a second application example of the present invention. Multiple voltage control delay units V
CD1 to VCDM are formed on the chip. VCD1,
VCD2 and VCDM consist of one, two and M delay elements, respectively. The reference delay generator RDG configured as described above is provided commonly to VCD1 to VCDM,
These outputs the control signal V _C. Reference delay generator R
The DG may be configured to receive a signal asynchronous with the external clock signal ECK. The selector SEL1 outputs a selection signal S generated by an external device or the controller shown in FIG.
_{According to SEL} , one of VCD1 to VCDM is selected. The selected clock signal CK _S are output to the internal circuit on the chip. With such a configuration, on the chip,
M clocks of high accuracy and high stability can be generated from an external clock. By selecting and using the M clocks, the internal circuit on the chip can be tested by various methods.

Further, as shown in FIG. 12A, a dummy delay circuit DDL having a delay time equal to the delay time of the selector SEL1 may be provided. Dummy delay circuit DDL generates delayed clock CKd. The internal circuit can be tested using the delayed clock CKd and the selected clock CKS. For example, as shown in FIG. 12B, the delay clock CKd and the selected clock CKS are supplied to flip-flops FF1 and FF2, respectively. The flip-flops FF1 and FF2 are provided on the input and output sides of the internal circuit INTCKT, respectively. Thus, a setup check can be performed. Delayed clock CKd, selected clock CKd, and flip-flops FF2 and FF1, respectively.
Give to. Thus, a hold check can be performed.

FIG. 13 is a diagram showing a third application example of the present invention. A third application example is the two chips CP1 and CP2
The purpose is to adjust the input / output timing between the two. As shown in FIG. 13, the chip CP1 has a voltage control delay unit VCD1, and the chip CP2 has a voltage control delay unit VCP2. VCD1 is controlled by a reference delay generator RDG1 formed on a chip.
CD2 is controlled by a reference delay generator RDG2. Each of the reference delay generators RDG1 and RDG2 may receive a signal asynchronous with the clock CK.
VCD1 delays clock CK to provide an input / output buffer I /
Output to O1. This input / output buffer I / O1 operates in synchronization with the delayed clock CK. Similarly, VCD
2 delays the clock signal CK to input / output buffer I / O
Output to 2. This input / output I / O2 operates in synchronization with the delayed clock CK. Reference delay generator RDG
1 and RDG2 control VCD1 and VCD2 to offset the delay between input / output buffers I / O1 and I / O2.
The control voltage obtained at this time is stored in the memories MEM1 and MEM2 under the control of the controllers CTL1 and CTL2.
Can also be stored. Also, the controller CTL
1 and STL2, data on a control voltage from an external device can be written into the memories MEM1 and MEM2. Note that the controllers CTL1, CTL2
The memories MEM1 and MEM2 are the same as those shown in FIG. The above-described timing adjustment can be performed after the chips CP1 and CP2 are mounted on the board.
That is, I / O timing design is no longer necessary. This timing adjustment can be performed at the time of system boot or in the initialization sequence, and the obtained data is stored in memories MEM1 and MEM2.
Can be stored.

FIG. 14 is a diagram showing a fourth application example of the present invention. FIG. 14A shows two functional blocks FB1 and FB1.
B2 and three flip-flop groups FF1, FF2 and F
4 shows a pipeline configuration having F3. As shown, clocks CK1, CK2 and CK3 are provided to flip-flop groups FF1, FF2 and FF3, respectively. After the input signal is latched by the flip-flop group FF1, it is input to the functional block FB1. The output signal of the functional block FB1 is latched by the flip-flop group FF2 and then input to the functional block FB2. The output signal of the functional block FB2 is latched by the flip-flop group FF3 and then input to the next functional block (not shown). In the conventional configuration, the same clock signal is supplied to the flip-flop groups FF1, FF2 and FF3.
Has given to.

On the other hand, according to the present invention, different clock signals can be applied to each flip-flop group. When the signal reception timing of some flip-flop groups on the input side of the pipeline configuration is slightly delayed from the reception timing of other flip-flop groups, for example, FIG.
4 (b), for example, the delayed intermediate clock C
3, CC2 and C1 are clocks CK1, CK2, respectively.
And CK3, flip-flop groups FF1, FF2
And FF3. The intermediate clock C1 is also applied to other flip-flop groups FF4, FF5,... (Not shown).
On the other hand, when the signal reception timing of some flip-flop groups on the output side of the pipeline configuration is slightly recommended than the reception timing of other flip-flop groups, for example, the delayed intermediate clocks C1, C2 and C3 is supplied to flip-flop groups FF1, FF2 and FF3 as clocks CK1, CK2 and CK3, respectively. The intermediate clock C3 is connected to another flip-flop group F
F4, FF5,...

The intermediate clock C generated by the configuration shown in FIG.
, C2, C3,...
2, FF3,... In this case, the input signal S _in is asynchronous with the external clock signal ECK.

FIG. 16A is a diagram showing a fifth application example of the present invention. The illustrated configuration functions as a clock distribution circuit. In FIG. 16A, the same components as those shown in the above-described drawings are denoted by the same reference numerals. CM
The OS type VCD is provided on the input side of the clock distribution system CDS. The signal obtained on the output side of the clock distribution system CDS is supplied to a flip-flop FF (not shown), and also an OPLL circuit PL via a variable delay element D0 +.
L. External complementary clocks ECK and EXCK
Is input to the converter CONV via the input buffer BUF. The converter CONV has clocks ECK and EX.
CK is converted into a CMOS level signal. This CMOS
The level signal enters the PLL circuit PLL via the variable delay element D0-. The PLL circuit PLL has a clock CK0.
Is compared with the phase of the delayed clock DCK, and the control voltage V _C is generated so that the phase difference becomes an integral multiple of 90 ° (for example, one cycle).

The variable delay elements D0 + and D0- can be adjusted as follows. When D0− is zero and D0 + is equal to the sum of the delay of the input buffer BEF and the delay of the converter CONV, the delay time between the external clock ECK and the clock distributed to the flip-flop group FF is almost zero. D0- = 2 ns and D0 + is the input buffer B
When it is equal to the sum of the delay of the UF and the delay of the converter CONV, the clock distributed to the flip-flop FF is delayed by 2NS from the external clock ECK. In this manner, a clock having a reliable phase relationship with the external clock ECK can be distributed to the flip-flop FF.

FIG. 16B shows a modification of the configuration shown in FIG. The configuration in FIG. 16B has an ECL type VCD. The operation is the same as that of FIG.

FIG. 17 shows a sixth application example of the present invention. This example has a monitor path circuit MP and an internal circuit INTCKT. The monitor path circuit MP has a plurality of cascade-connected internal gates E. This internal gate is CMOS, Bi
It is composed of circuits such as CMOS and TTL.
The variable power supply VPS is changed from the external power supply voltage _VEXT to the power supply voltage VEXT.
Generate _e . This power supply voltage V _e is supplied to the monitor path circuit M
P and each internal gate of the internal circuit INTCKT. In general, the propagation delay of a gate such as CMOS, CiCMOS, or TLL depends on its supply voltage. Therefore,
By controlling the power supply voltage, these gates can be used as a voltage control delay unit.

The PLL circuit PLL has an external clock ECK.
Is compared with the phase of the delayed clock DCK, and a control voltage V _c for controlling the phase difference to be eliminated.
Is output. Control voltage V _c is applied to the variable power source VPS, changing the output power supply voltage V _e. This power supply voltage V _e
Is controlled by the control voltage V _C generated by the monitor path circuit MP and the PLL circuit, so that the delay time of the internal gate E becomes substantially equal.

[0057]

As described above, a reference delay circuit which could not be realized in a semiconductor device until now can be realized by the present invention, and contributes to the development of large-scale semiconductor integrated circuit technology in many application fields. large.

[Brief description of the drawings]

FIG. 1 is a block diagram of a reference delay generator according to the present invention.

FIG. 2 is a block diagram of a modified example of the reference delay generator of FIG. 1;

FIG. 3 is a circuit diagram of the configuration of FIG. 2;

FIG. 4 is a waveform chart showing an operation of the circuit of FIG. 3;

FIG. 5 is a circuit diagram of the configuration of FIG. 1;

FIG. 6 is a waveform chart showing the operation of the circuit of FIG.

FIG. 7 is a block diagram showing another configuration of the control circuit shown in FIG. 1 or 2;

FIG. 8 is a block diagram showing another configuration of the reference delay generator of the present invention.

FIG. 9 is a block diagram showing still another configuration of the reference delay generator of the present invention.

10 is a block diagram showing another configuration example of the voltage control delay unit VCD4 shown in FIG.

FIG. 11 is a block diagram of a first application example of the present invention.

FIG. 12 is a block diagram of a second application example of the present invention.

FIG. 13 is a block diagram of a third application example of the present invention.

FIG. 14 is a block diagram of a fourth application example of the present invention.

FIG. 15 is a block diagram of a configuration replacing FIG. 14 (b).

FIG. 16 is a block diagram of a fifth application example of the present invention.

FIG. 17 is a block diagram of a sixth application example of the present invention.

[Explanation of symbols]

VCD, VCD1, VCD2, VCD3, VCD4, V
CD5 voltage control delay unit PDD phase difference detection circuit CT control circuit CP charge pump circuit DLC delay circuit E delay element UPC up / down counter DV driver DAC, DAC1, DAC2, DAC3 D / A converter CTL, CTL1, CTL2 controller MEM, MEM1, MEM2 Memory PLL PLL1, PLL2, PLL3 PLL circuit RDG, RDG1, RDG2 Reference delay generator SEL, SEL1 Selector

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-141121 (JP, A) JP-A-57-174927 (JP, A) JP-A-57-174928 (JP, A) JP-A 63-174 69315 (JP, A)

Claims (8)

(57) [Claims] A cascade-connected multiple circuit having a variable delay time.
It has a number of delay elements and receives a reference clock.
A delay unit that outputs a delayed clock that delays this
And the phase difference between the reference clock and the delay clock
Control signal for generating a control signal and inputting the control signal to the plurality of delay elements.
Control means, wherein the control means inputs the phase difference.
Phase detection for outputting a first control signal and a second control signal.
Output means, the first control signal and the second control signal,
Count up / down according to the digital count
A counter for outputting a value, and receiving the digital count value.
Driver and digital output from the driver
First conversion means for converting the count value into an analog signal;
And a second for converting the digital count value into an analog signal.
Conversion means, and output from the drivers of the plurality of reference delay generators.
To select the digital count value for the second conversion means.
Based on a controller supplied and a control signal supplied from the second conversion means.
A semiconductor integrated device comprising: a delay circuit that delays an input signal and outputs the delayed signal . 2. The digital counter output by the counter.
To store digital values or digital values generated by external devices.
2. The semiconductor integrated device according to claim 1 , further comprising storage means . 3. A cascaded circuit having a variable delay time.
It has a number of delay elements and receives a reference clock.
A delay unit that outputs a delayed clock that delays this
And detects and controls the phase difference between the reference clock and the delayed clock.
Control means for generating a signal and inputting the signal to the plurality of delay elements
Includes a plurality of reference delay generator having, when the control signal outputted from said plurality of reference delay generator
Selecting at least one delay element of the delay unit
A semiconductor integrated device having a selection unit for outputting to a child . 4. The control means of each of the reference delay generating devices, wherein the phase difference is inputted and a first control signal and a second control signal are inputted.
And a phase detection means for outputting a signal in response to the first control signal and the second control signal.
Output digital count value by counting up / down
A counter that receives the digital count value, and a digital count value output from the driver.
4. The semiconductor integrated circuit according to claim 3 , further comprising: first conversion means for converting the signal into a log signal.
apparatus. 5. The control means of each of the reference delay generating devices, wherein the phase difference is inputted and a first control signal and a second control signal are inputted.
And a phase detection means for outputting a signal in response to the first control signal and the second control signal.
Output digital count value by counting up / down
A counter that receives the digital count value, and a digital count value output from the driver.
First conversion means for converting the log signal is output from said plurality of reference delay generator driver
A second method for converting a digital count value into an analog signal
4. The semiconductor integrated device according to claim 3, further comprising a conversion unit . 6. A first reference delay generator, the control signal supplied from the first reference delay generator
Delay circuit for delaying and outputting an input signal based on the first delay circuit
And a first input which operates based on the output of the first delay circuit.
A first chip having an output buffer, a second reference delay generator, and a control signal supplied from the second reference delay generator.
Delay circuit for delaying an input signal based on the output and outputting the delayed signal
And a second input which operates based on the output of the second delay circuit.
And a second chip having an output buffer , wherein the first reference delay generator and the second reference delay generator are provided.
The device comprises a plurality of cascaded delay elements having variable delay times.
And delay this by receiving the reference clock.
A delay unit that outputs a delayed clock, and a phase difference between a reference clock and the delayed clock.
A control means for generating a control signal and inputting the control signal to the plurality of delay elements
Electronic system characterized in that it comprises a stage, a. 7. The first reference delay generator and the second reference delay generator.
The control means of the reference delay generating device further includes a first control signal and a second control signal to which the phase difference is input.
And a phase detection means for outputting a signal in response to the first control signal and the second control signal.
Output digital count value by counting up / down
A counter that receives the digital count value, and a digital count value output from the driver.
7. The electronic system according to claim 6 , further comprising: first conversion means for converting the log signal into a log signal.
M 8. The first chip or the second chip
Comprises a controller and storage means, wherein the controller comprises the first chip and the second chip
The control voltage when adjusting the input / output timing between
The electronic system according to claim 6, wherein the electronic system is stored in the storage unit.
M