JP3221060B2 - Substrate processing method and manufacturing method of mounting substrate - Google Patents

Substrate processing method and manufacturing method of mounting substrate

Info

Publication number
JP3221060B2
JP3221060B2 JP14843692A JP14843692A JP3221060B2 JP 3221060 B2 JP3221060 B2 JP 3221060B2 JP 14843692 A JP14843692 A JP 14843692A JP 14843692 A JP14843692 A JP 14843692A JP 3221060 B2 JP3221060 B2 JP 3221060B2
Authority
JP
Japan
Prior art keywords
substrate
processing
pattern
solder
treatment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP14843692A
Other languages
Japanese (ja)
Other versions
JPH05326637A (en
Inventor
睦禎 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP14843692A priority Critical patent/JP3221060B2/en
Publication of JPH05326637A publication Critical patent/JPH05326637A/en
Application granted granted Critical
Publication of JP3221060B2 publication Critical patent/JP3221060B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81193Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body

Landscapes

  • Manufacturing Of Printed Wiring (AREA)
  • Wire Bonding (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、基板処理方法及びこれ
を用いた実装基板の製造方法に関する。本発明は、電子
回路基板等の各種の基板の処理方法及びその製造方法
して用いることができる。例えば、プリント基板にワイ
ヤボンディングを行う場合の処理や、あるいはICチッ
プをはんだ付けして搭載する場合の処理を有する基板処
理として、また、このような処理を要する実装基板の製
造方法として、利用することができる。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for treating a substrate and a method for treating the same.
The present invention relates to a method for manufacturing a mounting board using the same . INDUSTRIAL APPLICABILITY The present invention can be used as a method for processing various substrates such as an electronic circuit substrate and a method for manufacturing the same . For example, as a substrate process having a process for performing wire bonding on a printed circuit board or a process for mounting an IC chip by soldering, or manufacturing a mounting board requiring such a process.
It can be used as a fabrication method .

【0002】[0002]

【従来の技術及び解決すべき問題点】基板にワイヤボン
ディングを行うとき、基板上に金メッキが必要である。
また、TAB(Tape Antomated Bonding) やフリップチ
ップ(基板上へのICチップのフェイスダウン接合)に
は、はんだ処理が必要である。例えば図3に示すよう
に、基板1上にCu箔2がプリントされ、この上にIC
チップ4をはんだ付けするときには、基板1のCu箔2
に予め予備はんだ3を形成するはんだ処理が必要であ
る。
2. Description of the Related Art When performing wire bonding on a substrate, gold plating is required on the substrate.
Further, TAB (Tape Antomated Bonding) or flip chip ( face-down bonding of an IC chip on a substrate ) requires soldering. For example, as shown in FIG. 3, a Cu foil 2 is printed on a substrate 1, and an IC
When the chip 4 is soldered, the Cu foil 2
Requires a soldering process for forming the preliminary solder 3 in advance.

【0003】しかし、このような各種処理も、基板1上
のパターンが微細化している現今にあっては必ずしも容
易ではない。特に、パターンギャップL(パターン間の
距離)が1mm未満の場合(図3参照)、このような処
理は困難である。
[0003] However, such various processes are not always easy in the present day when the pattern on the substrate 1 is miniaturized. In particular, when the pattern gap L (distance between patterns) is less than 1 mm (see FIG. 3), such processing is difficult.

【0004】一方、同一基板上には、1種類の処理しか
できない。例えば、金メッキ処理か、はんだ処理かのい
ずれか一方の金属処理しかできない。このため、同一基
板上にワイヤボンディング(金メッキが必要)とフリッ
プチップの実装(はんだ処理が必要)の両方を行おうと
しても、2種類の金属処理はできないので、この両方を
行うことができない。この問題は、高密度実装を実現す
るための隘路となっている。
On the other hand, only one type of processing can be performed on the same substrate. For example, it is possible to perform only one of the metal processing of the gold plating processing and the solder processing. For this reason, even if wire bonding (gold plating is required) and flip chip mounting (solder processing is required) are both performed on the same substrate, the two types of metal processing cannot be performed, and both cannot be performed. This problem is a bottleneck for realizing high-density mounting.

【0005】またフリップチップ用のパターンは、例え
ば75μmギャップ、75μm幅というように微細になるに
至っているため、前述したように基板上の処理は容易で
はなく、例えば通常のはんだクリーム印刷や、はんだデ
ィップなどではブリッジしてしまう。はんだ処理とし
て、微細な処理が可能なスーパーソルダーはんだ処理と
称される技術が開発されているが、このような処理を行
う場合も、パターンが微細であると必ずしもこれも容易
ではなく、かつ基本的に、2以上の処理は基板上に施せ
ない。
[0005] Further, since the pattern for the flip chip has become so fine as to have a gap of 75 μm and a width of 75 μm, for example, the processing on the substrate is not easy as described above. It bridges with dips. As soldering, a technique called super solder soldering, which can perform fine processing, has been developed. However, even when such processing is performed, it is not always easy if the pattern is fine, Typically, more than one treatment cannot be performed on the substrate.

【0006】また、その他の処理として、Cu箔等のプ
リント金属の耐熱処理(耐熱プリフラックス処理)を要
することがあるが、このような処理についても、上記と
同様のことが言える。
[0006] In addition, heat treatment (heat-resistant pre-flux treatment) of printed metal such as Cu foil may be required as another treatment. The same can be said for such treatment.

【0007】[0007]

【発明の目的】本発明は上記問題点を解決して、基板上
に複数の処理を行うことを可能ならしめた基板処理方
、及びこれを用いた実装基板の製造方法を提供するこ
とを目的とする。
SUMMARY OF THE INVENTION It is an object of the present invention to solve the above problems and to provide a substrate processing method capable of performing a plurality of processes on a substrate and a method of manufacturing a mounting substrate using the same. And

【0008】[0008]

【課題を解決するための手段】本出願の各請求項の発明
は、下記構成をとることによって、上記目的を達成する
ものである。
Means for Solving the Problems The invention of each claim of the present application achieves the above object by adopting the following constitution.

【0009】本出願の請求項1の発明は、被処理基板上
に、複数種類の処理を施す基板表面処理方法において、
光照射により現像除去可能となる感光性組成物で被処理
面の要部全体をおおい、第1の処理工程で、前記感光性
組成物に対して第1の被処理面を露出させ、第1の処理
を行い、次に第2の処理工程で、同一の前記感光性組成
物に対して第2の被処理面を露出させ、前記第1の処理
と異なる第2の処理を行い、前記第1および第2の処理
は、それぞれ、金メッキ処理、はんだ処理、耐熱処理の
いずれかである基板表面処理方法であって、これにより
上記目的を達成するものである。
[0009] The invention according to claim 1 of the present application is a method for manufacturing a semiconductor device on a substrate to be processed.
In the substrate surface treatment method of performing a plurality of types of treatment,
Treated with a photosensitive composition that can be developed and removed by light irradiation
Covering the main part of the surface, and in the first processing step, the photosensitive
Exposing a first surface to be treated to the composition;
And then in a second processing step, the same photosensitive composition
Exposing a second surface to be processed to an object;
A second process different from the first and second processes
Are gold plating, soldering, and heat treatment, respectively.
Any one of the substrate surface treatment methods,
The above object is achieved.

【0010】本出願の請求項2の発明は、前記被処理基
板には、1mm未満のギャップを有するパターン、ある
いは1mm未満のパターン幅を有するパターンが形成さ
れた請求項1に記載の基板表面処理方法であって、これ
により上記目的を達成するものである。
[0010] The invention according to claim 2 of the present application is characterized in that:
The plate has a pattern, with a gap of less than 1 mm
Or a pattern having a pattern width of less than 1 mm is formed.
The substrate surface treatment method according to claim 1, wherein
This achieves the above object.

【0011】本出願の請求項3の発明は、前記被処理基
板は、プリント回路基板である請求項1または2に記載
の基板表面処理方法であって、これにより上記目的を達
成するものである。
[0011] The invention according to claim 3 of the present application is characterized in that
3. The board according to claim 1, wherein the board is a printed circuit board.
Substrate surface treatment method, thereby achieving the above object.
Is what it does.

【0012】[0012]

【作用】本発明によれば、全面に形成した感光性組成物
を、必要な処理工程毎に必要な被処理面について除去し
て、その部分を露出させ、それぞれの処理を行うように
できる。よって本発明により複数の基板処理が可能であ
り、複数の金属処理も可能である。
According to the present invention, the photosensitive composition formed on the entire surface can be removed from the required surface to be processed in each required processing step, and that portion can be exposed to carry out each processing. Thus, a plurality of substrate treatments and a plurality of metal treatments are possible according to the present invention.

【0013】[0013]

【実施例】次に、本発明の実施例について、図面を参照
して説明する。但し当然のことではあるが本発明は以下
の実施例により限定を受けるものではない。
Next, embodiments of the present invention will be described with reference to the drawings. However, needless to say, the present invention is not limited by the following examples.

【0014】実施例1 本実施例は、プリント回路基板上のCu箔に、金メッキ
処理と、スーパーソルダー印刷によるはんだ処理の双方
の金属処理を行い、これにより実装基板を得る場合につ
いて、本発明を適用したものである。
[0014] Example 1 This example, a Cu foil on the printed circuit board, and gold plating, the case where have rows both metal processing soldering by super solder printing, thereby obtaining a mounting substrate, the present invention Is applied.

【0015】本実施例において、基板作成は以下の
(A)〜(F)の手順で行う。
In this embodiment, the substrate is prepared by the following procedures (A) to (F).

【0016】(A)基板1全面上に、光照射により現像
除去可能とする感光性組成物として、この種のレジスト
5を形成し、まず、通常の手順でワイヤボンディング用
金メッキ部分を含む面をレジスト開口する。これが第1
の処理工程(ここでは金メッキ処理工程)を行う被処理
面を露出させる工程である。これにより図1(a)に図
示のようにする。図1中、21,22はCu箔であり、Cu
箔21とCu箔22とは別の処理(つまり金メッキ処理とは
んだ処理)を行うべきものである。即ちこの工程におい
ては、次の第2の処理(ここでは予備はんだ処理、特に
スーパーソルダー処理)を行う部分のレジストは、その
まま基板1上に残す。露光・現像後も基板は暗(レジス
トの露光波長について暗のままの意味である。以下同
じ)のまま、次のメッキ工程へ移る。
(A) A resist 5 of this type is formed on the entire surface of the substrate 1 as a photosensitive composition that can be developed and removed by light irradiation. Open resist. This is the first
This is a step of exposing the surface to be processed in which the processing step (here, the gold plating processing step) is performed. This results in the state shown in FIG. In FIG. 1, reference numerals 21 and 22 denote Cu foils.
The foil 21 and the Cu foil 22 should be subjected to different treatments (that is, gold plating and soldering). That is, in this step, the resist for the portion where the next second process (preliminary soldering process, especially super soldering process) is performed is left on the substrate 1 as it is. After the exposure and development, the substrate is transferred to the next plating step while the substrate remains dark (meaning that the exposure wavelength of the resist remains dark; the same applies hereinafter).

【0017】(B)暗所のまま無電解金メッキを行う。
これが本実施例における第1の処理工程である。これに
より図1(b)のように、第1の処理61(金メッキ処
理)が施された基板1が得られる。この時点では、まだ
レジスト5はキュア(硬化)されていないものとする。
(B) Electroless gold plating is performed in a dark place.
This is the first processing step in this embodiment. Thus, as shown in FIG. 1B, the substrate 1 on which the first process 61 (gold plating process) has been performed is obtained. At this point, it is assumed that the resist 5 has not been cured (cured) yet.

【0018】(C)次いで、第2の処理であるはんだ処
理を行いたい部分を、図1(c)に示すようにマスク8
を用いて露光する。露光光を符号7で示す。
(C) Next, the portion to be subjected to the soldering, which is the second process, is covered with a mask 8 as shown in FIG.
Exposure using. Exposure light is indicated by reference numeral 7.

【0019】(D)現像することによって、図1(d)
に示すように、第2の処理であるはんだ処理を行うべき
部分のCu箔22が露出する。
(D) By developing, as shown in FIG.
As shown in (2), a portion of the Cu foil 22 where solder processing as the second processing is to be performed is exposed.

【0020】(E)次に、はんだ材を塗布して、熱処理
することにより、必要部の表面にのみはんだを形成す
る。例えば、いわゆるスーパーソルダーをはんだ処理部
分にベタ印刷する。スーパーソルダー印刷は、均一には
んだ塗布ができるので有利である。これにより図1
(e)の構造とする。
(E) Next, a solder material is applied and heat-treated to form a solder only on the surface of the necessary part. For example, a so-called super solder is solid-printed on a portion to be soldered. Super solder printing is advantageous because solder can be applied uniformly. FIG. 1
The structure shown in FIG.

【0021】(F)次に、スーパーソルダーを熱処理す
ることにより、Cu箔22の部分にのみはんだ63が残り、
ブリッジなどもなく、はんだメッキと同等の処理ができ
る。
(F) Next, by heat-treating the super solder, the solder 63 remains only in the portion of the Cu foil 22,
There is no bridge, and the same processing as solder plating can be performed.

【0022】上記により得られた被処理基板1の平面
を、図2に示す。必要な部分にのみ第1の処理61である
金メッキ処理が施され、同じく必要な部分にのみ第2の
処理により得られたはんだ63が形成されている。その他
の部分はこの状態では未だレジスト5におおわれてい
る。
FIG. 2 shows a plane of the substrate 1 to be processed obtained as described above. Only necessary portions are subjected to a gold plating process as a first process 61, and only necessary portions are formed with solders 63 obtained by the second process. Other portions are still covered with the resist 5 in this state.

【0023】更に、他のCu箔部分に耐熱プリフラック
ス処理等の別の処理を行いたいときは、必要部分に光照
射して露光・現像し、レジスト開口して処理部を塗布
し、更に加熱するなどして、その処理を行うことができ
る。
Further, when another processing such as heat-resistant pre-flux processing is desired to be performed on other Cu foil portions, the required portions are exposed and developed by irradiating light, a resist opening is provided, a processing portion is applied, and further heating is performed. By doing so, the processing can be performed.

【0024】本実施例のCu箔21,22によるパターン
は、そのパターンギャップ及びパターン幅はいずれも1
mm未満(特に75μmギャップ、75μm幅)であり、処
理が困難な場合であるが、本実施例により複数の金属処
理が可能ならしめられ、しかも良好に処理が達成でき
た。
The pattern formed by the Cu foils 21 and 22 of this embodiment has a pattern gap and a pattern width of 1 respectively.
Although it is less than 1 mm (especially a gap of 75 μm and a width of 75 μm) and the processing is difficult, a plurality of metal treatments can be performed according to the present embodiment, and the processing can be achieved satisfactorily.

【0025】上述の如く、本実施例よれば、基板の予備
はんだ作成(ソルダーレジスト作成)時に2段露光する
ことにより、同一基板上に金メッキ処理とはんだ処理を
可能にした。さらに銅箔上に、次工程のリフロー処理な
どのために予め耐熱処理する耐熱プリフラックス処理も
可能であり、3種類の基板処理も可能である。これら
が、レジストの2段露光(ないし多段露光)を用いるこ
とによって、可能となったものである。
As described above, according to the present embodiment, gold plating and soldering can be performed on the same substrate by performing two-step exposure when preparing the preliminary solder (solder resist) for the substrate. Further, a heat-resistant pre-flux treatment in which a heat-resistant treatment is performed on the copper foil in advance for a reflow treatment in the next step is also possible, and three types of substrate treatments are also possible. These are made possible by using two-step exposure (or multi-step exposure) of the resist.

【0026】[0026]

【発明の効果】本発明の基板処理方法及び実装基板の製
造方法によれば、基板上に複数の処理を行うことが可能
ならしめられるという効果がもたらされる。
According to the present invention, there is provided a substrate processing method and a method for manufacturing a mounting substrate.
According to the manufacturing method , there is an effect that a plurality of processes can be performed on the substrate.

【図面の簡単な説明】[Brief description of the drawings]

【図1】実施例1の工程を順に断面図で示すものであ
る。
FIG. 1 is a cross-sectional view showing the steps of Example 1 in order.

【図2】実施例1の被処理基板の平面図である。FIG. 2 is a plan view of a substrate to be processed according to the first embodiment.

【図3】従来技術を示す図である。FIG. 3 is a diagram showing a conventional technique.

【符号の説明】[Explanation of symbols]

1 基板 21,22 Cu箔(パターン) 61 第1の処理(金メッキ処理) 62 第2の処理(スーパーソルダー印刷はんだ処理) 63 (第2の処理により得られた)はんだ Reference Signs List 1 substrate 21, 22 Cu foil (pattern) 61 First treatment (gold plating treatment) 62 Second treatment (super solder printing solder treatment) 63 Solder (obtained by second treatment)

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】被処理基板上に、複数種類の処理を施す基
板表面処理方法において、 光照射により現像除去可能となる感光性組成物で被処理
面の要部全体をおおい、第1の処理工程で、前記感光性
組成物に対して第1の被処理面を露出させ、第1の処理
を行い、次に第2の処理工程で、同一の前記感光性組成物に対し
て第2の被処理面を露出させ、前記第1の処理と異なる
第2の処理を行い、 前記第1および第2の処理は、それぞれ、金メッキ処
理、はんだ処理、耐熱処理のいずれかである 基板表面処
理方法。
1. A substrate surface treatment method for performing a plurality of types of treatments on a substrate to be treated, wherein a first portion of the surface to be treated is covered with a photosensitive composition which can be developed and removed by light irradiation. In the step, a first processing surface is exposed to the photosensitive composition, a first processing is performed, and then, in a second processing step, the same photosensitive composition is exposed.
Exposes the second surface to be processed, and is different from the first process.
A second process is performed, and the first and second processes are each performed by a gold plating process.
A substrate surface treatment method that is one of the following :
【請求項2】前記被処理基板には、1mm未満のギャッ
プを有するパターン、あるいは1mm未満のパターン幅
を有するパターンが形成された請求項1に記載の基板表
面処理方法。
2. The processing target substrate has a gap of less than 1 mm.
Pattern with loop or pattern width less than 1mm
The substrate surface treatment method according to claim 1, wherein a pattern having :
【請求項3】前記被処理基板は、プリント回路基板であ
請求項1または2に記載の基板表面処理方法。
3. The substrate to be processed is a printed circuit board.
The substrate surface treatment method according to claim 1 or 2 that.
JP14843692A 1992-05-15 1992-05-15 Substrate processing method and manufacturing method of mounting substrate Expired - Fee Related JP3221060B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14843692A JP3221060B2 (en) 1992-05-15 1992-05-15 Substrate processing method and manufacturing method of mounting substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14843692A JP3221060B2 (en) 1992-05-15 1992-05-15 Substrate processing method and manufacturing method of mounting substrate

Publications (2)

Publication Number Publication Date
JPH05326637A JPH05326637A (en) 1993-12-10
JP3221060B2 true JP3221060B2 (en) 2001-10-22

Family

ID=15452753

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14843692A Expired - Fee Related JP3221060B2 (en) 1992-05-15 1992-05-15 Substrate processing method and manufacturing method of mounting substrate

Country Status (1)

Country Link
JP (1) JP3221060B2 (en)

Also Published As

Publication number Publication date
JPH05326637A (en) 1993-12-10

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