JP3218722B2 - Resist residue removal method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for removing a resist residue in a semiconductor device manufacturing field and the like, and more particularly, to a method for removing a resist mask having a surface hardened layer formed thereon through high dose ion implantation. And a method for completely removing so-called popping residues.

[0002]

2. Description of the Related Art In the field of semiconductor device manufacturing,
Organic polymer material as mask for etching and ion implantation
Resist masks are widely used. Place
The resist mask that is no longer needed after the
In the early days of the removal of the mask, fuming nitric acid or sulfuric acid-peroxide water
Performed by wet etching using a mixed solution
It has recently been_TwoAssin using plasma
Is widely used in mass production sites. This ashing
According to O_TwoO generated in plasma^*, O_x ⁺Etc.
Due to the contribution of chemical species, the organic polymer material burns and CO_x
Is removed in the form of

The ashing described above proceeds relatively easily with respect to a resist mask used for ordinary dry etching. However, in the case of a resist mask used for high-dose ion implantation, the situation is somewhat limited. different. As a specific example of such ion implantation, formation of a source / drain region of a MOS transistor (dose amount 10 ¹⁴
10 about ¹⁵ cm ^-2), forming (dose of 10 ¹⁶ cm approximately ^-2 emitter region of the bipolar transistor), and the like. Removal of the resist mask after such high dose ion implantation is generally very difficult.

It is believed that the reason is that a surface hardened layer is formed on the surface of the resist mask.
The curing of the resist material proceeds by heat generated by ion bombardment, but other factors such as Nu
clear Instruments and Met
hods, B39, p. 809-812 (1989) point out the mechanism of crosslinking by dopants. That is, as an example, when phosphorus is implanted as a dopant into a photoresist material layer having a novolak resin as a base resin, a chemical structure is formed on a surface layer portion of the photoresist material layer around a dose amount of about 10 ¹⁴ to 10 ¹⁵ cm ^-2. Changes occur. Specifically, crosslinking proceeds by a mechanism in which a methylene group in the main chain is replaced by a phosphorus atom, and the phosphorus atom is bonded to a phenol ring of another main chain. When arsenic or boron is ion-implanted as an impurity, crosslinking proceeds by a substantially similar mechanism.

When ordinary O ₂ plasma ashing is performed on a resist mask having such a hardened surface layer,
The surface hardened layer pops and scatters over a wide area on the wafer, resulting in a large amount of so-called popping residues. It is also said that this is due to bumping of the residual solvent contained in the unaltered portion on the lower layer side of the surface hardened layer. The popping residue is large in size as a residue generated in a semiconductor manufacturing process, and if left on a wafer, causes a significant reduction in the yield of semiconductor devices. Therefore, thorough removal is desired. However, it is also said that the dopant is changed into a non-volatile oxide in the hardened surface layer exposed to the O ₂ plasma, and its removal is more and more difficult.

As a solution to the above problem, Japan
anse Journal of Applied P
physics, Vol. 28, No. 10, (1989) 2130
On pages ３６2136, the surface hardened layer was removed by RIE (reactive ion etching) using H ₂ plasma to a position slightly deeper than the projected range of the dopant,
A two-step process of removing the remaining surface hardened layer by downflow ashing or the like has been proposed. According to this method, the surface hardened layer can be removed without generating particles or residues. It is believed that this is because active species in the H ₂ plasma cut chemical bonds in the hardened surface layer, and H atoms combine with dopants to generate volatile hydrides. H ₂ plasma R throughout the process
The reason for switching to downflow ashing in the middle without performing IE is to avoid contamination by Na, heavy metal, or the like contained in the resist material layer.

[0007] The above-mentioned technique is to prevent the generation of popping residues beforehand, but a method of removing the generated popping residues has also been considered. For example, C ₂ F
_{6 A} method of performing a plasma treatment by adding a fluorocarbon compound such as (hexafluoroethane) to O ₂ is described in C ₂ F
_The purpose is to decompose the dopant oxide by F ^* dissociated from ₆ and remove it in the form of fluoride.

[0008]

However, the conventional poppi
There are also many issues to be solved in measures to prevent dusting residues. First, the table
The method of removing the surface hardened layer by a two-step process requires less
Both need RIE device and ashing device separately
Or RIE chamber and ashing chamber
And a multi-chamber type device connected to the device is required. I
However, the complexity of such equipment is
Not always preferred. Also, H _TwoPlasma RIE stage
Due to the long floor time, there is a concern that the throughput will decrease.
It is.

On the other hand, in a technique for removing a popping residue by adding a fluorocarbon compound, F
^* It is not always easy to control the amount of generation, and if F ^* is excessive, the base material layer may be eroded. In addition, there is a high possibility that a carbon-based polymer will be formed due to discharge dissociation of the fluorocarbon-based compound, and consequently, in the resist removal process for removing the organic material layer, a contradiction arises that contamination with the organic material occurs again. I can't do it.

Accordingly, an object of the present invention is to provide a resist residue removing method capable of completely removing a popping residue without lowering economy, throughput, and underlayer selectivity.

[0011]

Resist residue according to the present invention, in order to solve the problems]
The residue removing method is proposed to achieve the above object, and includes a step of ashing a resist mask having a surface hardened layer generated by ion irradiation;
By performing the plasma treatment using _{the 2 F 2, SF 2, SF} 4, at least one mixed gas containing the _{O 2} sulfur fluoride selected from S _{2 F 10,} derived from the surface hardened layer Removing the generated residue.

The present invention is also characterized in that the mixed gas contains H ₂ or H ₂ O.

The present invention is further characterized in that at least the plasma treatment is performed while applying elastic vibration to the substrate holding the residue.

[0014]

The present invention is based on the idea of removing the popping residue generated on the wafer after ashing of the resist mask by F ^* . However, since it is necessary to ensure a sufficiently large underlayer selectivity, F ^* must never be generated in excess, and even if sedimentary by-products are formed at this time, particle by these by-products may cause contamination. It must not happen. As a result of considering these points, in the present invention, at least one kind of fluoride selected from S ₂ F ₂ , SF ₂ , SF ₄ and S ₂ F ₁₀ is used as a source of F ^* instead of a conventional fluorocarbon compound. with sulfur, adding this to O _2.

The above sulfur fluoride is a compound proposed by the present inventors as an etching gas for a silicon oxide-based material layer in Japanese Patent Application Laid-Open No. 4-84427, and releases F ^* under discharge dissociation conditions. be able to. Moreover, these sulfur fluorides have a higher molecular S / F ratio (ratio between the number of S atoms and the number of F atoms) than SF ₆ (sulfur hexafluoride) which has been well known in the field of dry etching. Therefore, the amount of F ^* produced per molecule is small. Therefore, it is relatively easy to control the generation amount of F ^{* in} the plasma, and it is possible to minimize the erosion of the base.

By the way, free S (sulfur) is by-produced from the above sulfur fluoride with the release of F ^* . The present inventors have experimentally confirmed that S is sublimated by heating to about 90 ° C. or higher under a high vacuum where ordinary dry etching is performed. In the resist ashing and subsequent popping residue removal steps, the wafer is heated to approximately 200 ° C. or higher, so that S does not remain on the wafer at all, and therefore cannot cause particle contamination.

In addition, the above sulfur fluoride generally has higher F ^* generation efficiency than the conventionally used fluorocarbon compounds. This is because, when the magnitude of the interatomic bond energy is compared, the SF bond (377 kJ / mo)
It can easily be inferred from the fact that 1) is smaller than the CF bond (448 kJ / mol). This means that the amount of sulfur fluoride to be added is relatively small with respect to O ₂ which is a main component of the mixed gas for removing the popping residue.

The above is the basic idea of the present invention.
According to the second aspect of the present invention, H ₂ or H ₂ O (steam) is further added to the mixed gas. This is based on the concept of removing the hardened layer by H ₂ plasma RIE described in the prior art, and in addition to the decomposition action of the hardened layer by O ₂ plasma ashing and F ^* , the hardening of the hardened layer by H ^* Attempts are also made to decompose the layers. H ^* also has the effect of capturing a part of F ^* and removing it in the form of HF (hydrofluoric acid).
^* It is also possible to control the amount of production more precisely.

According to the third aspect of the present invention, in the plasma processing step for removing at least the popping residue, elastic vibration is applied to the wafer. There are still many unknown reasons why it is difficult to remove the popping residue, but one of the reasons is that this popping residue is extremely large as a residue generated in the semiconductor process and has a large contact area with the wafer. It is believed that. When an elastic vibration is applied to a wafer as in the present invention, if the movement speed of the wafer due to the vibration is higher than the speed of the particles incident from the plasma, the relative speed of the particles increases and the kinetic energy increases. become. Thereby, peeling of the popping residue can be physically promoted. In addition, by increasing the probability of collision between the popping residue and the active species in the plasma, or by causing the etching species adsorbed on the surface of the popping residue to resonately absorb elastic vibrations, a chemical reaction or reaction product is desorbed. Separation can be promoted. With the above effects, the efficiency of removing the popping residue is greatly improved.

The elastic vibration may be applied in the resist mask ashing step in the same manner. In this case, there is an added advantage that the ashing reaction is promoted and the ashing speed is increased.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of the present invention will be described.

Embodiment 1 In this embodiment, the present invention is applied to a process for manufacturing a CMOS transistor, and a resist mask used for ion implantation of arsenic (As) for forming source / drain regions of an nMOS transistor is used. after ashing with ₂ / N ₂ mixed gas, popping residue generated on the wafer O ₂
This is an example of removal by plasma treatment using a / S ₂ F ₂ mixed gas. This process is illustrated in FIGS. 1 (a) through (d).
This will be described with reference to FIG.

As shown in FIG. 1A, the wafer used as a sample is subjected to ion implantation for forming a source / drain region of an nMOS transistor, and a region for forming a pMOS transistor is formed by a resist mask. 7. To briefly explain the steps so far, a ν-type (low-concentration n-type) silicon substrate (1; ν-e in the figure) formed by epitaxial growth
pi. ), A p-well 2 serving as an nMOS transistor formation region and an n-well 3 serving as a pMOS transistor formation region are formed by ion implantation, respectively.
Subsequently, field oxide film 4 and gate oxide films 5a and 5b made of silicon oxide are formed by selective oxidation and surface oxidation.
And gate electrodes 6a and 6b made of a polycrystalline silicon layer or a polycide film are formed on the gate oxide films 5a and 5b, respectively. Furthermore, a novolak-based positive photoresist (trade name: TSM)
R-V3; manufactured by Tokyo Ohka Kogyo Co., Ltd.), and g-ray exposure and development were performed to form a resist mask 7 in the formation region of the pMOS transistor, that is, at least the region covering the gate oxide film 5b and the gate electrode 6b. .

Next, for example, arsenic (A
s) with an implantation energy of 60 keV and a dose of 1 × 10¹⁶
/ Cm^TwoThe ion implantation was performed under the following conditions. As a result, FIG.
(B) As shown in FIG.
In the region, the gate electrode 6a and the field oxide film
4 is used as a mask and n is self-aligned in the p-well 2.
⁺Form source / drain regions 8 were formed. At the same time
In the pMOS transistor formation region, the resist
Phenol in the photoresist material on the surface of the mask 7
The ring was cross-linked with As to form a hardened surface layer 9. this
The thickness of the surface hardened layer 9 was about 250 nm.

Next, the above-mentioned wafer is set in an ashing chamber of a microwave discharge type plasma ashing apparatus, and as an example, a resist mask 7 is formed under the following conditions.
Ashing. O ₂ flow rate 800 SCCM N ₂ flow rate 200 SCCM Gas pressure 266 Pa Microwave power 1 kW (13.56 MH
z) Wafer temperature 250 ° C. In this step, portions of the resist mask 7 that have not been altered by ion implantation were promptly removed at a rate of about 1 μm / min, but as shown in FIG. The popping residue 9a derived from the surface hardened layer 9 was scattered over a wide area and adhered to the wafer. It is considered that this popping residue mainly contains an oxide of As, which is a dopant, and the like.

Thus, while keeping the wafer in the same ashing chamber, the discharge conditions were switched as follows, for example, to remove the popping residue 9a. O ₂ flow rate 950 SCCM S ₂ F ₂ flow rate 50 SCCM Gas pressure 133 Pa Microwave power 1 kW (13.56 MH
z) Wafer temperature 250 ° C. In this step, A ^{* is determined} by F ^* generated by dissociation from S ₂ F _2.
The oxide of s was changed to a fluoride of As, and as shown in FIG. 1D, the popping residue 9a could be quickly removed. Under the above conditions, the flow rate ratio of S ₂ F ₂ was relatively small, and the amount of generated F ^* was never excessive, so that an extremely high selectivity with respect to the gate oxide films 5a and 5b could be maintained. At this time, free S atoms were generated in the plasma, but no S was deposited on the wafer heated to 250 ° C.

Embodiment 2 In this embodiment, in a similar CMOS process, a resist mask used for phosphorus (P) ion implantation is changed to O ₂ /
This is an example in which after ashing is performed using a N ₂ mixed gas, a popping residue is removed using an O ₂ / SF ₄ mixed gas.
The reference drawing is the same as that of FIG. 1 described above, except that A in FIG.
s ⁺ is P ⁺ in the present embodiment.

First, phosphorus (P) was implanted into the same wafer as that shown in FIG.
Ion implantation was performed under the conditions of eV and a dose of 1 × 10 ¹⁶ / cm ² . As a result, as shown in FIG.
A surface hardened layer 9 was formed on the surface of the resist mask 7.

Next, the wafer was set in a microwave discharge type plasma ashing apparatus, and the resist mask 7 was ashed under the following conditions as an example. O ₂ flow rate 2000 SCCM N ₂ flow rate 200 SCCM Gas pressure 266 Pa Microwave power 1 kW (13.56 MH
z) Wafer temperature 250 ° C. Under the above conditions, the flow rate ratio of O ₂ is considerably higher than that of the embodiment. This is because when P is used as a dopant as generally known, As is used. This is because the fact that the degree of surface hardening of the resist mask 7 is greater than in the case where the resist mask 7 is used. Also in this process, FIG.
As shown in (c), a large amount of the popping residue 9a was generated.

Therefore, while keeping the wafer in the same ashing chamber, the discharge conditions were switched as follows as an example, and the popping residue 9a was removed. O ₂ flow rate 950 SCCM SF ₄ flow rate 50 SCCM Gas pressure 266 Pa Microwave power 1 kW (13.56 MH
z) Wafer temperature: 250 ° C. Since SF ₄ is a liquid substance at room temperature, it was vaporized by bubbling using He gas and then introduced into an ashing chamber. According to this embodiment,
The popping residue 9a could be removed promptly.

Embodiment 3 In this embodiment, the resist mask used for the ion implantation of phosphorus (P) is ashed by using an O ₂ / N ₂ mixed gas in the same manner as in Embodiment 2, and the popping residue is removed by O _2. / SF ₄ /
This is an example of removal using an H ₂ O mixed gas. Resist ・
Steps until the mask 7 is ashed are the same as those in the second embodiment.

In this embodiment, next, as an example, the popping residue 9a was removed under the following conditions. O ₂ flow rate 950 SCCM SF ₄ flow rate 50 SCCM H ₂ O flow rate 50 SCCM Gas pressure 266 Pa Microwave power 1 kW (13.56 MH
z) Wafer temperature: 250 ° C. In this step, a part of the oxide constituting the surface hardened layer 9a is hydrogenated due to the contribution of H ^* generated from H ₂ O, and is removed more quickly than in Example 2. We were able to.

Embodiment 4 In this embodiment, an ultrasonic vibrator is incorporated as a means for applying elastic vibration to a wafer stage of a microwave discharge type plasma ashing apparatus, and the ultrasonic vibration is applied to the wafer to remove popping residues. I went while giving.

First, a schematic configuration of the microwave plasma ashing apparatus used in this embodiment is shown in FIG.
The microwave plasma ashing apparatus 100 uses a microwave (2.45 GHz) generated from the magnetron 11.
z) is guided by the waveguide 12 to irradiate the bell jar 13 made of quartz, and the ashing gas supplied from the directions of arrows B ₁ and B ₂ through the gas supply pipe 16 is dissociated in the bell jar 13 to generate plasma. This is an apparatus of a method of ashing a resist mask on a wafer 18. The bell jar 13 is connected to a sample chamber 14 that accommodates a wafer stage 17, and is evacuated to a high vacuum in the direction of arrow A through an exhaust port 15 opened at the bottom of the sample chamber 14. The wafer stage 17 has a variable output type D
Quartz piezoelectric ultrasonic vibrator 1 connected to C power supply 20
9 is built in, so that ultrasonic vibration of a predetermined frequency can be applied to the wafer 18.

Using the microwave plasma ashing apparatus 100 described above, ashing of the resist mask and removal of the popping residue were actually performed. The used sample wafer is the same as that shown in FIG. 1B, and the surface layer of the resist mask 7 is implanted with As ⁺ ions.
The surface hardened layer 9 is formed. An example of the ashing condition is shown below.

O ₂ flow rate 800 SCCM N ₂ flow rate 200 SCCM Gas pressure 266 Pa Microwave power 1 kW (13.56 MH)
z) Wafer temperature 300 ° C. In this step, the ashing speed was increased to about 1.5 μm / min because the wafer temperature was higher than that in Example 1, but the resist mask 7 was altered by ion implantation. Missing parts were promptly removed. However, FIG.
A large popping residue 9a as shown in (c) remained on the wafer.

Therefore, as an example, the discharge conditions were switched as follows, and the popping residue 9a was removed. O ₂ flow rate 950 SCCM S ₂ F ₂ flow rate 50 SCCM Gas pressure 133 Pa Microwave power 1 kW (13.56 M
Hz) Wafer temperature 250 ° C. Ultrasonic vibrator applied power 200 W Here, the oscillation frequency of the ultrasonic vibrator 19 was set to 20 kHz. These conditions corresponded to those obtained by applying ultrasonic vibration to the conditions described in Example 1, and the popping residue 9a could be removed more quickly than in Example 1.

Example 5 In this example, a parallel plate type plasma ashing apparatus was used, an ultrasonic oscillator was built in the wafer stage, and removal of popping residues was performed while applying ultrasonic vibration to the wafer. .

First, FIG. 3 shows a schematic configuration of a parallel plate type plasma ashing apparatus used in this embodiment.
This parallel plate type plasma ashing apparatus 101 has a configuration in which an upper electrode 33 and a lower electrode 37 serving also as a wafer stage are arranged inside an ashing chamber 31 to face each other. The inside of the ashing chamber 31 is evacuated to a high vacuum in the direction of arrow C via an exhaust port 32. Further, a gas supply pipe 36 is formed in the upper electrode 33, and ashing gas introduced into the ashing chamber 31 from the direction of arrow D is dissociated by a high-frequency electric field applied between the two electrodes to generate plasma. Generate wafer 38
Ashing the upper resist mask. Here, the high-frequency electric field is applied by a so-called anode coupling method in which the RF power supply 35 is connected to the upper electrode 33 via the blocking capacitor 34. According to this method, a self-bias potential is not applied to the wafer 38 mounted on the lower electrode 37, and isotropic ashing can be performed. In addition, the lower electrode 37 has a built-in quartz piezoelectric ultrasonic vibrator 39 connected to a variable output type DC power supply 40, and can apply ultrasonic vibration of a predetermined frequency to the wafer 38. It has been made like that.

Using the above-mentioned parallel plate type plasma ashing apparatus 101, ashing of the resist mask and removal of the popping residue were actually performed. Table Sample wafers used were the same as those shown in FIG. 1 (b), the surface layer portion of the resist mask 7 by P ⁺ ion implantation
The surface hardened layer 9 is formed. An example of the ashing condition is shown below.

O ₂ flow 2000 SCCM N ₂ flow 200 SCCM Gas pressure 2660 Pa Microwave power 1 kW (13.56 MH
z) Wafer temperature 350 ° C. In this step, the ashing speed was high because of the high temperature treatment, but the popping residue 9a was also scattered over a wide area.

Therefore, as an example, the discharge conditions were switched as follows, and the popping residue 9a was removed. O ₂ flow rate 950 SCCM SF ₄ flow rate 50 SCCM Gas pressure 2660 Pa Microwave power 1 kW (13.56
MHz) Wafer temperature 250 ° C. Ultrasonic vibrator applied power 200 W Here, the oscillation frequency of the ultrasonic vibrator 19 was set to 20 kHz. Also in this example, the popping residue 9a could be efficiently removed.

Although the present invention has been described based on the five embodiments, the present invention is not limited to these embodiments. For example, in the above-described embodiment, the case where an n-type impurity such as As or P is used as a dopant for ion implantation has been described. However, the present invention is similarly applied to a case where a p-type impurity such as boron (B) is used. it can. In general, it is said that the degree of difficulty in removing the surface hardened layer caused by the dopant is higher in the case of the n-type impurity than in the case of the p-type impurity. Therefore, if the surface hardened layer caused by the n-type impurity can be removed well as in the above-described embodiments, the removal of the surface hardened layer caused by the p-type impurity is easier.

In the above embodiment, H ₂ O was added to the mixed gas as a supply source of H ^* . However, when H ₂ , which is another compound defined by the present invention, was added, almost the same effect was obtained. Is obtained. Further, in the above-described embodiment, the piezoelectric ultrasonic vibrator is used as the means for applying elastic vibration, but an electrostrictive vibrator, a magnetostrictive vibrator, or the like can be used as the ultrasonic wave generating source.

In addition, it goes without saying that the configuration of the sample wafer, the ashing condition, the removing condition of the popping residue, the configuration of the plasma ashing apparatus, and the like can be appropriately changed.

[0046]

As is clear from the above description, when the present invention is applied, a surface hardened layer is formed on the surface layer of the resist material layer through high dose ion implantation, and the surface hardened layer is formed after ashing. Even if the resulting popping residue remains on the wafer, it can be completely removed without lowering the base selectivity. In addition, sulfur fluoride, which is a source of F ^* at the time of removing the popping residue, does not generate deposits that cause particle contamination. Further, according to the present invention, the ashing step and the step of removing the popping residue can be continuously performed in the same ashing chamber, and there is no possibility that economic efficiency or throughput is significantly impaired. Further, the processing efficiency can be greatly increased only by making some improvements such as installing an ultrasonic vibrator on the wafer stage.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing a process example in which a resist removing method of the present invention is applied to a CMOS manufacturing process in the order of steps, (a) showing a pMOS formation region covered with a resist mask, (b) () Shows a state in which a surface hardened layer is formed on the surface of the resist mask by implantation of a high dose of As ⁺ into the nMOS formation region, (c) shows a state in which the resist mask has been ashed and popping residues have been generated, and (). d) represents a state in which the popping residue has been removed, respectively.

FIG. 2 is a schematic cross-sectional view showing an example of a configuration of a microwave plasma ashing apparatus used in performing the resist removing method of the present invention.

FIG. 3 is a schematic cross-sectional view showing an example of the configuration of a parallel plate type plasma ashing apparatus used in carrying out the resist removing method of the present invention.

[Explanation of symbols]

2 ... p well 6a, 6b ... gate electrode 7 ... resist mask 8 ... n ⁺ type source / drain region 9 ... surface hardened layer 9a ... popping residue 17 ... wafer -Stages 18, 38-Wafers 19, 39-Ultrasonic vibrators 20, 40-DC power supply 37-Lower electrode 100-Microwave plasma ashing device 101-Parallel plate type Plasma ashing equipment

Claims (3)

(57) [Claims] Ashing a resist mask having a surface hardened layer generated by ion irradiation; and at least one kind of sulfur fluoride selected from S ₂ F ₂ , SF ₂ , SF ₄ and S ₂ F _10. by performing the plasma treatment using a mixed gas containing O _2, a resist residue removal method characterized by a step of removing the residue generated derived from the surface hardened layer. 2. A resist residue removal process of claim 1, wherein the mixed gas is characterized by containing H ₂ or H _{2 O.} Wherein at least said plasma treatment resist residue removal <br/> removed by the method of claim 1 or claim 2, characterized in that while applying elastic vibration to the substrate to hold the residue.