JP3218614B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an insulated gate field effect transistor having a check pattern for measuring contact resistance.

[0002]

2. Description of the Related Art In a conventional insulated gate type field effect transistor (hereinafter abbreviated as "MOS FET"), a high melting point metal or polycrystalline silicon or polycrystalline silicon or a high melting point metal is particularly used as a gate electrode material. In a MOS FET using a metal compound, the gate electrode material itself cannot be used as a bonding pad or a wiring. For this reason, after the gate electrode is pulled out and covered with a silicon oxide film or the like, a through electrode is formed.
An opening called a hole is provided to connect to an aluminum electrode.

A through-hole portion in the above-mentioned conventional MOS FET will be described with reference to FIG. FIG. 3 is a vertical sectional view taken along the line BB of the through-hole portion of the gate of FIG. In FIG. 3, 31 is a silicon substrate, 32 is a silicon oxide film, 3
3 is a gate molybdenum layer, 34 is a PSG oxide film, 35
Is an aluminum electrode (connected to the gate bonding pad). As shown in FIG. 3, an opening C38 called a through hole is provided to connect the gate molybdenum layer 33 and the aluminum electrode 35.

[0004]

SUMMARY OF THE INVENTION Conventional MOS having the above structure
In the FET, it is impossible to measure the contact resistance (hereinafter abbreviated as RC) between the gate electrode and the aluminum electrode of the wiring in a direct-current manner. When the process becomes unstable, it is difficult to select a device having a large RC, that is, a device having poor characteristics. By the way, when a MOS FET is used for a high-frequency amplifier, the magnitude of RC greatly affects the amplification factor at the high frequency. However, with conventional MOS FETs, it is not possible to estimate the quality of the amplification factor by checking RC, and when directly measuring the amplification factor at a high frequency, not only is the measuring device complicated, but also the measurement is lengthy. There is a problem that time is required.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to solve the above-mentioned problems, and in particular, an object of the present invention is to provide an insulating gate having a check pattern for measuring contact resistance. An object of the present invention is to provide a semiconductor device having a G-type field effect transistor.

[0006]

According to the present invention, there is provided a semiconductor device comprising an insulated gate field effect transistor having a through hole for connecting two different metal layers via an insulating film. within the same chip, the same sul - e - have a Le structure, and an insulated gate field effect transistor device
Is a semiconductor device comprising an electrically independent check pattern for measuring contact resistance. Sa
In addition, the check pattern for measuring the contact resistance is two
It has an opening and consists of one gate electrode and two pads.
It is characterized by that.

That is, the MOS FET of the present invention has exactly the same vertical cross-sectional shape as the through-hole portion, which is the connection portion between the gate electrode lead-out portion of the device and the aluminum electrode used for wiring, etc. In addition, a check pattern capable of measuring the contact resistance between the gate electrode portion and the aluminum electrode portion is provided.

As a means for measuring the contact resistance of the check pattern section, a general DC measuring instrument can be used, which can measure in a very short time of about 1 mS.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to FIGS. FIG. 1 is a plan view of a MOS FET according to an embodiment of the present invention, and FIG.
FIG. 3 is a vertical sectional view taken along the line A-B of FIG. 1, and FIG. 3 is a vertical sectional view taken along the line BB of the element through-hole portion 4 of the gate of FIG. As shown in FIG. 1, the element portion of the MOS FET has a gate pad portion 1 and a gate pad portion.
The structure comprises a through hole portion 4, a source pad portion 2 and a drain pad portion 3 of the gate, and further includes a check pattern portion 5.

As shown in FIG. 2, the check pattern section 5 has two openings (openings A36 and B37) and two aluminum electrodes (aluminum electrodes A25 and B2).
6) and one gate electrode (gate molybdenum layer 33)
And

Then, as shown in FIG. 2 and FIG.
The through-hole portion 4 and the check pattern portion 5 of the gate are formed on a silicon substrate 21 and a silicon substrate 32, on which a silicon oxide film 22, a silicon oxide film 32 and a molybdenum layer 23 and a refractory metal layer 33 are formed. The oxide films 24 and 34 are further provided with an aluminum electrode A
25, an aluminum electrode B26, and an aluminum electrode 35 are formed in the same manufacturing process steps as the corresponding ones, and are manufactured so that the film thickness, film quality, and the like are all the same. Also, the apertures (the apertures A36, B37, and C38) for connecting aluminum and molybdenum are the same in size and are provided in the same manner.

In this embodiment, the contact resistance between the gate molybdenum electrode and the aluminum electrode of this element can be easily determined by measuring the DC resistance between the aluminum electrodes A25 and B26 of the check pattern section 5. You can ask. In addition,
Since the measured value includes two through-holes, the measured value is twice as large as that of the present element.

[0013]

As described in detail above, the MOS FET device according to the present invention is provided with the check pattern for measuring the contact resistance. Can be easily measured in a DC manner with this check pattern, and as a result, a remarkable effect that the quality of the amplification factor of this element at a high frequency can be easily estimated. In addition, in the conventional MOS FET, the pass / fail at high frequency is directly measured by the amplification factor.
According to the present invention, it is possible to perform measurement in about 1 mS using a check pattern and a general DC measuring instrument, while the sorting must be performed in about 3 seconds. Has an excellent effect that it can be dramatically reduced.

[Brief description of the drawings]

FIG. 1 is a plan view of a MOS FET according to an embodiment of the present invention.

FIG. 2 is a vertical sectional view taken along the line AA of the check pattern portion in FIG.

FIG. 3 is a cross-sectional view of B- of the gate of FIG. 1;
FIG. 3 is a vertical sectional view taken along line B.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Gate pad part 2 Source pad part 3 Drain pad part 4 Gate through hole part 5 Check pattern part 21 Silicon substrate 22 Silicon oxide film 23 Molybdenum layer 24 PSG oxide film 25 Aluminum electrode A 26 Aluminum electrode B 31 Silicon substrate 32 Silicon oxide film 33 Molybdenum layer 34 PSG oxide film 35 Aluminum electrode 36 Opening A 37 Opening B 38 Opening C

Claims (2)

(57) [Claims] 1. A semiconductor device comprising an insulated gate type field effect transistor having a through hole for connecting two different metal layers via an insulating film, wherein the same through hole is provided in the same chip. have a Le structure, insulated-gate field-effect
A semiconductor device comprising a check pattern for measuring contact resistance , which is electrically independent of the transistor element . 2. A check pattern for measuring the contact resistance.
Has two openings, one gate electrode and two
2. The semiconductor device according to claim 1, wherein the semiconductor device comprises
Place.