JP3214612B2 - Clock synchronous communication device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a clock synchronous communication device.

[0002]

2. Description of the Related Art A clock synchronous (3-wire) serial communication generally used in the related art will be described below.

For example, when transmitting and receiving between a first clock synchronous communication device and a second clock synchronous communication device having an 8-bit transmission / reception buffer, communication is performed by the following operation.

First, a communication clock is selected. At this time, when the internal clock is selected in the first clock synchronous communication device, it is necessary to specify the external clock in the second clock synchronous communication device. If an external clock is designated by the first clock synchronous communication device, the second
In the clock synchronous communication device of (1), it is necessary to specify an internal clock (in the following description, the first clock synchronous communication device (the clock synchronous communication device 1 in FIG. 1) uses the internal clock and the second clock synchronization (This is a case where the clock communication device (the clock synchronous communication device 2 in FIG. 1) operates with an external clock.)

Next, 8-bit transfer is set in the serial transfer bit setting register. For example, when performing 2-bit transfer, 2-bit transfer is set in the serial transfer bit setting register.

[0006] Finally, by setting serial transfer permission in the dedicated register, preparation for serial communication is completed.

[0007] Since the dedicated register is not directly related to the operation of the present invention, a detailed description is omitted.

The start of the communication operation will be described with reference to the drawings.

FIG. 1 is a diagram showing connections between general clock synchronous communication devices.

Here, a description will be given of a case where a clock synchronous communication device 1 and a clock synchronous communication device 2 communicate with each other as shown in FIG.

FIG. 2 is a schematic block diagram of a general clock synchronous communication device.

As shown in FIG. 2, the clock synchronous communication device 1 or 2 comprises an internal bus 3, a direction control circuit 4, a serial I / O shift register 5, a serial clock counter 6, an interrupt The generator 7 and the serial
It comprises a clock control circuit 8, a selector 9, a serial transfer bit setting register 10, and input / output buffers 11 to 14.

FIG. 10 is a block diagram showing the serial interface shown in FIG.
FIG. 3 is an internal block diagram of a clock control circuit 8;

In this conventional example, the serial clock control circuit 8 comprises a clock output control circuit 15 and a comparator 1
6, a counter 17, and a transfer bit width setting unit 18.

FIG. 3A is an internal block diagram of the interrupt generation circuit 7 shown in FIG.

In this conventional example, an interrupt generation circuit 7
Comprises a count value setting circuit 19 and a comparator 20. In FIG. 3A, the IN of the output of the comparator 20 is shown.
Although TCSI is input to the count value setting circuit 19, in this conventional example, INTCSI is not input to the count value setting circuit 19.

FIG. 9 is an internal block diagram of the count value setting circuit 19 shown in FIG.

In this conventional example, the count value setting circuit 19 includes a transfer bit width setting unit 21.

To start the communication operation, first, "AA" (arbitrary) data is written to the serial I / O shift register 5 of the clock synchronous communication device 2.
At this time, the clock-synchronous communication device 2 is ready for transmission and reception, and waits for an external clock input.

Next, by writing "55" (arbitrary) data into the serial I / O shift register 5 of the clock synchronous communication device 1, a start signal is generated, and the serial clock control circuit 8 In response to the start signal, the output of the external output communication clock and the internal output communication clock is started.

The external output communication clock is output as SCK, and at the same time, the internal output communication clock is output to serial clock counter 6 and serial I / O shift register 5. The output of the external output communication clock and the internal output communication clock in the serial clock control circuit 8 is stopped by a signal from the comparator 16 shown in FIG.

The value set by the transfer bit width setting unit 18 in response to the input of the transfer bit setting signal and the value counted by the counter 17 when the communication clock output from the clock output control circuit 15 rises are input to the comparator 16. The values are input, and the comparator 16 always compares the two input values.

If the result of the comparison is a coincidence, it is determined that the transfer is completed, and a coincidence signal is output to the clock output control circuit 15, and the clock output control circuit 15 stops outputting the communication clock.

Similarly, in the interrupt generation circuit 7 shown in FIG. 2, the count value setting circuit 19 (shown in FIG. 3A)
The transfer bit width setting unit 21 (shown in FIG. 9) receives the transfer bit setting signal and sets the transfer bit width as the transfer count value.
The transfer count number is output to 0 (shown in FIG. 3A).

The comparator 20 always compares the count value generated by the serial clock counter 6 (shown in FIG. 1) with the above-mentioned transfer count number.
If they match, INTCSI is generated to notify the end of the transfer to the outside.

With the above operation, communication is performed as shown in the timing chart of FIG.

Communication in this conventional example is performed according to a flowchart shown in FIG.

[0028]

The problem here is that transmission of 2-bit data (data A, data C) and transmission of 8-bit data (data B,
This is a case where transmission of data D) is performed alternately. At this time, as shown in FIG. 15, before transmitting data B after transmitting data A, before transmitting data C after transmitting data B, and before transmitting data D after transmitting data C. It is necessary to reset the serial transfer bit setting register 10 every time. In a system transferring a large amount of data, the serial transfer bit setting register 10
Access time and the complexity of interrupt processing have been heavy loads.

The present invention has been made in view of the above points, and can reduce the processing time and avoid complicated processing when transmitting data of plural lengths in a clock synchronous communication device. An object of the present invention is to provide a clock synchronous communication device.

[0030]

According to the present invention, in order to achieve the above object, a data length to be transferred is set in advance.
In a clock synchronous communication device that performs data transfer of a plurality of data lengths, the transfer of each of the plurality of data lengths is performed.
Based on the interrupt signal indicating the end, the plurality of data
It is characterized in that data transfer is performed by switching the length .

Further, in the clock synchronous communication device according to claim 1, each of the plurality of data lengths is supported.
Then, the interruption signal is determined.

Further, in the clock synchronous communication device according to claim 1, the determination of the interrupt signal is made by mode data.
Data transmission completion interrupt signal and normal data transmission completion interrupt
It is characterized in that it is a discrimination with the only signal .

The clock synchronous communication device according to claim 1, further comprising a flip-flop circuit for inverting an output when the interrupt signal is input,
The transfer is performed based on the output of the flip-flop circuit .
It is characterized in that the data length of power data is switched.

Further, in clocked communication apparatus according to any one of claims 1 to 4, wherein the transfer all
Type of data length of the feeder data is characterized in that two types.

[0035]

[0036]

Embodiments of the present invention will be described below with reference to the drawings.

The present invention is characterized in that, in the clock synchronous communication device, a circuit capable of changing a transfer bit in real time is added to the serial clock control circuit and the interrupt generation circuit.

FIG. 1 is a diagram showing connections between general clock synchronous communication devices as described above. Also in the embodiment of the present invention, the connection shown in FIG. 1 is made.

Here, a case where the clock synchronous communication device 1 and the clock synchronous communication device 2 communicate with each other as shown in FIG. 1 will be described.

Hereinafter, a first embodiment of the present invention will be described.

In the first embodiment of the present invention, a schematic block diagram of the clock synchronous communication device is the same as that of FIG. 2 described above, and therefore, will be described with reference to FIG.

As shown in FIG. 2, the clock synchronous communication device 1 or 2 includes an internal bus 3, a direction control circuit 4, a serial I / O shift register 5, a serial clock counter 6, an interrupt The generator 7 and the serial
It comprises a clock control circuit 8, a selector 9, a serial transfer bit setting register 10, and input / output buffers 11 to 14.

FIG. 3 shows the interrupt generation circuit 7 shown in FIG.
(A) is an internal block diagram of the interrupt generation circuit 7 shown in FIG. 2, (b) is an internal block diagram of the count value setting circuit 19 shown in (a), (C) is an internal block diagram of the setting signal change circuit 22 shown in (b).

In this embodiment, the interrupt generation circuit 7 includes a count value setting circuit 19 and a comparator 20, and the INTCSI output from the comparator 20 is input to the count value setting circuit 19.

The count value setting circuit 19 includes a setting signal changing circuit 22 and a transfer bit width setting unit 23. The setting signal changing circuit 22 includes a flip-flop circuit 24 and a plurality of logic gates. Is done.

FIG. 4 is an internal block diagram of serial clock control circuit 8 shown in FIG.

In this embodiment, the serial clock control circuit 8 includes a clock output control circuit 25, a comparator 26, a counter 27, and a transfer bit width setting unit 28
And a setting signal change circuit 29.

In FIG. 2, information of serial transfer bit setting register 10 is input to interrupt generation circuit 7 and serial clock control circuit 8, and interrupt generation circuit 7
In the serial clock control circuit 8, based on the input transfer bit setting signal, FIG.
As shown in FIG. 3C, the number of transfer bits is controlled using the INTCSI signal indicating the end of transfer.

In the conventional clock synchronous communication device, the bit width is changed in the serial transfer bit setting register 10, but in the present invention, the bit width is changed in FIG.
As shown in (c), the number of transfer bits can be changed in real time in a small number of logic gates.

Also, in the serial clock control circuit 8 of FIG. 2, the number of transfer bits is controlled by controlling the configuration as shown in FIG.

As shown in FIG. 2, the clock synchronous communication apparatus 1 or 2 according to the first embodiment of the present invention comprises an internal bus 3, a direction control circuit 4, a serial I / O shift register 5, , A serial clock counter 6,
Interrupt generation circuit 7 and serial clock control circuit 8
, Selector 9 and serial transfer bit setting register 1
0 and input / output buffers 11 to 14.

Here, the interrupt generation circuit 7, which is a feature of the present embodiment, comprises a count value setting circuit 19 and a comparator 20, as shown in FIG. As shown in FIG. 3B, the inside of 19 includes a setting signal changing circuit 22 and a transfer bit width setting unit 23. Further, the internal circuit of the setting signal changing circuit 22 is as shown in FIG. Is configured.

As shown in FIG. 4A, the serial clock control circuit 8, which is another feature of the present embodiment, comprises a clock output control circuit 25 and a comparator 26.
, A counter 27, a transfer bit width setting unit 28, and a setting signal changing circuit 29. The setting signal changing circuit 29 has the same configuration as that of FIG.

Next, the operation of the first embodiment of the present invention will be described.

In the first embodiment, a case where data transfer is performed between the clock synchronous communication device 1 according to the present invention and the clock synchronous communication device 2 according to the present invention will be described with reference to FIG.

First, before performing communication, information indicating a transfer mode for alternately transferring 2 bits and 8 bits is written into the serial transfer bit setting register 10 of both clock synchronous communication devices 1 and 2 (prior art). This is performed by writing to the serial transfer bit setting register in the same manner as in the above.)

Next, as in the prior art, a clock used for communication is selected in the dedicated register, and serial transfer is permitted.

With the above operations, the preparation for performing the serial communication is completed.

At this time, when an internal clock is designated by the clock synchronous communication device 1, the clock synchronous communication device 2 needs to designate an external clock. When an external clock is designated by the clock synchronous communication device 1,
The clock synchronous communication device 2 needs to designate an internal clock. (In the present embodiment, the clock synchronous communication device 1 and the clock synchronous communication device 2 operate in the same manner. Unify the expression.).

Next, the start of the transmission operation will be described with reference to FIG.

The clock synchronous communication device 1 has a serial I
When data is written to the / O shift register 5, a start signal is input to the serial clock control circuit 8, and the serial clock control circuit 8 uses the clock selected by the selector 9 as a communication clock, an internal output communication clock, and an external output clock. Start outputting the output communication clock (when the clock synchronous communication device 1 uses an external clock,
No external output communication clock is output. ).

In serial clock counter 6, a counter indicating the number of transfer bits counts up in synchronization with the rise of the clock input from serial clock control circuit 8. The count value counted by the serial clock counter 6 is output to the comparator 20 in the interrupt generation circuit 7.

The other data input to the comparator 20 passes through a setting signal change circuit 22 shown in FIG.
It is generated from a transfer bit width setting unit 23 which is the same circuit as the transfer bit width setting unit 21 of the conventional example shown in FIG.

Here, an internal circuit of the setting signal change circuit 22 which is a feature of the present embodiment will be described.

The setting signal change circuit 22 outputs the information of the current transfer bit to the transfer bit width setting unit 23 according to the information of the input transfer bit setting signal. For example, when performing 8-bit transfer, a signal indicating 8-bit transfer is output to the transfer bit width setting unit 23, and the transfer bit width setting unit 23 that has received the signal indicating 8-bit transfer inputs "8". Output to the comparator 20.

The comparator 20 constantly compares the count value output from the serial clock counter 6 with the value output from the transfer bit width setting unit 23, and when these values match each other. , INTCSI attain an active level and generate an interrupt signal indicating the end of transfer.

The INTCSI is output to the interrupt controller (not shown) as a signal indicating the end of the transfer, and is also output to the setting signal change circuit 22 of the present embodiment to control the number of transfer bits.

FIG. 3C shows an example of a circuit for changing the number of transfer bits.

The setting signal change circuit 22 is composed of a flip-flop circuit 24 and a general logic gate. In the case of the 2-bit and 8-bit alternate transfer mode as described above, FIG. ), The output of the flip-flop circuit 24 is inverted at the rising edge of the interrupt signal (transfer end signal) INTCSI to control the output of the 2-bit transfer signal and the 8-bit transfer signal via the logic gate, The transfer bit width setting unit 23 receiving the signal sets the output count to “2”,
Switch to “8”. With the above operation, 2 bits, 8
Bit-alternate transfer becomes possible.

On the other hand, the serial
In the clock control circuit 8 as well, similarly to the interrupt generation circuit 7, the output signal is controlled by the setting signal change circuit 29.

As described above, in the interrupt generation circuit 7 and the setting signal change circuits 22 and 29 of the serial clock control circuit 8, the transfer bit information output to the transfer bit width setting sections 23 and 28 is switched. Serial communication corresponding to transfer bit switching becomes possible.

FIG. 7 shows a timing chart of the communication at this time.

The communication according to the first embodiment is performed according to a flowchart shown in FIG.

As described above, in the case of the alternate transfer mode of 2 bits and 8 bits, as shown in FIG. 7, at the time of mode data transfer, after the transfer of 2 bits, the interrupt signal (INT)
CSI) indicates the end of 2-bit data transfer. In the next 8-bit data transfer, 8 bits are transferred.
After the end of bit data transfer, an interrupt signal (INTCS
The occurrence of I) ends the 8-bit data transfer.

As described above, in the case of alternate transfer of 2 bits and 8 bits, since the data transfer bit width can be changed in real time in the above-described circuit, access to the serial transfer bit setting register 10 is achieved. It can be lost and efficient communication can be performed.

Although the present invention has been described with reference to alternate data transfer of 2 bits and 8 bits, for example, alternate data transfer of 3 bits and 8 bits, and alternate data transfer of 4 bits and 7 bits are also applicable. The transfer of two patterns alternately can be realized by the same circuit as that described in the first embodiment.

Also, in the switching of the transfer pattern of the three patterns and the four patterns, the FF (flip-flop circuit) in the setting signal change circuit, which is a feature of this embodiment, is set to one.
By adding one and two logic gates, the operation can be realized in the same manner as the operation shown in the first embodiment.

Next, a second embodiment of the present invention will be described.

The clock synchronous communication device 31 according to the second embodiment is configured as shown in FIG. 5. The difference from FIG. 2 is that the signal generated by the interrupt generation circuit 37 is INTCSIM and INTCSID. It is a book.

As shown in FIG. 5, the clock synchronous communication device 31 includes an internal bus 33, a direction control circuit 34, a serial I / O shift register 35, a serial clock counter 36, and an interrupt generation circuit. 37, a serial clock control circuit 38, a selector 39, a serial transfer bit setting register 40, and an input / output buffer 41.
To 44.

FIG. 6 shows the interrupt generation circuit 3 shown in FIG.
7A is an internal block diagram of the interrupt generation circuit 37 shown in FIG. 5, and FIG. 7B is an internal block diagram of the count value setting circuit 49 shown in FIG. , (C) show the setting signal changing circuit 5 shown in (b).
2 is an internal block diagram of FIG.

In this embodiment, as shown in FIG. 6A, the interrupt generation circuit 37 includes a count value setting circuit 49, a comparator 50, and a plurality of logic gates. The output INTCSI is input to the count value setting circuit 49. Also, the count value setting circuit 4
9 and the INTC signal from the comparator 50
Based on the SI and INTC, as shown in FIG.
The SIM and INTCSID are generated and output.

As shown in FIG. 6B, the count value setting circuit 49 includes a setting signal change circuit 52 and a transfer bit width setting unit 53. As shown in FIG. 6C, the setting signal change circuit 52 includes a flip-flop circuit 54 and a plurality of logic gates.

The second embodiment is an example in which interrupt signals are divided according to transfer bit widths of 2 bits and 8 bits. As shown in FIG. 6C, the setting signal changing circuit 5 in the interrupt generating circuit 37 serves as an interrupt signal determining means.
2 is used as a transfer mode signal, and a logical AND of this transfer mode signal and the output of the comparator 50 is performed, thereby generating a mode data transmission completion interrupt signal (INTCSIM) and transmitting normal data. Generation of a completion interrupt signal (INTCSID) can be realized. The operation of the other circuits is the same as that of the first embodiment, and the detailed description is omitted.

FIG. 8 is a timing chart in the case where the interrupt signal is divided into mode data transfer and normal data transfer separately. Dividing this interrupt greatly reduces the software load.

The communication in the first embodiment is performed according to the flowcharts shown in FIGS. 14 (a) and 14 (b).

[0087]

The effects of the present invention are shown in FIGS.
4 (a) and FIG. 14 (b).

In a system using a conventional clock synchronous communication apparatus for performing alternate data transfer of 2 bits and 8 bits, as shown in FIG. 12, in the processing within an interrupt, the transfer bit width is changed every time. Therefore, in software processing in the conventional clock synchronous communication device, a single transfer does not cause a large load, but when transferring a large amount of data, this serial transfer bit setting is performed. It was necessary to change the register 10 every time.

For example, the time required for changing serial transfer bit setting register 10 is as follows when the operating frequency is 20 MHz.
In this case, it takes 100 ns until rewriting is completed.

The setting change time of this register in one data transfer is very small, but 10 μs is required to transfer 100 data, 1 ms is required to transfer 10,000 data, and 1 million data is transferred. 100ms in case
Things time is wasted.

By setting the processing time as shown in the first embodiment of the present invention shown in FIG. 13, the number of transfer bits can be changed in real time, and the register setting change time is set to "0". ".

Further, as in the second embodiment of the present invention, for example, in alternate data transfer of 2 bits and 8 bits, 2 bits indicate data indicating a mode, and 8 bits indicate data to be transferred normally. By enabling different interrupts to be generated at the end of 2-bit transfer and at the end of 8-bit transfer, software processing can be reduced and software processing can be simplified. The software processing at this time is shown in FIG.
This is shown in the software processing according to the second embodiment of the present invention shown in FIG. 14A and FIG.

The effect at this time is that the time for changing the setting of the register can be omitted, and the information of the mode communication mode and the data communication mode is conventionally generally stored in the RAM, and the information is updated every time. Although the mode data and the normal data are discriminated, the operation can be omitted according to the second embodiment. If the operation frequency is 20 MHz and two clocks are required for register change and RAM change, etc. It is possible to reduce the time by 20 μs when transferring 100 data, 2 ms when transferring 10,000 data, and 200 ms when transferring 1 million data.

[Brief description of the drawings]

FIG. 1 is a connection diagram of a general clock synchronous communication device.

FIG. 2 is a configuration diagram of a clock synchronous communication device according to the first embodiment of the present invention and a conventional technology.

3A is an internal configuration diagram of the interrupt generation circuit shown in FIG. 2 according to the present invention and the prior art, and FIG. 3B is an internal configuration diagram of the count value setting circuit shown in FIG. (C) is an internal configuration diagram of the setting signal change circuit shown in (b) according to the present invention.

FIG. 4 is an internal configuration diagram of the serial clock control circuit shown in FIG. 2 according to the present invention;

FIG. 5 is a configuration diagram of a clock synchronous communication device according to a second embodiment of the present invention.

6A is an internal configuration diagram of the interrupt generation circuit shown in FIG. 5 according to the present invention, FIG. 6B is an internal configuration diagram of the count value setting circuit shown in FIG. (C) is an internal configuration diagram of the setting signal change circuit shown in (b) according to the present invention.

FIG. 7 is a diagram showing a timing chart in the clock synchronous communication device according to the first embodiment of the present invention.

FIG. 8 is a diagram showing a timing chart in the clock synchronous communication device according to the second embodiment of the present invention.

FIG. 9 is an internal configuration diagram of a count value setting circuit shown in FIG. 3A according to a conventional example.

FIG. 10 is an internal configuration diagram of the serial clock control circuit shown in FIG. 2 according to a conventional example.

FIG. 11 is a diagram showing a timing chart in a conventional clock synchronous communication device.

FIG. 12 is a diagram showing a flowchart of software processing of a clock synchronous communication device in a conventional example.

FIG. 13 is a diagram illustrating a flowchart of software processing of the clock synchronous communication device according to the first embodiment of the present invention.

FIGS. 14A and 14B are diagrams showing a flowchart of software processing of the clock synchronous communication device according to the second embodiment of the present invention.

FIG. 15 is a diagram illustrating an example of a transfer mode in a clock synchronous communication device.

[Explanation of symbols]

 1, 2, 31 Clock synchronous communication device 3, 33 Internal bus 4, 34 Direction control circuit 5, 35 Serial I / O shift register 6, 36 Serial clock counter 7, 37 Interrupt generation circuit 8, 38 Serial Clock control circuit 9,39 Selector 10,40 Serial transfer bit setting register 11-14,41-44 Input / output buffer 15 Clock output control circuit 16,20,26,50 Comparator 17,27 Counter 18,21,23,28 , 53 transfer bit width setting section 19, 49 count value setting circuit 22, 29, 52 setting signal change circuit 24, 54 flip-flop circuit 25 clock output control circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 29/08 H04L 7/00

Claims (5)

(57) [Claims] A data length to be transferred is set in advance.
In a clock synchronous communication device that performs data transfer of a plurality of data lengths, the transfer of each of the plurality of data lengths is performed.
Based on the interrupt signal indicating the end, the plurality of data
A clock-synchronous communication device characterized in that data is transferred by switching lengths . 2. The method according to claim 2, wherein each of said plurality of data lengths is
2. The clock synchronous communication device according to claim 1 , wherein the interrupt signal is determined. 3. The method according to claim 1, wherein the determination of the interrupt signal is a mode data.
Data transmission interrupt signal and normal data transmission completion interrupt
The clock synchronous communication device according to claim 2, wherein the determination is a signal . Wherein providing the flip-flop circuit for inverting the output by the interrupt signal is input, based on the output of the flip-flop circuit, said transfer all
2. The clock synchronous communication device according to claim 1, wherein the data length of the data is switched. 5. The clock synchronous communication device according to claim 1, wherein the data to be transferred has two types of data length.