JP3214040B2 - Digital gain variable device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital gain variable device applied to a digital / analog converter called a 1-bit digital / analog converter.

[0002]

2. Description of the Related Art Conventionally, a variable gain device for adjusting the level of an output audio signal is provided around a digital / analog converter for converting a digital audio signal into an analog audio signal. FIG. 3 is a diagram showing an example thereof. In the figure, reference numeral 1 denotes a digital audio signal output terminal, and a digital audio signal obtained at the output terminal 1 is supplied to a digital multiplier 2. And
The gain setting signal (digital data) obtained at the gain setting signal input terminal 3 is supplied to the digital multiplier 2 to multiply the digital audio signal level data by the gain setting signal. Then, the multiplied output is supplied to the digital / analog converter 4, and the digital / analog converter 4 converts the digital audio signal into an analog audio signal. Then, the analog audio signal converted by the digital / analog converter 4 is
It is supplied to an analog audio signal output terminal 5.

In this way, before the digital audio signal is converted into an analog signal, the gain is adjusted, and the gain is adjusted only by changing the value of the gain setting signal. Is done.

As another configuration, for example, as shown in FIG. 4, an analog audio signal output from a digital / analog converter 4 is converted into an inverting input of an operational amplifier 6 forming an output circuit via a predetermined resistor. And the non-inverting input terminal of the operational amplifier 6 is grounded. Then, the inverting input terminal side of the operational amplifier 6 is connected to one end of a plurality of semiconductor switches 7a, 7b # 7i composed of transistors and the like. In this case, the gain setting signal of each bit obtained at the input terminals 8a, 8b ‥‥ 8i of the gain setting signal of a plurality of bits is transmitted to the respective semiconductor switches 7a, 7b.
$ 7i is supplied to the control terminal. The other end of each of the semiconductor switches 7a, 7b # 7i is commonly connected through resistors 9a, 9b # 9i having different resistance values, and this connection point is connected to the output terminal of the operational amplifier 6. I do.
Then, the output terminal of the operational amplifier 6 is connected to the analog audio signal output terminal 5.

By doing so, the input terminals 8a, 8
The resistance value of the resistor connecting the inverting input terminal side and the output terminal side of the operational amplifier 6 changes depending on the connection state of the semiconductor switches 7a and 7b # 7i according to the gain setting signal obtained at b ‥‥ 8i. Then, the gain of the analog audio signal obtained at the output terminal 5 changes.

By the way, when such a variable gain device is configured, there is a possibility that the output analog audio signal is deteriorated. That is, as shown in FIG. 3, when digitally attenuating by a digital multiplier, the dynamic range of the digital / analog converter has a limit, so that the distortion increases as the attenuation increases. Further, as shown in FIG. 4, when the gain is switched by an analog switch such as a semiconductor switch, the distortion rate is deteriorated due to the non-linearity of the characteristics of the analog switch, and the sound quality is deteriorated.

In order to solve this problem, the present applicant has previously proposed in Japanese Patent Application No. Hei 2-274709 a variable gain device of this type which does not deteriorate the sound quality.

[0008] This variable gain device will be described.
In this example, gain adjustment is performed using a 1-bit digital / analog converter as a digital / analog converter. First, the 1-bit digital / analog converter will be described. This 1-bit type digital / analog converter can obtain a pulse signal whose number or width changes as a converted output, and supplies the output whose number or width changes to a low-pass filter. By averaging, an analog audio signal is obtained. In this case, the pulse waveform output from the digital / analog converter has either a high level or a low level, and the pulse waveform that changes in number according to the input digital data is pulse number modulation ( PN
M), and those in which the width of the pulse waveform changes are called pulse width modulation (PWM). According to the digital / analog converter of such a system, distortion generated at the time of conversion can be suppressed to a minimum, and a good analog audio signal without distortion can be converted.

FIG. 5 shows an overall configuration of a variable gain device applied to a device using the 1-bit digital / analog converter. In FIG. 5, 1
Reference numeral 1 denotes a digital audio signal input terminal, which supplies a digital audio signal obtained at the digital audio signal input terminal 11 to a 1-bit digital / analog converter 12. The pulse signal converted and output by the digital / analog converter 12 is supplied to the plurality of logic gates 13a, 13b # 13i. As the logic gate, various gate elements such as an AND gate, a tri-state gate, and a flip-flop can be considered. In the following description, the logic gate will be described as an AND gate.

In the figure, 14a, 14b１４14i are:
A gain setting signal input terminal is shown.
Each bit data of the gain setting signal of a plurality of bits is supplied to 14b ‥‥ 14i. In this case, the gain setting signal is supplied from a control circuit (not shown) of the audio equipment in which the digital-to-analog converter is incorporated, and only some bits are set to the high-level signal “1” according to the set gain. , And the other bits are set to the low level signal “0”. And input terminals 14a, 14b
The gain setting signal of each bit obtained at # 14i is supplied to logic gates 13a and 13b # 13i. Then, respective logic gates 13a, 13b #
13i is connected to a resistor 2 having a different resistance value.
0a, 20b ‥‥ 20i. The other ends of the resistors 20a, 20b # 20i are commonly connected to the inverting input terminal of the operational amplifier 21. Then, the non-inverting input terminal of the operational amplifier 21 is grounded, and the inverting input terminal and the output terminal of the operational amplifier 21 are connected to each other.
Connected by a resistor 22.

The output terminal of the operational amplifier 21 is connected to a low-pass filter 23, and the pulse signal supplied from the operational amplifier 21 is averaged by the low-pass filter 23 to obtain an analog audio signal. To supply.

According to the configuration shown in FIG.
The digital audio signal converted into the pulse signal by the analog converter 12 is applied to logic gates 13a, 13b # 13.
The pulse-converted audio signal is output only from the logic gate to which the high-level signal “1” is supplied as the gain setting signal. That is, the low level signal “0” is used as the gain setting signal.
Is always a low level signal "0" regardless of the state of the pulse signal supplied from the digital / analog converter 12 side. And
From the logic gate to which the high-level signal “1” is supplied as the gain setting signal, a logical product output that becomes the high-level signal “1” when the pulse signal is the high-level signal “1” is obtained. Do not change the signal state of the signal.

Therefore, the signal is converted into a pulse signal via a resistor (either of the resistors 20a, 20b # 20i) connected to the logic gate to which the high level signal "1" is supplied as the gain setting signal. The audio signal is supplied to the operational amplifier 21 side, and the level of the pulse signal (that is, the potential of the high-level signal “1”) is adjusted according to the resistance value of the connected resistor. For this reason, the audio signal obtained by averaging by the low-pass filter 23 changes according to the resistance value of the connected resistor, and the gain adjustment is performed by selecting the resistor to be connected by the gain setting signal. It can be carried out.

The gain adjustment performed in this manner is 1
Only the level adjustment of the output pulse of the bit digital / analog converter 12 is performed, and the switching of the resistor itself is also performed by the logical operation by the logic gate, and the distortion is not changed by the adjustment of the gain. A good analog audio signal can be obtained.

[0015]

However, such a gain adjusting device has a disadvantage that the DC level of the analog audio signal obtained at the output terminal 24 fluctuates rapidly during the gain adjustment. That is, the logic gates 13a, 1
When the connection state of the resistor is changed according to the output state of 3b ‥‥ 13i, the output level of the operational amplifier 21 changes. Therefore, when the gain is adjusted, the DC level of the analog audio signal fluctuates, and this level fluctuation becomes noise such as a click sound.

In view of the foregoing, an object of the present invention is to suppress generation of noise such as a click sound at the time of gain adjustment in such a variable gain device.

[0017]

According to the present invention, as shown in FIG. 1, for example, a noise shaping circuit 32, PW, in which the number or width of output pulses changes in response to a digital input signal.
In a digital gain variable device that changes the output gain of the M wave generation circuit 33, the noise shaping circuit 32,
The output of the PWM wave generating circuit 33 is output to a plurality of selecting means 41a to 41d.
44a, 41b to 44b are supplied to one of the input sections of 41i to 44i, and a pulse having a duty of 50% is supplied to a plurality of selecting means 41a to 44a, 41b to 44b.
i to the other input unit, and each of the selecting means 41a-44
a, 41b-44b ‥‥ Selected output of 41i-44i,
A buffer 45a, 45b # 45i and a resistor 46a, 46b # 46i having different constants are supplied to a series circuit, and outputs of the respective resistors 46a, 46b # 46i are supplied to an operational amplifier 47. The amplified output of the low-pass filter 49 is supplied to a low-pass filter 49 to obtain an analog output signal from the output of the low-pass filter 49, and the selection means 41a to 44a, 41b to 44b ‥‥ 41
The gain of the analog output signal is adjusted by selecting the outputs i to 44i.

[0018]

With this arrangement, the data supplied from each selector to the operational amplifier via the series circuit of the buffer and the resistor becomes a pulse synchronized with the clock regardless of the gain adjustment amount. Even if the gain adjustment amount is switched, no sharp fluctuation occurs in the analog average level.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS.

In FIG. 1, reference numeral 31 denotes a digital audio signal input terminal, and a digital audio signal obtained at the digital audio signal input terminal 31 is supplied to a noise shaping circuit 32 constituting a 1-bit digital / analog converter. Then, the digital audio data subjected to the processing such as oversampling and bit compression by the noise shaping circuit 32 is supplied to the PWM wave generation circuit 33. Then, this PWM wave generation circuit 3
In step 3, the PWM wave is converted into a 1-bit PWM wave, and this PWM wave is used as an output of the PWM wave generation circuit 33. A clock obtained at a clock supply terminal 34 is supplied to the PWM wave generation circuit 33.

Reference numeral 35 denotes a 50% duty pulse generation circuit.
Also, the clock obtained at the clock supply terminal 34 is supplied. The 50% duty pulse generation circuit 3
In step 5, a pulse having a duty of 50% is generated. At this time, since the same clock is supplied to the PWM wave generation circuit 33 and the 50% duty pulse generation circuit 35, pulses having the same cycle are output from both circuits 33 and 35.

The PWM wave output from the PWM wave generating circuit 33 is output to a plurality of AND gates 41a, 41b # 4.
1i (i is an unspecified integer, the same applies hereinafter) to one input terminal. Also, a 50% duty pulse generation circuit 35
Output a pulse with a duty of 50%
The gates 42a, 42b are supplied to one input terminal of 42i.

Reference numerals 37a, 37b and 37i denote gain setting data input terminals to which i-bit series gain setting data is supplied from a central control unit (not shown) of the audio equipment. The gain setting data obtained at the data input terminals 37a, 37b # 37i is supplied to the D flip-flop 36. A clock is supplied to the D flip-flop 36 from the clock supply terminal 34. Therefore, the gain setting data is changed by the D flip-flop 36 in synchronization with the clock.

Then, the gain setting data of the i-bit sequence output from the D flip-flop 36 is divided into separate AND gates 41a, 41b # 4 for each bit sequence.
1i, 42a, 42b ‥‥ supplied to 42i. For example,
The bit sequence gain setting data obtained at the terminal 37a is supplied to the other input terminals of the AND gates 41a and 42a, and the bit sequence gain setting data obtained at the terminal 37b is supplied to the other input terminals of the AND gates 41b and 42b. To supply. In this case, each AND gate 42a, 42b
# 42i is supplied with inverted gain setting data. And each AND gate 41a, 41bａ41i
AND output of each AND gate 42a, 42b # 4
The logical product output of 2i and the OR gate 43
a, 43b ‥‥ 43i are supplied to one and the other input terminals.

As described above, AND gates 41a and 41b #
{41i, 42a, 42b} 42i and OR gate 43
a, 43b ‥‥ 43i are connected, so that each O
A selection means for supplying data to only one of the two input terminals of the R gates 43a, 43b # 43i is configured. In this case, the supplied data is selected according to the state of the gain setting data supplied from the D flip-flop 36 side. That is, according to the gain setting data, the PWM
The PWM wave output from the wave generation circuit 33 and the duty 50
Either of the 50% duty pulse output from the% pulse generation circuit 35 and the OR gate 43a, 43b
# 43i, and the supplied pulse is output as it is.

Then, each OR gate 43a, 43b #
The OR output of 43i is supplied to separate D flip-flops 44a, 44b # 44i. Each of the D flip-flops 44a, 44b # 44i has a terminal 38
Supplies a master clock, and the waveform is shaped into a pulse synchronized with the master clock.

Then, each of the D flip-flops 44a, 44
4b ‥‥ 44i are output to separate buffer circuits 4
5a, 45b ‥‥ 45i and resistors 46a, 46b ‥‥ 4
6i. In this case, the constants of the buffer circuits 45a, 45b # 45i and the resistors 46a, 46b # 46i constituting each series circuit are changed.
Then, the outputs of the resistors 46a, 46b # 46i are supplied to the inverting input terminal-of the operational amplifier 47, and the non-inverting input terminal + of the operational amplifier 47 is grounded. Furthermore, the inverting input terminal − and the output terminal of the operational amplifier 47 are connected by a resistor 48. Thus, the operational amplifier 47
, The current addition is performed.

The output obtained by adding the current by the operational amplifier 47 is supplied to a low-pass filter 49 and averaged. The averaged output is output to an analog audio signal output terminal 50.
To supply.

Next, the operation of the circuit thus configured will be described with reference to the timing chart of FIG. Here, in order to simplify the explanation, the buffer circuits 45a, 4
It is assumed that only three series circuits of 5b @ 45i and resistors 46a, 46b # 46i are prepared, and the gain adjustment is performed by selecting the three circuits using the gain adjustment data. Accordingly, here, the circuits (buffer circuits 45a, 45b, 45i, resistors 46a, 46b,
46i) is prepared, a circuit including the buffer circuit 45a and the resistor 46a is used as a first circuit system, a circuit including the buffer circuit 45b and the resistor 46b is used as a second circuit system, and a circuit including the buffer circuit 45i and the resistor 46i is used. The circuit is a third circuit system. By selecting these three circuits, the amount of attenuation is 1/7, 2/7, 3 /
It is assumed that the gain can be adjusted in seven steps of 7, 4/7, 5/7, 6/7, and 7/7. That is, the constants of the buffer circuit 45a and the resistor 46a are selected so as to perform the 4/7 attenuation in the first circuit system, and the buffer circuit 45b and the resistor are controlled so that the 2/7 attenuation is performed in the second circuit system. Table 46
The constant of b is selected, and the constants of the buffer circuit 45i and the resistor 46i are selected so as to perform 1/7 attenuation in the third circuit system.

By selecting the constants of each circuit system in this manner, when all the circuit systems are selected, (4/7) + (2 /
7) + (1/7) = 7/7 = 1, and an attenuation amount of 1/7 to 6/7 can be selected by selecting any one or two circuit systems. Further, when no circuit system is selected, the output state becomes no signal 0.

Next, the change of the output data according to the selection of the circuit system based on the gain adjustment data will be described with reference to FIG. 2. First, as a PWM modulation clock obtained at the terminal 34, FIG. It is assumed that a pulse indicated by A in FIG. Then, it is assumed that the pulse data shown in FIG. 2B is obtained as the output of the PWM wave generation circuit 33. This PW
The M-modulated wave has a duty cycle of -3, -2, -1, 0, +1, +2, +3 with a duty of 50% as a reference 0.
Is one-bit data that changes in seven stages. The output of the pulse generation circuit 35 with a duty of 50%
Duty 50 which is the same as when the WM modulation wave is at the reference 0 level
% Pulses are obtained as shown in FIG.

As described above, since the gain is adjusted by selecting three circuits, the gain setting data obtained at the input terminals 37a to 37i is
The data is 3-bit data, and the first to third circuit systems are selected based on the data of each bit series. Here, the gain setting data obtained at the input terminal 37a is referred to as attenuation data 1 (ATT1 shown in FIG.
The gain setting data obtained at 7b is referred to as attenuation data 2 (ATT2 shown in FIG. 2E), and the gain setting data obtained at the input terminal 37i is referred to as attenuation data 3 (ATT3 shown at F in FIG. 2).

At this time, each of the attenuate data 1, 2, 3 is subjected to PWM by the D flip-flop 36.
The data changes in synchronization with the modulation clock, and becomes data 1, 2, and 3 shown in G, H, and I in FIG.

Then, first, the amount of the attenuate (ATT
When 5/7 is selected as the amount, the 5/7 attenuation amount is obtained by adding the 4/7 attenuation amount by the first circuit system and the 1/7 attenuation amount by the third circuit system (that is, the addition amount). [4/7] + [1/7]). Therefore, according to the attached data 1, 2, 3,
The first circuit system and the third circuit system are selected. That is, the attenuation data 1 and the attenuation data 3 become the high level signal “1”, and the attenuation data 2 become the low level signal “0”. According to this signal state, the AND gate 41a of the first circuit system and the AND gate 41a of the third circuit system
A high level signal "1" is supplied to the other input terminal of the D gate 41i.
The PWM wave supplied to one of the input terminals 1a and 41i is output as it is. Also, A of the second circuit system
A high-level signal “1” obtained by inverting the low-level signal “0” is supplied to the other input terminal of the ND gate 42b.
A 50% duty pulse supplied from the 50% duty pulse generation circuit 35 to one input terminal of the AND gate 42b is output as it is.

Accordingly, the buffer circuit 45a and the resistor 46a constituting the first circuit system and the buffer circuit 45i and the resistor 46i constituting the third circuit system are provided as shown in J and L of FIG. At the output of the PWM wave generation circuit 33
The WM wave is supplied as it is. The buffer circuit 45b and the resistor 46b constituting the second circuit system have a 50% duty pulse generation circuit 35 as shown in FIG.
Are supplied with a 50% duty pulse.

In this state, as the amplified output of the operational amplifier 47, the PWM wave having passed through the first circuit system, the pulse having a duty of 50% having passed through the second circuit system, and the pulse having passed through the third circuit system. The PWM wave is added to obtain a current-amplified signal. Therefore, the amount of P
The WM wave is output from the operational amplifier 47, and the analog audio signal attenuated to the output terminal 50 by 5/7 is obtained by the smoothing by the low-pass filter 49.
In this case, since the data that has passed through the second circuit system is a pulse with a duty of 50%, it is a pulse corresponding to 0 data and does not affect the output of the operational amplifier 47.

Next, as shown in the approximate center of the timing chart of FIG. 2, if 1/7 is selected as the amount of attenuation, the amount of attenuation of 1/7 is reduced by 1/3 by the third circuit system. It is obtained only with an amount of 7 of attenuate. Therefore, the change from the amount of attenuation 5/7 to the amount of attenuation 1/7 is obtained by the change of the attenuation data 1 from the high-level signal "1" to the low-level signal "0". Due to such a change, AND of the third circuit system
The high-level signal "1" is supplied only to the other input terminal of the gate 41i.
The PWM wave supplied to one input terminal 1i is output as it is. Also, A of the first and second circuit systems
A high-level signal "1" obtained by inverting the low-level signal "0" is supplied to the other input terminals of the ND gates 42a and 42b.
A 50% duty pulse supplied to one input terminal of the gates 42a and 42b is output as it is.

In this state, as the amplified output of the operational amplifier 47, the duty 5 that has passed through the first and second circuit systems
The 0% pulse and the PWM wave that has passed through the third circuit system are added to obtain a current-amplified signal. Accordingly, a PWM wave having an attenuation amount of 1/7 is output from the operational amplifier 47, and an analog audio signal attenuated to 1/7 at the output terminal 50 is obtained by smoothing with the low-pass filter 49. Also in this case, the first and second
Is a pulse with a duty of 50%, it is a pulse corresponding to 0 data, and does not affect the output of the operational amplifier 47.

Further, assuming that 6/7 is selected as the amount of attenuation, as shown on the right side of the timing chart of FIG. 2, the amount of attenuation of 6/7 is the amount of attenuation of 4/7 by the first circuit system. And the amount of attenuation of 2/7 by the second circuit system. Therefore, the amount of the attenuate is reduced from 1/7 to 6 /
The change to 7 is a change from low level signal “0” of the attach data 1 and 2 to high level signal “1”,
It is obtained by a change from the high level signal “1” of the attenuation data 3 to the low level signal “0”. With such a change, the AND gates 41a and 41a of the first and second circuit systems
The high-level signal "1" is supplied to the other input terminal of 1b, and the PWM wave supplied to one input terminal of each of the AND gates 41a and 41b is output as it is. Further, the AND gate 42 of the third circuit system
A high-level signal “1” obtained by inverting the low-level signal “0” is supplied to the other input terminal of the i.
A pulse with a duty of 50% supplied from the pulse generation circuit 35 to one input terminal of the AND gate 42i is output as it is.

In this state, as the amplified output of the operational amplifier 47, the PWM wave passing through the first and second circuit systems,
A pulse having a duty of 50% that has passed through the third circuit system is added to obtain a current-amplified signal. Accordingly, a PWM wave having an attenuation amount of 6/7 is output from the operational amplifier 47, and an analog audio signal attenuated to 6/7 at the output terminal 50 is obtained by smoothing with the low-pass filter 49. Also in this case, since the data that has passed through the third circuit system is a pulse with a duty of 50%, it is a pulse corresponding to 0 data,
Does not affect the output of.

As described above, according to the circuit of this embodiment, depending on the state of the attach data 1, 2, and 3, 1/7 to 7/7
Can be freely selected. In addition, all the low level signals “0” are used as the attenuation data 1, 2, 3, and the duty 5
By passing 0% of the pulse, a pulse corresponding to 0 data can be output from the operational amplifier 47 to make a silent state. Such adjustment of the amount of attenuate
Since the processing is performed without lowering the precision of the PWM wave which is digital audio data, the dynamic range of the digital audio data is not impaired.

When adjusting the amount of attenuation (that is, gain adjustment), a pulse having a duty of 50% corresponding to 0 data is passed through a circuit system that does not need to pass a PWM wave. Even if the amount changes, no sharp fluctuation occurs in the average level of the signal supplied to the operational amplifier 47. Therefore, generation of a click sound due to a sudden change in the DC level during gain adjustment is prevented. Further, the attenuating process of the present embodiment does not degrade characteristics in an analog manner,
There is no deterioration of the analog audio signal output from.

In the example shown in FIG. 2, the case where the amount of attenuation is adjusted in seven stages by setting the first and second circuit systems has been described. Gain adjustment becomes possible.

In the above embodiment, the pulse width modulation (PW
Although the present invention is applied to a 1-bit digital / analog converter in which M) is performed, the present invention can be applied to a 1-bit digital / analog converter of another modulation method (such as pulse number modulation).

[0045]

According to the gain varying device of the present invention, data supplied to the operational amplifier from each selector through the series circuit of the buffer and the resistor is synchronized with the clock regardless of the gain adjustment amount. Thus, even if the gain adjustment amount is switched, no sudden change occurs in the analog average level, and generation of a click sound during gain adjustment is prevented.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention.

FIG. 2 is a timing chart for explaining one embodiment;

FIG. 3 is a configuration diagram illustrating an example of a conventional variable gain device.

FIG. 4 is a configuration diagram illustrating an example of a conventional variable gain device.

FIG. 5 is a configuration diagram illustrating an example of a conventional variable gain device.

[Explanation of symbols]

 31 Digital audio signal input terminal 32 Noise shaping circuit 33 PWM wave generation circuit 34 Clock input terminal 35 Duty 50% pulse generation circuit 37a, 37b {37i Gain setting data input terminal 41a, 41b {41i AND gate 42a, 42b} 42i AND gate 43a, 43b ‥‥ 43i OR gate 44a, 44b ‥‥ 44i D flip-flop 45a, 45b ‥‥ 45i Buffer circuit 46a, 46b ‥‥ 46i Resistor 47 Operational amplifier 49 Low-pass filter 50 Analog audio signal output terminal

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H03M 1/00-1/88 H03G 1/00-3/34

Claims (3)

(57) [Claims] 1. A plurality of selecting means, and converts an input digital signal into a 1-bit pulse signal and outputs the signal. One input terminal of each of the plurality of selecting means is connected to one input terminal of each of the plurality of selecting means. Pulse signal conversion means for supplying the converted 1-bit pulse signal; and each selection means for generating a pulse signal representing zero data in the 1-bit pulse signal and constituting the plurality of selection means. A pulse signal generating means for supplying a pulse signal representing the zero data to the other input terminal of each of the plurality of buffer means; a plurality of buffer means to which each selected output of the plurality of selecting means is supplied; and a plurality of buffer means. A plurality of attenuating means having different constants, and all outputs from the plurality of attenuating means are provided, and An operational amplifier whose amplification factor is varied according to different constants; a low-pass filter to which an output from the operational amplifier is supplied to output an analog signal; And a control means for controlling each selection output of the selection means. 2. The digital gain varying device according to claim 1, wherein the pulse signal output from said pulse signal generating means has a duty of 50%. 3. The digital gain according to claim 1, wherein a common clock is supplied to all of said plurality of selecting means, and said plurality of selecting means switches each selected output based on said clock. Variable device.