JPH05259767A - Digital gain variable device - Google Patents

Abstract

PURPOSE:To provide the gain adjustment device in which production of click noise is suppressed at the time of gain adjustment. CONSTITUTION:Outputs of 1-bit system D/A converters 32, 33 are fed to one input section of plural selection means 41a-44a, 41b-44b...41i-44i and a pulse whose duty is 50% is fed to other input section of plural selection means. A selection output of each selection means is fed to a series circuit comprising buffers 45a, 45b...45i and resistors 46a, 46b...46i whose resistance differs from each other and an output of the resistors is fed to an operational amplifier 47. The amplified output of the operational amplifier is fed to a low pass filter 49, an analog output signal is obtained from the output of the low pass filter, the output is selected by the selection means to adjust the gain of the output signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital gain variable device applied to a digital / analog converter called a 1-bit digital / analog converter.

[0002]

2. Description of the Related Art Conventionally, a gain varying device for adjusting the level of an output audio signal has been constructed around a digital / analog converter for converting a digital audio signal into an analog audio signal. FIG. 3 is a diagram showing an example thereof, in which 1 denotes a digital audio signal output terminal, and the digital audio signal obtained at this output terminal 1 is supplied to a digital multiplier 2. And
The gain setting signal (digital data) obtained at the gain setting signal input terminal 3 is supplied to the digital multiplier 2, and the level data of the digital audio signal and the gain setting signal are multiplied. Then, this multiplication output is supplied to the digital / analog converter 4, and the digital / analog converter 4 converts the digital audio signal into an analog audio signal. Then, the analog audio signal converted by the digital / analog converter 4 is converted into
It is supplied to the analog audio signal output terminal 5.

By doing so, the gain adjustment is performed before the digital audio signal is converted into the analog signal, and the gain adjustment is performed only by changing the value of the gain setting signal, and a so-called electronic volume is constructed. To be done.

As another structure, for example, as shown in FIG. 4, an analog audio signal output from the digital / analog converter 4 is input to an inverting side of an operational amplifier 6 forming an output circuit via a predetermined resistor. The non-inverting side input terminal of the operational amplifier 6 is grounded. The inverting input terminal side of the operational amplifier 6 is connected to one end of a plurality of semiconductor switches 7a, 7b ... In this case, the gain setting signal of each bit obtained at the input terminals 8a, 8b ... 8i of the gain setting signal of a plurality of bits is converted to the respective semiconductor switches 7a, 7b.
Supply to the control terminal of 7i. The other end of each of the semiconductor switches 7a, 7b ... 7i is commonly connected through resistors 9a, 9b ... 9i having different resistance values, and this connection point is connected to the output terminal of the operational amplifier 6. To do.
Then, the output terminal of the operational amplifier 6 is connected to the analog audio signal output terminal 5.

By doing so, the input terminals 8a, 8
The resistance value of the resistor that connects the inverting side input terminal side and the output terminal side of the operational amplifier 6 changes depending on the connection state of the semiconductor switches 7a, 7b. Then, the gain of the analog audio signal obtained at the output terminal 5 changes.

By the way, when such a gain varying device is constructed, the analog audio signal outputted may be deteriorated. That is, as shown in FIG. 3, when digitally attenuating by a digital multiplier, the dynamic range of the digital / analog converter has a limit, and thus the distortion rate becomes worse as the attenuation increases. Further, as shown in FIG. 4, when the gain is switched by an analog switch such as a semiconductor switch, the distortion rate is deteriorated due to the non-linearity of the characteristics of the analog switch, and the sound quality is deteriorated.

In order to solve this problem, the present applicant has previously proposed, in Japanese Patent Application No. 2-274709, a gain varying device of this kind which does not deteriorate the sound quality.

Explaining this gain changing device,
In this example, as the digital / analog converter, a gain adjustment is performed using a 1-bit type digital / analog converter. First, the 1-bit type digital / analog converter will be described. This 1-bit digital / analog converter is capable of obtaining a pulse signal whose number or width changes as a converted output, and supplies the output whose number or width of this pulse signal changes to a low-pass filter. An analog audio signal is obtained by performing averaging. In this case, the pulse waveform output from the digital / analog converter is either a high level or a low level, and the number of pulse waveforms that changes according to the input digital data is pulse number modulation ( PN
M), in which the width of the pulse waveform changes, is called pulse width modulation (PWM). According to the digital / analog converter of such a system, distortion generated at the time of conversion can be minimized, and a good analog audio signal without distortion can be converted.

This is a gain variable device applied to the one using this 1-bit type digital / analog converter, and the entire configuration is shown in FIG. In FIG. 5, 1
Reference numeral 1 denotes a digital audio signal input terminal, and the digital audio signal obtained at the digital audio signal input terminal 11 is supplied to a 1-bit digital / analog converter 12. The pulse signal converted and output by the digital / analog converter 12 is supplied to the plurality of logic gates 13a, 13b ... Various gate elements such as an AND gate, a tri-state gate, and a flip-flop can be considered as the logic gate, but the AND gate will be described below.

Further, in the figure, 14a, 14b ...
The gain setting signal input terminal is shown, and this input terminal 14a,
.. 14i are supplied with respective bit data of the gain setting signal of a plurality of bits. In this case, the gain setting signal is supplied from the control circuit (not shown) of the audio device in which the digital / analog converter is incorporated, and only some bits are set to the high level signal “1” according to the gain to be set. ", And the other bits are set to the low level signal" 0 ". Then, the input terminals 14a and 14b
The gain setting signals of the respective bits obtained at 14i are supplied to the logic gates 13a, 13b. Then, the respective logic gates 13a, 13b ...
The output terminal of 13i is a resistor 2 having a different resistance value.
Connect to one end of 0a, 20b ... 20i. The other ends of the resistors 20a, 20b ... 20i are commonly connected to the inverting side input terminal of the operational amplifier 21. Then, the non-inverting side input terminal of the operational amplifier 21 is grounded, and the inverting side input terminal and the output terminal of the operational amplifier 21 are connected to each other.
Connect with a resistor 22.

Then, the output terminal of the operational amplifier 21 is connected to the low-pass filter 23, the pulse signal supplied from the operational amplifier 21 side is averaged by the low-pass filter 23 into an analog audio signal, and this analog audio signal is output terminal 24. Supply to.

According to the configuration shown in FIG. 5, digital / digital
The digital audio signal converted into the pulse signal by the analog converter 12 has logic gates 13a, 13b ...
The pulsed audio signal is output only from the logic gate that is supplied to i and is supplied with the high level signal "1" as the gain setting signal. That is, as the gain setting signal, the low level signal "0"
In the logic gate to which is supplied, the logical product output always becomes the low level signal “0” regardless of the state of the pulse signal supplied from the digital / analog converter 12 side. And
From the logic gate to which the high level signal “1” is supplied as the gain setting signal, a logical product output that becomes the high level signal “1” is obtained when the pulse signal is the high level signal “1”, and the pulse output is output. Do not change the signal state of the signal.

Therefore, a pulse signal is formed through the resistor (any one of the resistors 20a, 20b ... 20i) connected to the logic gate to which the high level signal "1" is supplied as the gain setting signal. The audio signal is supplied to the operational amplifier 21 side, and the level of the pulse signal (that is, the potential of the high level signal "1") is adjusted according to the resistance value of the connected resistor. Therefore, the audio signal obtained by averaging by the low-pass filter 23 changes according to the resistance value of the resistor to which the gain is connected, and the gain adjustment is performed by selecting the resistor to be connected by the gain setting signal. It can be carried out.

The gain adjustment performed in this way is 1
Only the level adjustment of the output pulse of the bit digital / analog converter 12 is performed, the switching of the resistor itself is also performed by the logical operation by the logic gate, and the distortion does not change due to the gain adjustment. A good analog audio signal can be obtained.

[0015]

However, in such a gain adjusting device, there is a disadvantage that the DC level of the analog audio signal obtained at the output terminal 24 rapidly changes during gain adjustment. That is, the logic gates 13a, 1
If the connection state of the resistor is changed depending on the output states of 3b ... 13i, the output level of the operational amplifier 21 will change. Therefore, by performing the gain adjustment, the DC level of the analog audio signal fluctuates, and this level fluctuation becomes noise such as a click sound.

In view of the above points, the present invention has an object of suppressing noise generation such as a click sound at the time of gain adjustment in a gain varying device of this type.

[0017]

According to the present invention, for example, as shown in FIG. 1, a 1-bit type digital / analog converter 32, 33 in which the number or width of output pulses is changed in response to a digital input signal. In a digital gain variable device that changes the output gain, a digital / analog converter 3
The output of 2, 33 is output to a plurality of selecting means 41a to 44a, 41.
b to 44b, ...
.. 44a, 41b to 44b ... 41i to 44i are supplied to the other input section to select each of the selecting means 41a to 44a, 41b.
44b ... Selective outputs of 41i to 44i are transferred to the buffer 45.
a, 45b ...
46i, a series circuit of a, 46b, ... 46i, the outputs of the respective resistors 46a, 46b, ... 46i are supplied to an operational amplifier 47, and the amplified output of the operational amplifier 47 is supplied to a low-pass filter 49. This low pass filter 4
The analog output signal is obtained from the output of 9 and the gain of the analog output signal is adjusted by selecting the output by the selecting means 41a to 44a, 41b to 44b.

[0018]

By doing so, regardless of the gain adjustment amount, the data supplied to the operational amplifier from each selection means through the series circuit of the buffer and the resistor becomes a pulse synchronized with the clock. Even if the gain adjustment amount is switched, the analog average level does not suddenly change.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

In FIG. 1, reference numeral 31 denotes a digital audio signal input terminal, and the digital audio signal obtained at this digital audio signal input terminal 31 is supplied to a noise shaping circuit 32 which constitutes a 1-bit digital / analog converter. Then, the digital audio data that has been subjected to processing such as oversampling and bit compression in the noise shaping circuit 32 is supplied to the PWM wave generation circuit 33. And this PWM wave generation circuit 3
In 3, the PWM wave of 1-bit system is converted, and this PWM wave is used as the output of the digital / analog converter. A clock obtained at the clock supply terminal 34 is supplied to the PWM wave generation circuit 33.

Reference numeral 35 denotes a 50% duty pulse generation circuit, which is a 50% duty pulse generation circuit 35.
Also, the obtained clock is supplied to the clock supply terminal 34. Then, this duty 50% pulse generation circuit 3
In step 5, a pulse having a duty of 50% is generated. At this time, since the same clock is supplied to the PWM wave generation circuit 33 and the 50% duty pulse generation circuit 35, pulses of the same cycle are output from both circuits 33 and 35.

The PWM wave output from the PWM wave generation circuit 33 is converted into a plurality of AND gates 41a, 41b.
1i (i is an unspecified integer; the same applies hereinafter) is supplied to one input terminal. In addition, the duty 50% pulse generation circuit 35
Pulse of 50% duty output by
Supply to one input end of the gates 42a, 42b ... 42i.

Reference numerals 37a, 37b ... 37i denote gain setting data input terminals, which are terminals to which i-bit series gain setting data is supplied from a central control unit (not shown) of the audio equipment. The gain setting data obtained at the data input terminals 37a, 37b ... 37i are supplied to the D flip-flop 36. A clock is supplied to the D flip-flop 36 from the clock supply terminal 34. Therefore, the gain setting data is data that changes in synchronization with the clock in the D flip-flop 36.

The i-bit series gain setting data output from the D flip-flop 36 is provided to AND gates 41a, 41b.
1i, 42a, 42b ... 42i. For example,
The bit series gain setting data obtained at the terminal 37a is supplied to the other input terminals of the AND gates 41a and 42a, and the bit series gain setting data obtained at the terminal 37b is supplied to the other input terminals of the AND gates 41b and 42b. Supply to. In this case, the AND gates 42a and 42b
The gain setting data is inverted and supplied to 42i. And AND gates 41a, 41b ... 41i
AND output of each AND gate 42a, 42b ... 4
2i and the logical product output of
a, 43b, ... 43i are supplied to one and the other input ends.

Thus, the AND gates 41a, 41b.
41i, 42a, 42b ... 42i and OR gate 43
a, 43b, ... 43i are connected to each O
Selection means for supplying data to only one of the two input terminals of the R gates 43a, 43b ... In this case, the supplied data is selected depending on the state of the gain setting data supplied from the D flip-flop 36 side. That is, depending on the gain setting data, the PWM
The PWM wave output by the wave generation circuit 33 and the duty 50
One of the 50% duty pulse output from the% pulse generation circuit 35 and the OR gates 43a, 43b.
... 43i and outputs the supplied pulse as it is.

The OR gates 43a, 43b ...
The logical sum output of 43i is supplied to different D flip-flops 44a, 44b. The D flip-flops 44a, 44b ...
The master clock is supplied from and the waveform is shaped into a pulse synchronized with this master clock.

Then, each D flip-flop 44a, 4
The outputs of 4b ...
45i and resistors 46a, 46b ... 4i
Supply to the series circuit with 6i. In this case, the constants of the buffer circuits 45a, 45b ... 45i and the resistors 46a, 46b.
Then, the outputs of the resistors 46a, 46b ... 46i are supplied to the inverting side input terminal − of the operational amplifier 47, and the non-inverting side input terminal + of the operational amplifier 47 is grounded. Further, the inverting side input terminal − and the output terminal of the operational amplifier 47 are connected by the resistor 48. In this way, the operational amplifier 47
The current addition is performed by configuring the circuit that faces.

Then, the outputs obtained by adding the currents in the operational amplifier 47 are supplied to the low-pass filter 49 and averaged, and the averaged output is outputted to the analog audio signal output terminal 50.
Supply to.

Next, the operation of the circuit thus constructed will be described with reference to the timing chart of FIG. Here, in order to simplify the explanation, the buffer circuits 45a, 4a
45i and resistors 46a, 46b, ... 46i are provided in series, and the gain adjustment is performed by selection based on the gain adjustment data of these three circuits. Therefore, here, the circuit actually shown in FIG. 1 (buffer circuits 45a, 45b, 45i, resistors 46a, 46b,
46i) and the like, and the circuit formed by the buffer circuit 45a and the resistor 46a is the first circuit system, the circuit formed by the buffer circuit 45b and the resistor 46b is the second circuit system, and the circuit formed by the buffer circuit 45i and the resistor 46i. Let the circuit be a third circuit system. Then, by selecting these three circuits, the amount of attenuation is 1/7, 2/7, 3 /
It is assumed that the gain can be adjusted in seven stages of 7, 4/7, 5/7, 6/7, 7/7. That is, the constants of the buffer circuit 45a and the resistor 46a are selected so as to perform the 4/7 attenuation in the first circuit system, and the buffer circuit 45b and the resistor so as to perform the 2/7 attenuation in the second circuit system. Bowl 46
The constant of b is selected, and the constants of the buffer circuit 45i and the resistor 46i are selected so as to perform 1/7 attenuation in the third circuit system.

By selecting the constants of the respective circuit systems in this way, when all the circuit systems are selected, (4/7) + (2 /
7) + (1/7) = 7/7 = 1, and an amount of 1/7 to 6/7 can be selected by selecting any one or two sets of circuit systems. Furthermore, when neither circuit system is selected, the output state becomes no signal 0.

Next, the change of the output data according to the selection of the circuit system by such gain adjustment data will be described with reference to FIG. 2. First, as a clock for PWM modulation obtained at the terminal 34, as shown in FIG. It is assumed that the pulse indicated by A is obtained. Then, it is assumed that the pulse data shown in B of FIG. 2 is obtained as the output of the PWM wave generation circuit 33. This PW
The M-modulated wave is -3, -2, -1, 0, +1, +2, +3 when the duty is 50% and the reference is 0.
1-bit data that changes in 7 steps. The output of the 50% duty pulse generation circuit 35 is P
Same duty as when the WM modulated wave is at the reference 0 level
% Pulses are obtained as shown in FIG. 2C.

As described above, since the gain adjustment is performed by selecting the circuits of three systems here, the gain setting data obtained at the input terminals 37a to 37i is as follows.
The data is 3-bit data, and the first to third circuit systems are selected by the data of each bit series. Here, the gain setting data obtained at the input terminal 37a is converted to the attenuation data 1 (ATT1 shown in D of FIG. 2) and the input terminal 3
The gain setting data obtained at 7b is assumed to be attenuation data 2 (ATT2 shown in E of FIG. 2), and the gain setting data obtained at the input terminal 37i is assumed to be attenuation data 3 (ATT3 shown in F of FIG. 2).

At this time, the respective attenuated data 1, 2, and 3 are PWM-controlled by the D flip-flop 36.
The data is data that changes in synchronization with the modulation clock, and the data 1, 2, and 3 shown in G, H, and I of FIG.

Then, first, the amount of attenuation (ATT
If 5/7 is selected as the amount), this 5/7 attenuation amount is the sum of the 4/7 attenuation amount by the first circuit system and the 1/7 attenuation amount by the third circuit system (that is, [4/7] + [1/7]). Therefore, according to the attenuation data 1, 2, 3
The first circuit system and the third circuit system are selected. That is, the attenuated data 1 and the attenuated data 3 become the high level signal "1", and the attenuated data 2 become the low level signal "0". Depending on this signal state, the AND gate 41a of the first circuit system and the AN of the third circuit system
The high level signal "1" is supplied to the other input end of the D gate 41i.
The PWM wave supplied to one input end of 1a and 41i comes to be output as it is. In addition, A of the second circuit system
A high level signal "1" obtained by inverting the low level signal "0" is supplied to the other input terminal of the ND gate 42b,
The 50% duty pulse supplied from the 50% duty pulse generation circuit 35 to one input terminal of the AND gate 42b is directly output.

Therefore, the buffer circuit 45a and the resistor 46a which form the first circuit system, and the buffer circuit 45i and the resistor 46i which form the third circuit system are respectively arranged as shown in J and L of FIG. P output from the PWM wave generation circuit 33
The WM wave is supplied as it is. Further, in the buffer circuit 45b and the resistor 46b forming the second circuit system, as shown by K in FIG.
A pulse having a duty of 50% is output.

In this state, as the amplified output of the operational amplifier 47, the PWM wave passing through the first circuit system, the 50% duty pulse passing through the second circuit system, and the third circuit system are passed. The PWM wave is added to obtain a current-amplified signal. Therefore, P with an amount of attenuation of 5/7
The WM wave is output from the operational amplifier 47, and smoothed by the low-pass filter 49 to obtain an analog audio signal that is attenuated by 5/7 at the output terminal 50.
In this case, since the data that has passed through the second circuit system is a pulse with a duty of 50%, it is a pulse corresponding to 0 data and does not affect the output of the operational amplifier 47.

Then, assuming that 1/7 is selected as the amount of attenuation as shown in the substantially central portion of the timing chart of FIG. 2, this amount of 1/7 attenuation is 1/3 by the third circuit system. Can be obtained with only 7 Attenuate. Therefore, the change from the amount of attenuation 5/7 to the amount of 1/7 attenuation is obtained by the change of the high level signal "1" of the attenuation data 1 to the low level signal "0". Due to such changes, AND of the third circuit system
The high level signal "1" is supplied only to the other input end of the gate 41i.
The PWM wave supplied to one input end of 1i comes to be output as it is. In addition, A of the first and second circuit systems
A high level signal "1" obtained by inverting the low level signal "0" is supplied to the other input terminals of the ND gates 42a and 42b, and the 50% duty pulse generation circuit 35 outputs an AND signal.
A pulse with a duty of 50% supplied to one input end of the gates 42a and 42b is directly output.

In this state, as the amplified output of the operational amplifier 47, the duty 5 which has passed through the first and second circuit systems is used.
The 0% pulse and the PWM wave that has passed through the third circuit system are added to obtain a current-amplified signal. Therefore, a PWM wave having an attenuation amount of 1/7 is output from the operational amplifier 47, and smoothed by the low-pass filter 49 to obtain an analog audio signal that is attenuated to 1/7 at the output terminal 50. Also in this case, the first and second
Since the data passing through the circuit system of No. 1 is a pulse having a duty of 50%, it is a pulse corresponding to 0 data and does not affect the output of the operational amplifier 47.

Further, as shown on the right side of the timing chart of FIG. 2, assuming that 6/7 is selected as the amount of attenuation, the amount of attenuation of 6/7 is the amount of attenuation of 4/7 by the first circuit system. And the amount of 2/7 attenuation by the second circuit system. Therefore, the amount of attenuation is 1/7 to 6 /
The change to 7 is a change from the low level signal “0” of the attenuated data 1 and 2 to the high level signal “1”,
It is obtained by changing the high level signal "1" of the attenuated data 3 to the low level signal "0". Due to such changes, the AND gates 41a, 4 of the first and second circuit systems
The high level signal "1" is supplied to the other input terminal of 1b, and the PWM wave supplied to one input terminal of each of the AND gates 41a and 41b is directly output. Further, the AND gate 42 of the third circuit system
A high level signal "1" obtained by inverting the low level signal "0" is supplied to the other input terminal of i, and the duty is 50%.
A pulse having a duty of 50% supplied from the pulse generation circuit 35 to one input terminal of the AND gate 42i is directly output.

In this state, as the amplified output of the operational amplifier 47, the PWM wave that has passed through the first and second circuit systems,
A pulse having a duty of 50% that has passed through the third circuit system is added to obtain a current-amplified signal. Therefore, a PWM wave with an attenuation amount of 6/7 is output from the operational amplifier 47, and smoothed by the low-pass filter 49 to obtain an analog audio signal that is attenuated by 6/7 at the output terminal 50. Also in this case, since the data that has passed through the third circuit system is a pulse with a duty of 50%, it is a pulse corresponding to 0 data, and the operational amplifier 47
Does not affect the output of.

As described above, according to the circuit of this example, 1/7 to 7/7 depending on the states of the attenuation data 1, 2 and 3.
The amount of attenuation can be freely selected. Further, as the attenuated data 1, 2, and 3, all are low level signals “0”, and the duty is 5 in all circuit systems.
By passing a 0% pulse, a pulse corresponding to 0 data can be output from the operational amplifier 47 to put it into a silent state. Such adjustment of the amount of attenuation is
Since the PWM wave, which is digital audio data, is processed without degrading the accuracy, the dynamic range of the digital audio data is not impaired.

When adjusting the amount of attenuation (that is, gain adjustment), a pulse having a duty of 50% corresponding to 0 data is passed through a circuit system that does not need to pass a PWM wave. Even if the amount changes, no sudden change occurs in the average level of the signal supplied to the operational amplifier 47. Therefore, at the time of gain adjustment, generation of a click sound due to a rapid change in the DC level is prevented. Further, the attenuation processing of this example does not deteriorate the characteristics in an analog manner, and the output terminal 50
The analog audio signal output from the device does not deteriorate.

In the example shown in FIG. 2, the case where the amount of attenuation is adjusted in seven steps by setting the first and second circuit systems has been described, but by increasing the number of circuit systems, it becomes more detailed. Gain adjustment becomes possible.

In the above embodiment, the pulse width modulation (PW
Although the present invention is applied to the 1-bit digital / analog converter in which M) is performed, the present invention can also be applied to the 1-bit digital / analog converter of another modulation method (pulse number modulation or the like).

[0045]

According to the gain varying device of the present invention, the data supplied to the operational amplifier from each selection means through the series circuit of the buffer and the resistor is synchronized with the clock regardless of the gain adjustment amount. Even if the gain adjustment amount is switched, a sudden change does not occur in the analog average level, and the generation of a click sound during gain adjustment is prevented.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart provided for explaining one embodiment.

FIG. 3 is a configuration diagram showing an example of a conventional gain varying device.

FIG. 4 is a configuration diagram showing an example of a conventional gain varying device.

FIG. 5 is a configuration diagram showing an example of a conventional gain varying device.

[Explanation of symbols]

 31 Digital Audio Signal Input Terminal 32 Noise Shaping Circuit 33 PWM Wave Generation Circuit 34 Clock Input Terminal 35 50% Duty Pulse Generation Circuit 37a, 37b ... 37i Gain Setting Data Input Terminal 41a, 41b ... 41i AND Gate 42a, 42b. 42i AND gate 43a, 43b ... 43i OR gate 44a, 44b ... 44i D flip-flop 45a, 45b ... 45i buffer circuit 46a, 46b ... 46i resistor 47 operational amplifier 49 low-pass filter 50 analog audio signal output terminal

Claims (1)

[Claims] 1. A digital gain variable device for changing the output gain of a 1-bit type digital / analog converter in which the number or width of output pulses changes according to a digital input signal. Is supplied to one input part of the plurality of selection means, a pulse having a duty of 50% is supplied to the other input part of the plurality of selection means, and the selection output of each selection means is a resistor having a constant different from that of the buffer. And the output of each of the resistors is supplied to an operational amplifier, the amplified output of the operational amplifier is supplied to a low-pass filter, and an analog output signal is obtained from the output of the low-pass filter. A digital gain varying device adapted to adjust the gain of the analog output signal by selecting the output by means.