JP3210231B2 - Light emitting element drive circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit for driving a light emitting element such as a light emitting diode or a laser diode which is suitably used for optical communication.

[0002]

2. Description of the Related Art Various improvements have been made in conventional driving circuits for light emitting elements in order to improve the switching characteristics of the light emitting elements. Techniques for proposing such improvements include, for example, the following three configurations.

(1) "Optical semiconductor element driving circuit" (disclosed in JP-A-2-272778) (2) "Optical semiconductor element driving circuit" (JP-A-5-2965)
No. 5) (3) "Light emitting element driving circuit" (Japanese Patent Laid-Open No. 5-117883)
Hereinafter, the respective drive circuits described in (1) to (3) are referred to as first to third drive circuits, respectively.

[0004] The first drive circuit, as shown in FIG.
The light emitting element 22 is driven by the switch circuit 21. In this first drive circuit, the resistors 23 to 25
As a result, a forward pre-bias voltage is applied to both ends of the light emitting element 22 and the speed-up capacitor 2
6 allows the light emitting element 22 to be quickly charged / discharged at the time of switching by the switch circuit 21. Accordingly, it is possible to drive the light emitting element 22 at high speed and with a reduced amount of jitter.

[0005] The second drive circuit, as shown in FIG.
The light emitting element 32 is driven by a switch circuit 31 that outputs two signals having different polarities. In the second driving circuit, the diodes 33 and 34 and the resistor 3
By means of 5.36, a pre-bias voltage in the forward direction is applied to both ends of the light emitting element 32.

In the second driving circuit, the light emitting element 32
Are biased even when there is no signal, so that charge can be quickly accumulated in the junction capacitance of the light emitting element 32 when turned on. Thereby, the switching speed of the light emitting element 32 is increased, and the amount of jitter can be suppressed.

FIGS. 13 and 14 show a third driving circuit.
As shown in the figure, an input data signal which takes on a binary logic in synchronization with a clock signal is reproduced by a retiming circuit 41, and its output signal (reproduced data signal) is converted into a pulse current by a pulse conversion circuit 42, and the light emitting element 43 is supplied as a drive current. On the other hand, the output signal of the retiming circuit 41 is waveform-shaped by differentiating the rising and falling edges of the output signal with the differentiating circuit 44, respectively, and the DC bias circuit 45 applies a DC bias.

As a result, the output of the differentiating circuit 44 is added as a peaking current to the driving pulse applied to the light emitting element 43, and the electric charge accumulated in the light emitting element 43 is forcibly released by the peaking current. This makes it possible to obtain an optical output waveform with a small light emission delay, a short rise time and a short fall time of the optical output of the light emitting element 43, and a small jitter.

[0009]

In the above-described first driving circuit, the magnitude and duration of the transient current supplied to the light emitting element 22 depend on the junction capacitance of the light emitting element 22 and the capacitance of the speed-up capacitor 26. Determined by the ratio. For this reason, the magnitude and duration of the transient current are very difficult to set and vary greatly due to the junction capacitance described above. Therefore, it is not possible to obtain a target appropriate transient current, and there is a disadvantage that the performance of each drive circuit during mass production becomes unstable.

In the second driving circuit, the speed of the switching of the light emitting element 32 is increased by applying the pre-bias voltage. However, the application of the pre-bias voltage is also limited. I can not cope.
Therefore, the light emitting element 32 cannot be driven at a frequency exceeding the frequency band in which the light emitting element 32 can be switched.

In the third drive circuit, if a phase difference occurs between the output signal of the pulse conversion circuit 42 and the output signal of the DC bias circuit 45, there is a possibility that the peaking current will not be added to a desired portion of the drive pulse current. is there. If the addition of the peaking current is not performed properly, the light output waveform will be distorted and the performance of the light emitting element 43 may be degraded. To avoid such inconveniences, very precise phase adjustment of a fraction of the target rise time and fall time of the optical output is required, and this cannot be a practical method.

As described above, according to each of the above driving circuits,
When the operating speed (frequency) band of each driving circuit and the light emitting element was not sufficient for the frequency of the input signal, the switching of the light emitting element could not follow the input signal, and the current pulse for driving the light emitting element was turned off. The light emission state continues, albeit slightly, later.

[0013] If the optical wavelength as a light-emitting element is used 660nm light emitting diode, the upper limit of the operating frequency, generally, the cut-off frequency f _c of the when the gain of the light emitting diode is decreased 3 dB. This cutoff frequency f
_c, when the rise time required for the gain is changed to from 10% to 90% of the steady-state value and t _r, it is represented by f _c ≒ 0.35 / t _r. Therefore, the t _r each 30nse
c, 20 nsec, the f _c in the case of a 10 nsec, respectively 11.7MHz, 17.5MHz, 35.0MHz
Becomes

As described above, the operating frequency of the light emitting diode is _tr and the fall time (the gain is 90% of the steady value).
% To 10%).

In the conventional driving circuit, the above operation speed is not sufficient. On the other hand, a bias current is supplied to the light emitting element even at the off level, a peaking current is added at the time of switching of the driving current pulse, or a combination thereof. Thus, attempts are being made to reduce the generation delay of the light emitting element, reduce the jitter, and shorten the rise time and fall time of the optical output, but it is not possible to obtain a sufficient effect or it is difficult to realize in principle. Is a problem.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to shorten the rise time and fall time of a light emitting element and increase the switching speed of the light output of the light emitting element.

[0017]

In order to solve the above-mentioned problems, a light-emitting element driving circuit according to the present invention comprises two signals which have the same logical state as an input digital signal and have the opposite logical state. A signal generating means for generating a signal; a phase difference providing means for providing a phase difference to a change in logic level of the two signals so that the signal on the negative logic side has a lagging phase; and a phase difference provided by the phase difference providing means. Current generating means for generating a driving current having a phase difference based on the change in the logic level, and two driving currents from the current generating means are combined and supplied to the light emitting element.

In the above configuration, a phase difference is given to the logic levels of the two signals from the signal generating means by the phase difference providing means such that the negative logic side has a delayed phase. Then
The current generating means generates two drive currents based on the change in the logic level. Since this drive current has the above-mentioned phase difference, the drive current is supplied to the light-emitting element together, so that it corresponds to the signal on the positive logic side to be a signal component of the two signals. A peaking portion is added to the rising edge and the falling edge of the signal component of the drive current.

When such a drive current is supplied to the light-emitting element, the charge and discharge of the junction capacitance of the light-emitting element are quickly performed,
The rise time and the fall time of the light emitting element can be reduced. In addition, since the current flows to the light emitting element even when the light emitting element is turned off, the charge and discharge time of the junction capacitance can be reduced. Further, since the peaking amount is determined by the phase difference, a peaking portion can be added to the drive current relatively easily.

Specifically, the phase difference providing means in the drive circuit changes the level in the direction opposite to the change in the logic level of the digital signal corresponding to the positive logic side of the two signals, A reference voltage generator whose level changes in the same direction as the change in the logic level of the digital signal corresponding to the logic side and generates two reference voltages having different change widths; And a comparator for expressing the magnitude relationship by a binary signal.

In the above configuration, since the level of the reference voltage generated by the reference voltage generator changes, the judgment level of the magnitude relationship between the two signals with respect to the reference voltage changes in the comparator. Therefore, the difference level between the two reference voltages is different, so that the judgment level of the magnitude relationship between the two signals is different, and the two signals obtained as a result of the judgment are different.
A phase difference occurs in the value signal.

As described above, in the above configuration, it is possible to easily provide the binary signal with a phase difference by adjusting the change width of the reference voltage. Therefore, adjustment when giving a phase difference to the logical level of the two signals becomes simpler than when a delay circuit or the like is used. Further, the above-described reference voltage generator can be configured by only slightly changing the differential amplifier or the like, and the circuit is not complicated.

Preferably, the drive circuit including the reference voltage generator and the comparator includes two systems in which the reference voltage generator, the comparator, and the current generating means have the same characteristics corresponding to two signals. It is composed of circuits.

As a result, almost no phase difference occurs in the signal processing between the circuits of both systems, so that the influence of such a phase difference does not affect the drive current. Further, since the above-described drive circuit is configured to provide a phase difference between signals between the two systems, even when the above-described phase difference occurs, the phase difference is converted to the logical level of the two signals. It can be absorbed by the phase difference. Further, by using two circuits having the same characteristics, the circuit configuration can be simplified.

The phase difference providing means in the above-mentioned drive circuit, in addition to the above-mentioned drive circuit, determines the magnitude relationship between one of the two signals with respect to the other, and the level difference between the two signals is larger than a predetermined value. It is also possible to have a comparator which is represented by a binary signal which is sometimes inverted and which is set differently for each of two signals whose predetermined value can be used as a reference.

In the above arrangement, the comparator determines the magnitude relationship between one of the two signals with reference to the other. This determination is made at a position delayed from the position where the two signals intersect by a predetermined value of the level difference between the two signals. Therefore, when the predetermined value is different for the two signals, the determination time is also different for the two signals, and a phase difference occurs between the two binary signals obtained as a result of the comparison.

As described above, in the above configuration, by adjusting the predetermined value, a phase difference can be easily provided in the binary signal. Therefore, adjustment when giving a phase difference to the logical level of the two signals becomes simpler than when a delay circuit or the like is used. Further, the reference voltage generator as in the above configuration is not required, and the circuit can be further simplified.

In the drive circuit including the comparator, preferably, the comparator and the current generating means are composed of two circuits having equal characteristics corresponding to two signals.

As a result, a phase difference hardly occurs in signal processing between the circuits of both systems, so that the influence of such a phase difference does not affect the drive current. Further, since the above-described drive circuit is configured to provide a phase difference between signals between the two systems, even when the above-described phase difference occurs, the phase difference is converted to the logical level of the two signals. It can be absorbed by the phase difference. Further, by using two circuits having the same characteristics, the circuit configuration can be simplified.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION

[Embodiment 1] An embodiment of the present invention will be described below with reference to FIGS.

As shown in FIG. 1, the drive circuit according to the present embodiment includes an input circuit 2 and reference voltage generators 3a and 3b.
And differential comparators 4a and 4b and differential amplifiers 5a and 5b.

The input circuit 2 as a signal generating means shapes the waveform of a digital signal input from the outside, and outputs a signal whose logic state is the same as that of the digital signal and an opposite signal. Reference voltage generators 3a and 3
b generates a reference voltage used in the differential comparators 4a and 4b based on signals from the positive logic side output and the negative logic side output of the input circuit 2, respectively.

The differential comparator 4a compares the reference voltage _Vrefa from the reference voltage generator 3a with the signal from the positive logic side output, and when the signal is higher than the reference voltage _Vrefa , While outputting a signal, a low level signal is output in the opposite case. The differential comparator 4a also outputs a signal whose logic level is opposite to that of the above signal. The differential comparator 4b compares the reference voltage _Vrefb from the reference voltage generator 3b with the signal from the negative logic side output, and, like the differential comparator 4a, outputs two signals of different logic levels. Is output.

The reference voltage generator 3a · 3b is adapted to change the value of the reference voltage V _REFA · V _refb according to 2, the input voltage (the level of the input digital signal). Reference voltage V _REFA is input voltage at a higher range T ₂ input voltage threshold V _th becomes a low level as compared with the low range T ₁ than the threshold V _th is, the reference voltage V _refb a reference voltage V
The level relationship is the opposite of _refa . The level decrease width Δ
_V refa · ΔV _refb is, is larger in the decrease in width ΔV _refb. Further, V _refa > V _refb in the range T ₁ , and V _refa in the region T ₂ .
_refa < _Vrefb .

The reference voltage generators 3a and 3b are specifically configured as described below to generate the above-described reference voltages _Vrefa and _Vrefb .

As shown in FIG. 3A, the reference voltage generator 3a is based on a differential amplifier circuit having a pair of transistors 6a and 6b. The negative logic side output of the input circuit 2 is connected to the base of the transistor 6a.
The positive logic side output of the input circuit 2 is connected to the base of b. The collectors of the transistors 6a and 6b are connected to a power supply via resistors 7a and 7b having the same resistance value, and are connected to each other via a resistor 8. The emitters of the transistors 6a and 6b are both connected to a constant current source 9.

As shown in FIG. 3B, in the reference voltage generator 3b, the positive logic output of the input circuit 2 is connected to the base of the transistor 6a, and the negative logic output of the input circuit 2 is connected to the base of the transistor 6b. The configuration is the same as that of the reference voltage generator 3a except that is connected.

In the reference voltage generator 3a, when the input voltage is at a high level (a level higher than the threshold value _Vth ),
Since a high level signal is output from the positive logic side output and a low level signal is output from the negative logic side output, the transistor 6a is turned off and the transistor 6b is turned on.
At this time, a current flows into the transistor 6b via the resistors 7a and 8 and the resistor 7b.

On the other hand, when the input voltage is at a low level (lower than the threshold value _Vth ), a low level signal is output from the positive logic side output and a high level signal is output from the negative logic side output. The transistor 6a turns on and the transistor 6b turns off. At this time, the transistor 6
A current flows into a through the resistance 7a and the resistances 7b and 8.

Here, if the current flowing through the resistor 7b is I ₁ when the input voltage is at a high level, and the current flowing through the resistor 7b is I ₂ when the input voltage is at a low level, I ₁ > I It becomes ₂ . Therefore, when the input voltage is at the high level, the voltage drop due to the resistor 7b is larger, and the reference voltage _Vrefa is smaller than when the input voltage is at the low level.

In the above reference voltage generator 3b, the input circuit 2 for each base of the transistors 6a and 6b
The connection relationship between the positive logic side output and the negative logic side output is opposite to that of the reference voltage generator 3a. For this reason, the level relationship of the reference voltage V _refb when the input voltage is at a high level and when the input voltage is at a low level is opposite to that of the reference voltage generator 3a.

With such an operation, when the input voltage is at a low level, the reference voltage _Vrefa becomes higher than the reference voltage _Vrefb , and when the input voltage is at a high level, the reference voltage _Vrefa is increased.
_refa becomes lower than the reference voltage V _refb . Further, the above-mentioned decrease width ΔV _refa · ΔV _refb is determined by the resistance value of the resistor 8.

Differential amplifiers 5a and 5 as current generating means
b converts two sets of signals (voltages) from the differential comparators 4a and 4b into currents. Specifically, the differential amplifiers 5a and 5b both
When the difference between the pair of signals is smaller than a predetermined value, no current flows,
When the difference exceeds a predetermined value, a current flows. The outputs of the differential amplifiers 5a and 5b are connected to the cathode of the light emitting diode 1 as a light emitting element, and the currents of the differential amplifiers 5a and 5b are combined and flow through the light emitting diode 1.

In the drive circuit configured as described above, the input circuit 2 outputs two pulse signals V whose logical levels are opposite to each other based on the input digital signal.
_a · _Vb is output. On the other hand, reference voltage generators 3a and 3
From b, in the level according to the logic level of the digital signal is the reference voltage V _REFA · V _refb to be changed is the output.

As shown in FIG. 4, in the differential comparator 4a,
Pulse signal V _a is changed from low level to high level,
If changes to the low level again, the pulse signal V _a is compared with a high reference voltage V _REFA when the rising and compared with a lower reference voltage V _REFA during the fall. As a result of the comparison,
The differential comparator 4a outputs a positive logic comparison determination signal _Va1 and a negative logic comparison determination signal _Va2 .

On the other hand, in the differential comparator 4b, the pulse signal V
_{Since b} is changed by the pulse signal V _a and opposite logic level, the pulse signal V _b is lower at the fall reference voltage V
_refb and is compared with a high reference voltage V _refb at the time of rising. Result of the comparison, from the differential comparator 4b, a positive logic of the comparison judgment signal V _b1 and the comparison determination signal V _b2 of the negative logic is output.

[0047] Thus, by the level of the reference voltage V _REFA · V _refb is reversed, the comparison determination signal V _a1 is compared against judgment signal V _b1, advances the time t _S1 phase at the rising time at the fall Proceed t _S2 . The comparison determination signal _Va2 has the opposite relationship between the rise and fall times as described above, but a similar phase difference occurs with respect to the comparison determination signal _Vb2 when the level changes.

From the above operation, the reference voltage generators 3a and 3
b and the differential comparators 4a and 4b function as phase difference providing means.

As shown in FIG. 5, in the differential amplifier 5a,
The comparison / judgment signal _Va1 · _Va2 is converted into _a pulse current _Ia , and the differential amplifier 5b converts the comparison / judgment signal _Vb1 · _Vb2 into a pulse current Ia having _a smaller amplitude (about 10%) than the pulse current Ia. Convert to _b . For example, when the pulse current _Ia is 20 m
If the amplitude is A, the pulse current _Ib has an amplitude of 2 mA. This amplitude difference is due to the difference between the amplification degrees of the differential amplifiers 5a and 5b.

The rise of this result, pulse current between the fall of the rise and the pulse current I _b of I _a, it occurs a phase difference between the time t _S1 ', falling a pulse current I _b of the pulse current I _a And a phase difference of time t _S2 ′ occurs.

[0051] At this time, the light emitting diode 1, the driving current I _d which the pulse current I _a · I _b was synthesized flows. The drive current I _d has a positive direction of the peaking of the peaking amount [Delta] I _p1 to the rising edge, it will have a peaking of the negative direction of the peaking amount [Delta] I _p2 to the falling edge. Therefore, the light emitting diode 1
Also has a waveform having a similar peaking portion.

[0052] Thus, in the driving circuit according to the present embodiment, by combining the pulse current I _a · I _b with a phase difference, the drive current I _d with peaking unit to fall and rise of the edge It has gained. As a result, as shown in FIG. 6, the charging and discharging of the junction capacitance of the light emitting diode 1 is quickly performed, and the rise time and the fall time of the light emitting diode 1 can be reduced.
Therefore, the light emitting diode 1 can be driven in a frequency band higher than the original operating frequency of the light emitting diode 1.

[0053] In the figure, t _r represents the rise time until the gain of the light emitting diode 1 is changed from 10% to 90% of the steady-state value, t _f is the gain of the steady-state value 9
Shows the fall time from 0% to 10%.

Further, a current of ΔI _p2 flows through the light emitting diode 1 even when it is turned off. For this reason, the charging / discharging time of the junction capacitance of the light emitting diode 1 can be shortened as compared with the case where no current flows when turned off.

Further, since the peaking amounts ΔI _p1 and ΔI _p2 are determined by the amplitudes of the pulse currents I _a and I _b and the times t _S1 ′ and t _S2 ′, the peaking portion can be relatively easily added to the drive current. be able to.

[0056] Further, in this driving circuit, the driving current I and the system for generating a pulse current I _a as the signal component of _d, the drive current I _d the pulse current I as a peaking component of
_Since the system that generates _b is constituted by an equivalent circuit, there is almost no phase difference in signal processing between the two systems. Moreover, even if a phase difference occurs due to signal processing,
Originally, the present drive circuit is configured to provide a phase difference between signals between the two systems, so that the above-described phase difference does not matter.

Here, a modified example of the present embodiment will be described.

As shown in FIG. 7, the drive circuit according to the present modification includes an input circuit 2, reference voltage generators 3a and 3b, and drive current generators 10a and 10b, like the above-described drive circuit. ing. The drive current generators 10a and 10b are provided with the functions of the differential comparators 4a and 4b and the differential amplifiers 5a and 5b.
5b. Drive current generator 10a
More specifically, as shown in FIG. 8, reference numeral 10b denotes a transistor 12 to which reference voltages from reference voltage generators 3a and 3b are inputted to a base via a transistor 11, and a transistor whose emitter is connected to the transistor 12 in common. 1
And 3.

The driving current generator 10 configured as described above
In a-10b, the transistor 12, 13 are operated on the basis of the output signal of the amplified reference voltage from the input circuit 2 in the transistor 11, the pulse current I _{a-I b} shown in FIG. 5 is a transistor 13, Flow through 13. Therefore, as in the driving circuit, peaking unit is provided in the drive current I _d flowing through the light emitting diode 1.

In this modification, the drive current generators 10a and 1
By using 0b, the configuration of the drive circuit can be simplified.

Embodiment 2 Another embodiment of the present invention will be described below with reference to FIGS. 4, 5, 9 and 10. Note that, in the present embodiment, components having the same functions as the components in the above-described first embodiment are denoted by the same reference numerals, and description thereof is omitted.

As shown in FIG. 9, the drive circuit according to the present embodiment includes an input circuit 2 and differential comparators 14a and 14b.
And differential amplifiers 5a and 5b.

A differential comparator 14a as a phase difference providing means
14b is a circuit having a hysteresis characteristic in the comparison operation, and receives a pair of signals from the positive logic output and the negative logic output of the input circuit 2. As shown in FIG. 10, the differential comparators 14a and 14b invert the logical level of the output signal when the level difference between the two signals exceeds a predetermined value after the logical level of a pair of input signals is inverted. It is made to let.

The hysteresis width ΔH _a of the differential comparator 14a
Is greater than the hysteresis width [Delta] H _b of the differential comparator 14b, and is set to generate a suitable amount of peaking of the same as the driving circuit according to Embodiment 1 of the embodiment.

In the driving circuit configured as described above, as shown in FIG. 4, the comparison judgment signals V _a1 and V _b1 include
At the rise, a phase difference of time t _S1 occurs, and at the fall, a phase difference of time t _S2 occurs. Also, the comparison determination signal _Va2 ·
_Vb2 has the opposite relationship between rising and falling when _compared to the above case, but a similar phase difference occurs when the level changes.

As shown in FIG. 5, the differential amplifier 5a
A pulse current I _a flowing in, the pulse current I _b flowing into the differential amplifier 5b, occurs a phase difference between the time t _S1 '· t _S2'. Moreover, the amplitude of the pulse current I _b, the amplitude is smaller than the pulse current I _a. Thereby, the light emitting diode 1
The drive current I _d which the pulse current I _a · I _b was synthesized flows. This drive current I _d, peaking of the respective rising edges and falling edges peaking amount ΔI _p1 · I _p2 are provided. Therefore, the light output of the light emitting diode 1 also has a waveform having a similar peaking portion.

[0067] Thus, also in the driving circuit according to this embodiment, by obtaining the driving current I _d with peaking unit, it is possible to shorten the rise time and fall time of the light emitting diode 1. Therefore, the light emitting diode 1 can be driven in a frequency band higher than the original operating frequency of the light emitting diode 1.

Further, since the current ΔI _p2 flows through the light emitting diode 1 even when the light emitting diode 1 is turned off, the charge / discharge time of the junction capacitance of the light emitting diode 1 can be shortened. The peaking amount ΔI _p1 · ΔI _p2 is adjusted by the pulse current I _a · I _p.
It can be done relatively easily by the amplitude of _b and the time t _S1 ′ · t _S2 ′.

[0069] Further, in this driving circuit, the driving current I and the system for generating a pulse current I _a as the signal component of _d, the drive current I _d the pulse current I as a peaking component of
There is almost no phase difference in signal processing between systems that generate _b, and even when a phase difference occurs due to signal processing,
If the phase difference for forming the peaking portion is adjusted, the above-described phase difference does not matter.

The present invention is not limited to the configuration of each drive circuit described in the present embodiment and the first embodiment, and various modified drive circuits can be applied. Of course.

[0071]

As described above, the driving circuit of the light emitting element according to the first aspect of the present invention converts the signal having the same logic state as the input digital signal and the two signals having the opposite logic state to the input digital signal. Signal generating means for generating, a phase difference providing means for giving a phase difference to a change in the logical level of the two signals so that the negative logic side has a lagging phase, and a change in the logic level given the phase difference by the phase difference providing means And a current generating means for generating a driving current having the phase difference based on the above-mentioned method, and the two driving currents from the current generating means are combined and supplied to the light emitting element.

Since the two drive currents obtained based on the two signals have a phase difference as described above, when the drive currents are supplied to the light emitting element together, the drive current Are added to the rising edge and the falling edge of the signal component.

Therefore, when the above-described drive current is supplied to the light emitting element, the charging and discharging of the junction capacitance of the light emitting element are performed quickly, and the rise time and the fall time of the light emitting element can be shortened. In addition, the light emitting element has OFF
Since the current sometimes flows, the light emission delay can be reduced, and the jitter can be reduced. Further, since the peaking amount is determined by the phase difference,
Unlike the peaking drive method using the capacitance component, the peaking drive current does not vary due to the variation in the junction capacitance of the light emitting element. Therefore, when the present drive circuit is mass-produced, it is not necessary to provide the drive circuit with an adjusting function.

Therefore, when the present driving circuit is employed, not only can the light emitting element be driven in a frequency band higher than the original operating frequency of the light emitting element, but also an optical output with less pulse width distortion and jitter can be obtained. This has the effect.

According to a second aspect of the present invention, in the light emitting element driving circuit according to the first aspect, the phase difference providing means corresponds to a positive logic side of two signals. Then, while the level changes in the opposite direction to the change in the logic level of the digital signal, the level changes in the same direction as the change in the logic level of the digital signal corresponding to the negative logic side, and the two change widths differ. The configuration includes a reference voltage generator that generates a reference voltage, and a comparator that expresses a magnitude relationship between two signals with respect to the two reference voltages using a binary signal.

As described above, since the two reference voltages have different widths of change, the judgment levels of the magnitude relationship between the two signals are different from each other, and the two binary signals obtained as a result of the judgment have a phase difference. Occurs. Therefore, it is possible to easily provide a phase difference to the binary signal by adjusting the change width of the reference voltage. For this reason, adjustment of the phase difference between the logical levels of the two signals becomes simpler than when a delay circuit or the like is used. Also, the reference voltage generator as described above,
The configuration can be achieved by only slightly changing the differential amplifier and the like, and the circuit is not complicated.

Therefore, the adoption of the above-described configuration provides an effect that a drive circuit for a light-emitting element can be provided at a low cost and the manufacture of the drive circuit can be simplified.

According to a third aspect of the present invention, there is provided a light emitting element driving circuit according to the second aspect, wherein the reference voltage generator, the comparator, and the current generating means each include two units. 2 with the same characteristics corresponding to the signal
Since the circuit is constituted by the circuits of the two systems, almost no phase difference occurs in the signal processing between the circuits of the two systems, and the influence of such a phase difference does not affect the drive current. Further, since the above-described drive circuit is configured to provide a phase difference between signals between the two systems, even when the above-described phase difference occurs, the phase difference remains at the level of the logical level of the two signals. It is absorbed by the phase difference. Further, by using two circuits having the same characteristics, the circuit configuration can be simplified.

Therefore, the adoption of the above configuration has an effect that a highly reliable drive circuit can be provided.

According to a fourth aspect of the present invention, in the driving circuit of the light emitting element according to the first aspect, the phase difference applying means is configured to set one of the two signals as a reference to the other of the two signals. Is expressed by a binary signal that is inverted when the level difference between the two signals becomes larger than a predetermined value, and a comparator that is set to be different for each of the two signals that can be a predetermined value as a reference. It is a configuration that it has.

As described above, when the two predetermined values are different, the timing for determining the magnitude relationship between the two signals is different. Therefore, by adjusting the predetermined value, a phase difference can be easily provided in the binary signal. For this reason, adjustment of the phase difference between the logical levels of the two signals becomes simpler than when a delay circuit or the like is used. Further, the circuit can be further simplified without requiring the reference voltage generator as in the above configuration, and the circuit can be simplified.

Therefore, by adopting the above configuration, it is possible to provide an inexpensive drive circuit for the light emitting element and to simplify the manufacture of the drive circuit.

According to a fifth aspect of the present invention, in the driving circuit for a light emitting element according to the fourth aspect, the comparator and the current generating means each have a characteristic corresponding to two signals. Since the circuits are composed of two equal circuits, there is almost no phase difference in the signal processing between the circuits of both systems, and even if the above-described phase difference occurs, the phase difference is equal to the two signals. It is absorbed by the logic level phase difference. In addition, by using two circuits having the same characteristics, the circuit configuration can be simplified.

Therefore, when the above configuration is adopted, there is an effect that a highly reliable drive circuit can be provided as in the case of the drive circuit according to the third aspect.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a light emitting element driving circuit according to one embodiment of the present invention.

FIG. 2 is a graph showing reference voltages generated by two reference voltage generators in the driving circuit of FIG. 1;

FIG. 3 is a circuit diagram showing a detailed configuration of the two reference voltage generators.

FIG. 4 is a waveform diagram illustrating a phase relationship between output signals of a differential comparator in a light emitting element driving circuit according to one or another embodiment of the present invention.

FIG. 5 is a waveform diagram showing waveforms of an output current of a differential amplifier, a driving current of a light emitting diode, and the like in a light emitting element driving circuit according to one or another embodiment of the present invention.

FIG. 6 is a graph showing a relationship between a peaking amount and a rise time and a fall time of a digital signal in the drive circuit of FIG. 1;

FIG. 7 is a block diagram showing a configuration of a light emitting element drive circuit according to a modification of the embodiment of the present invention.

FIG. 8 is a circuit diagram showing a detailed configuration of the drive circuit of FIG. 7;

FIG. 9 is a block diagram illustrating a configuration of a light emitting element driving circuit according to another embodiment of the present invention.

10 is a waveform chart showing a phase relationship between output signals of a differential comparator in the drive circuit of FIG.

FIG. 11 is a block diagram illustrating a configuration of a driving circuit of a conventional light emitting element.

FIG. 12 is a block diagram illustrating a configuration of another driving circuit of a conventional light emitting element.

FIG. 13 is a block diagram showing a configuration of still another driving circuit of a conventional light emitting element.

FIG. 14 is a waveform chart showing an operation of the drive circuit of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Light emitting diode (light emitting element) 2 Input circuit (signal generating means) 3a / 3b Reference voltage generator (phase difference providing means) 4a / 4b Differential comparator (phase difference providing means) 5a / 5b Differential amplifier (current generation Means) 14a ・ 14b Differential comparator (phase difference providing means)

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-5-37022 (JP, A) JP-A-2-215170 (JP, A) JP-A 1-213025 (JP, A) JP-A-4- 233776 (JP, A) JP-A-5-110142 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 33/00 H01S 5/00-5/50

Claims (5)

(57) [Claims] 1. A signal generating means for generating a signal having the same logic state as an input digital signal and two signals having a logic state opposite thereto, and a logic of the two signals so that the negative logic side has a lagging phase. Phase difference providing means for providing a phase difference to the level change, and current generating means for generating a drive current having the phase difference based on the change in the logic level given the phase difference by the phase difference providing means, A driving circuit for a light emitting element, wherein two driving currents from the current generating means are supplied to the light emitting element together. The phase difference providing means changes the level in the direction opposite to the change in the logic level of the digital signal in response to the positive logic side of the two signals, while providing the digital signal in response to the negative logic side. A reference voltage generator whose level changes in the same direction as the change in the logic level of the signal and generates two reference voltages having different widths of change, and a binary signal indicating the magnitude relationship between the two signals with respect to the two reference voltages. The driving circuit for a light emitting element according to claim 1, further comprising a comparator. 3. The circuit according to claim 2, wherein said reference voltage generator, said comparator and said current generating means are each composed of two systems of circuits having the same characteristics corresponding to two signals. Driver circuit for light emitting element. 4. The method according to claim 1, wherein the phase difference providing means represents a magnitude relationship between one of the two signals with respect to the other as a binary signal which is inverted when the level difference between the two signals becomes larger than a predetermined value. 2. The driving circuit for a light emitting device according to claim 1, further comprising a comparator which is set differently for each of two signals whose predetermined value can be a reference. 5. The driving circuit according to claim 4, wherein said comparator and said current generating means are each composed of two circuits having the same characteristics corresponding to two signals.