JP3207759B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device and a method of manufacturing the same related to a pattern arrangement for planarizing a semiconductor device.

[0002]

2. Description of the Related Art As semiconductor devices become smaller, the wavelength λ of light used for photolithography tends to become shorter. However, as the wavelength λ becomes shorter, the depth of focus of lithography decreases. Therefore, the step in the height direction of the element is reduced over the entire surface in the shot where the photolithography is performed.
That is, it is necessary to planarize the entire surface. In recent years, as a method of planarizing the entire surface, a polishing method of polishing a film (for example, a silicon oxide film) for planarizing the entire surface using a selective etching solution such as colloidal silica has attracted attention.

However, flattening the entire surface using the polishing method may cause the following problems in the corners of the pattern as compared with conventional local flattening. These will be described with reference to FIGS.

FIG. 10 (a) is a plan view after the entire surface is subjected to polishing, and FIGS. 10 (b) and 10 (c) are views AA 'and B of FIG. 10 (a), respectively. It is sectional drawing of -B '.

In FIG. 10, reference numeral 1 denotes a film serving as a polishing stopper, 2 denotes a buried insulating film, 3 denotes a conductor layer, and 4 denotes a buffer insulating film. Here, the buffer insulating film 4
If there is no problem in the stress or adhesion between the stopper film 1 and the conductor layer 3, it is not always necessary to provide the stopper film.

In FIG. 10A, a region surrounded by a dotted line indicates a contour line based on a certain height of the stopper film 1. FIG. 11 is a diagram showing an example of a method of manufacturing the configuration shown in FIG.

First, as shown in FIG. 11A, a buffer insulating film 4 and a stopper film 1 are formed on a conductor layer 3. The buffer insulating film 4 may be obtained by oxidizing or nitriding the conductor layer 3.

Next, as shown in FIG. 11B, a groove is formed in the laminated structure of the conductor layer 3, the buffer insulating film 4, and the stopper film 1 by patterning and etching (FIG. 11B). , Grooves are formed at both ends of the laminated structure.) This groove is formed at least to a depth that reaches the conductor layer 3. When a plurality of conductor layers 3 are present, it is sufficient that the conductor layers 3 have a depth at which element isolation is formed therebetween. For example, when the conductor layer 3 is a wiring layer, the conductor layer 3 may be entirely removed by etching so that the wiring layer can be separated. When the conductor layer 3 is a semiconductor substrate, the groove may be formed at a depth such that punch-through does not occur between the transistor regions formed in the conductor layer 3.

Next, in order to maintain insulation between the conductor layers 3, an insulating film body 2 is deposited on the entire surface as shown in FIG. Next, as shown in FIG. 11C, the insulating film 2 formed on the stopper film 1 is removed by polishing.

By the way, in the region where the wide element isolation is formed, the height of the insulator film 2 is lower than the region where the stopper film 1 is formed, as shown in FIG. Therefore, even after the polishing, the height of the region where the element isolation film is formed becomes lower than the region where the stopper film 1 is formed, and thus a step is formed. Also, with the formation of this step, the polishing pressure of polishing increases at the end of the stopper film 1 and polishing proceeds at this point, or the etching rate of the insulating film 2 is larger than the etching rate of the stopper film 1. Is easily etched, the thickness of the peripheral portion of the stopper film 1 is reduced as shown in FIG.

Here, comparing the vicinity of the center of the side portion and the vicinity of the corner of the pattern shown in FIG. 10, the area surrounded by the element isolation film 2 having a low height is larger near the corner. Therefore, the polishing pressure increases near the corner and the surface area in contact with the abrasive increases, so that the thickness of the stopper film 1 is further reduced. Further, as shown in FIGS. 10B and 10C, the width of the region where the film thickness is reduced is such that the width y near the corner is larger than the width x near the center of the side.

The remarkable non-uniformity of the film thickness between the corner and the center of the side as described above is caused by the poli that performs the entire surface flattening polishing.
This is a peculiar phenomenon newly generated by the shing method, and does not cause much problem in the conventional etch-back method for performing local flattening. This is because, in the conventional etch-back method, when the area is larger than a certain value, the so-called loading effect hardly occurs, and there is no problem of concentration of pressure on the corner, so that etching is performed evenly on the corner. That's why.

If the film thickness varies during the polishing as described above, for example, when removing the film 1 serving as an etching stopper, the stopper film 1 is completely removed at the thickest portion (for example, the center of the pattern). In order to prevent the conductive layer 3 from being etched at the thinnest portion (for example, the corner of the pattern), it is necessary to secure a large process margin. If lithography is performed before removing the stopper film 1, it is necessary to secure a large focus margin just to compensate for the variation in film thickness.

[0014] Further, polishing for flattening the entire surface is performed.
A problem also occurs when the method is applied to a repetitive pattern as shown in FIG. In FIG. 12A, the shape of the basic cell of the repetition pattern is shown as a rectangle, but the same applies to any shape. FIG.
(B) and (c) respectively show arrow A- in FIG.
It is sectional drawing of A 'and BB'.

When the entire surface is polished by a pattern as shown in FIG. 12, polishing pressure is concentrated on cells at the corners of the pattern. In particular, the cell at the end of the repetitive pattern has a large surface area in contact with the abrasive.
As shown in FIG. 2C, the thickness of the stopper film 1 is reduced. Further, the width y of the region where the film thickness is reduced near the corner portion
Becomes wider than the width x near the center of the repeated pattern. Therefore, a large process margin is set to prevent the conductive layer 3 from being etched at both the thickest portion (for example, the center portion of the repeated pattern) and the thinnest portion (for example, the corner portion of the repeated pattern). Need to secure. If the margin is not secured,
As shown in FIG. 12C, a region 5 where the conductive layer 3 is etched is generated.

In such a region 5, defects are introduced by damage due to polishing, and the etching resistance and electrical characteristics at the end of the conductive layer 3 are deteriorated, for example, the leakage current characteristics when a pn junction is formed. Degradation occurs. Further, the region 5 is further etched by etching for removing the stopper film 1 and the buffer insulating film 4,
Then, when depositing and etching the laminated film (for example,
During the gate formation step), the laminated film may be left in the region 5.

In the structure shown in FIG. 12, the insulator film 2 is configured to reach below the conductor layer 3.
As shown in FIG. 3 (a cross-sectional view taken along the line AA ′ in FIG. 12A), the same applies to a configuration in which the insulator film 2 is formed halfway in the conductor layer 3. As an example of this configuration, there is a case where a trench element isolation is configured using the conductor layer 3 as a semiconductor substrate.

By the way, in the damascene method in which a conductive layer is buried after forming a groove and polished to leave a conductive layer in the groove, a poli is formed between the vicinity of the center of the side of the pattern and the vicinity of the corner.
A step due to shing occurs. This will be described with reference to FIGS.

In FIG. 14, reference numeral 13 denotes a conductor layer;
It is buried in the insulator film 12. FIG.
(A) is a plan view after the entire surface is subjected to polishing,
FIGS. 14B and 14C are cross-sectional views taken along arrows AA ′ and BB ′ in FIG. 14A, respectively.

FIG. 15 shows an example of a manufacturing method for obtaining the structure shown in FIG. First, FIG.
As shown in (a) and (b), a groove is formed in the insulator layer 12 by, for example, lithography and etching. Next, as shown in FIG. 15C, a conductor layer 13 is deposited on the entire surface. At this time, when the width of the groove is wider than twice the thickness of the deposited film, the height of the film 3 in the groove portion becomes lower than the other portions. In addition, the entire surface is subjected to polishing,
As shown in FIG. 15D, the conductor layer 1 other than the groove portion
3 is removed, and the conductive layer 13 is left only in the groove. At this time, since there is a step in the conductor layer 13 as described above,
Alternatively, since the polish speed of the conductor layer 13 is higher than that of the insulator film 12, so-called dishing occurs in which the height of the conductor layer 13 is lower at the center than at the periphery.

Here, comparing the sides and corners of the pattern shown in FIG. 14, the area near the corners is larger in the area surrounded by the higher element isolation film 12. In addition, in order to realize a damascene structure, the insulating film 12 has a lower etching rate than the conductive layer 13 during the polishing, so that the conductive property is higher in the vicinity of the corner than in the vicinity of the center of the side. The body layer 13 tends to remain without being etched. Therefore, the contour lines (the conductor layer 13) indicated by the dotted lines in FIG.
Is not a rectangle, but a shape resembling an ellipse with missing corners. In addition, dishing does not occur uniformly on the entire surface.
As shown in (b) and (c), as for the width to the thinned region, the width y near the corner is wider than the width x near the center of the side.

The non-uniformity between the vicinity of the center of the side portion and the vicinity of the corner portion of the pattern as described above, as shown in FIG.
This also occurs when a dummy pattern 12a for preventing shing is arranged. Further, in this case, since the dummy pattern 12a is formed of an insulator, when the dummy pattern is formed on the entire surface, the resistance increases by the area of the dummy pattern as compared with the case where the dummy pattern is not formed. There is also.

[0023]

As described above, the entire surface is polished to form a device isolation insulating film.
In the lishing method, the area surrounded by the low-height insulator film is larger at the corners than at the sides of the conductor region. For this reason, the polishing pressure is higher at the corners than at the sides, and the rate of contact with the abrasive is higher. Therefore,
The thickness of the stopper film at the corners becomes thinner and polish
There is a problem that a large variation occurs in the ining film thickness.

In the formation of a conductor layer by damascene, the conductor layer is more likely to remain without being etched at the corners than at the sides. Therefore, in this case also poli
There is a problem that a large variation occurs in the shing film thickness. Further, when a dummy pattern is formed on the entire surface to prevent dishing, there is a problem that the resistance increases by the amount of the dummy pattern.

An object of the present invention is to provide a semiconductor device and a method of manufacturing the semiconductor device, which can reduce the variation in the thickness of the polishing film between the corners and the sides of the pattern.

[0026]

SUMMARY OF THE INVENTION A semiconductor device according to the present invention has a first conductor layer, and has at least a pair of corners including a right angle or an acute angle and a side between the pair of corners. It has a first region (for example, a rectangular region) and a second conductor layer using the same material as that of the first conductor layer, and is formed in a region separated from the first region. Second
It has a region and a third region which has an insulator film and is formed in a region other than the first and second regions, and has the following features (1) and (2). (1) The second region is formed to face a corner of the first region via the insulator film of the third region. (2) The second region is discretely formed facing the corners and sides of the first region via the insulator film of the third region, and the discretely formed second region is formed. Are arranged so that the portion facing the corner portion has a higher density than the portion facing the side portion.

In the above-described semiconductor device, the first region may be configured to correspond to the first conductor layer as it is,
A plurality of first conductor layers separated from each other may be formed in the first region. In the latter case, the pattern of the plurality of first conductor layers is, for example, a pattern in which a plurality of basic patterns (cells) are periodically arranged.

For example, when the first region is rectangular, the second region is formed to face each corner of the first region. Further, the distance between the first region and the second region is preferably shorter than the distance between the second region and another second region.

It is preferable that the potential of the second region is fixed. Further, the height of the insulator film in the third region is preferably higher in a portion adjacent to a corner of the first region than in a portion adjacent to a side of the first region.

Further, it is preferable that the height of the insulator film sandwiched between the first region and the second region is higher than the height of the insulator film in contact with the second region outside the second region. In the method of manufacturing a semiconductor device according to the present invention, a step of forming a stopper film serving as a polishing stopper on a conductor layer and a step of selectively removing the stopper film and the conductor layer to form a groove. Thereby, the first pattern having at least a pair of corners including a right angle or an acute angle in a portion other than the groove and a side portion between the pair of corners, and a region separated from the first pattern are formed. Second
While forming a pattern, a third
Forming a pattern, forming an insulator film on the stopper film and in the groove, removing the insulator film on the stopper film by polishing, and removing the stopper film. And the second pattern is formed to face a corner of the first pattern with the third pattern interposed therebetween.

In the above-described semiconductor device and the method of manufacturing the semiconductor device, the second region (or the second pattern) is provided only in the region facing the corner of the first region (or the first pattern). The density of the second region (or the second pattern) facing the corner of the (or first pattern) is the density of the second region (or the second pattern) facing the side of the first region (or the first pattern). Since the height is higher than that, it is possible to prevent unevenness in the film thickness between the corners and the sides due to the polishing.

The semiconductor device according to the present invention includes a fourth region having a conductor layer, at least a pair of corners including a right angle or an acute angle, and at least a side between the pair of corners. A fifth region formed so as to surround the periphery of the fourth region, and a second insulator film using the same constituent material as that of the first insulator film. And
A sixth region formed in a region surrounded by the fourth region, wherein the sixth region is discretely formed at least at a corner and a side of the fourth region, and The sixth region thus formed is arranged such that a portion facing the corner has a lower density than a portion facing the side.

The patterns of the plurality of sixth regions are, for example, patterns in which a plurality of basic patterns (cells) are periodically arranged. In the above-described semiconductor device, the density of the sixth region facing the corner of the fourth region is equal to the density of the sixth region facing the side of the fourth region.
Lower than the density of the area. Therefore, it is possible to prevent unevenness in the film thickness between the corners and the sides of the fourth region. Further, since the low-density sixth region is provided as described above, the proportion of the sixth region as a whole can be reduced,
Therefore, it is possible to prevent an increase in the resistance of the fourth region due to an increase in the occupied area of the insulator.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a first embodiment according to the present invention will be described with reference to FIGS. FIG.
FIG. 1A is a plan view showing the configuration of the first embodiment, and FIGS. 1B and 1C are each a plan view of FIG.
It is sectional drawing of arrow AA 'and arrow BB' of FIG.

In this embodiment, a plurality of dummy patterns 1a
Are not necessarily arranged as shown in the figure, and the corners of the pattern are not necessarily required to be right angles but may be acute angles. Although FIG. 1 shows a structure in which the film 1, the film 1a, and the film 4 are left,
These films are removed upon completion, and FIG.
The final shape is as shown in (b) and (c).

In the embodiments other than this embodiment, figures corresponding to FIGS. 1A, 1B and 1C are shown in order to make the manufacturing process and the polish step easy to understand. Similarly, when completed, these membranes 1,
The film 1a and the film 4 have been removed. That is, what is essentially required at the time of completion is the conductor region 3, the conductor region 3a serving as a dummy pattern, and the insulator layer 2, and the arrangement of these is important.

In FIGS. 1 (a), (b) and (c),
The film 1 serving as a polishing stopper is a buffer insulating film 4
Is formed on the conductor layer 3 through the intermediary of the conductor layer 3. The film 1a serving as a polishing stopper for the dummy pattern is formed on the conductor layer 3a with the buffer insulating film 4 interposed therebetween.
The conductor layer 3 (corresponding to the conductor region and the first region) has at least two corners (having an acute angle or a right angle).
What is necessary is just to have it at both ends of the side, but in the present embodiment, it has a rectangular shape. The conductor layer 3a (the conductor region, the second
The region (corresponding to the region) is formed with the insulator layer 2 (corresponding to the third region) sandwiched between the corners of the conductor layer 3 (conductor region). The distance between the conductor layer 3 and the conductor layer 3a is smaller than the distance between the conductor layer 3a and another conductor layer 3a.

The components of the stopper film 1 include:
Silicon oxide film, silicon nitride film, polycrystalline silicon film,
Examples include a W film, an Al film, a WSi film, a TiSi film, a single crystal silicon film, an amorphous silicon film, a Cu film, a Ru film, and a composite film of these components.
The constituent elements of the conductor layer 3 include a polycrystalline silicon film and W
Examples include a film, an Al film, a WSi film, a TiSi film, a single-crystal silicon film, an amorphous silicon film, and a composite film of these components. Components of the insulator film 2 and the buffer insulating film 4 include a silicon oxide film, a silicon nitride film, a silicon fluoride film, and a composite film of these components.

The height of the insulator film 2 in contact with the corner of the conductor region 3 is formed higher than the height of the insulator film 2 in contact with the side portion of the conductor region 3. Has a different configuration. Further, the film 1a serving as a polishing stopper film is reduced in height toward the outside. Therefore, the conductor layer 3 and the conductor layer 3a
The height of the insulator film 2 in the region sandwiched by the conductor layers 3a
Is higher than the height of the insulator film 2 which is in contact with the conductor layer 3a on the outside.

It is preferable that the potential of the conductor layer 3a is fixed in order to keep the capacitance and the leak current of the insulator film 2 constant. Here, an example of the manufacturing process in the present embodiment will be described with reference to FIGS.

First, as shown in FIG. 3A, a buffer insulating film 4 and a stopper film 1 are laminated on a conductor layer 3.
Note that the buffer insulating film 4 is formed on the conductor layer 3 of the stopper film 1 in order to improve the selection ratio when the stopper film 1 is peeled off.
It is provided to improve the adhesion to the conductor layer or to alleviate the stress on the conductor layer 3 of the stopper film 1 and is not necessarily provided. The buffer insulating film 4 may be obtained by oxidizing or nitriding the conductor layer 3. The thickness of the buffer insulating film 4 is, for example, about 5 to 100 nm, and the thickness of the stopper film 1 is, for example, 1 to 1.
It is about 0 to 500 nm.

Next, as shown in FIG. 3B, grooves are formed in the laminated structure obtained as described above by patterning and etching. This groove is formed at least at a depth equal to or greater than the depth reaching the conductor layer 3, and the depth is, for example, 0.05 to 5 μm. When a plurality of conductor layers 3 are present, it is sufficient that the conductor layers 3 have a depth at which element isolation is formed therebetween. For example, when the conductor layer 3 is a wiring layer, the conductor layer 3 may be entirely removed by etching so that the wiring layer can be separated. The conductor layer 3
Is a semiconductor substrate, the trench may be formed at such a depth that punch-through does not occur between the transistor regions formed in the conductor layer 3.

Next, in order to maintain insulation between the conductor layer 3 and the conductor layer 3a, an insulator film 2 is deposited on the entire surface as shown in FIG. The insulator film 2 has a thickness sufficient to fill the groove, and is, for example, 0.05 to 5 μm. If the laminated thickness of the insulator film 2 is set to be larger than half the distance between the conductor layer 3 and the conductor layer 3a, the upper surface of the stopper film 1 and the surface of the insulator film 2 in the groove region are formed. Since the step can be reduced, it is more preferable for flattening.

Further, the insulator film 2 formed on the stopper film 1 is removed by polishing, and etching is performed until the surfaces of the stopper film 1 and the stopper film 1a are exposed. In this way, as shown in FIG. 1C, a shape in which the insulator film 2 is embedded in the groove is obtained. Further, the stopper film 1, the stopper film 1a, and the buffer insulating film 4 are removed by etching to obtain a shape as shown in FIG.

Incidentally, the region where the wide element isolation is formed is lower in height than the region where the stopper film 1 is formed. Therefore, even after the polish, the height of the region where the element isolation film is formed is lower than the region where the stopper film 1 is formed, so that a step is formed. In addition, with the formation of the step, the polishing pressure of the polishing increases at the end of the stopper film 1 and polishing proceeds at this point. Therefore, as shown in FIGS. 1B and 1C, the periphery of the stopper film 1 is formed. The thickness of the part is reduced.

However, in the present embodiment, unlike the conventional case, the dummy pattern 1a is provided outside the corner of the stopper film 1.
Are formed. In FIGS. 1B and 1C, the widths of the thinner regions at the center and the corners of the side are shown as width x and width y, respectively. In the present embodiment, the dummy pattern 1a is formed. Therefore, the width y near the corner can be smaller than the width x near the center of the side. In FIG. 1A, a region surrounded by a dotted line shows contour lines based on a certain height of the stopper film 1, but in the present embodiment, the contour lines of the stopper film 1 are shown in FIG.
As shown by the dotted line in FIG. As described above, the polishing pressure at the corners of the pattern can be reduced, and the thickness of the stopper film 1 at the corners can be increased.

In the present embodiment, since the dummy pattern 1a is arranged only in the area facing the corner of the pattern,
For example, as shown in FIG. 4A, another conductor region 1b can be formed in a region corresponding to the side of the pattern,
As a result, it is possible to increase the density. FIG.
As shown in (b), the dummy patterns 1a may be formed so as to be intricate on the sides of adjacent patterns.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 5A is a plan view showing the configuration of the second embodiment, and FIG.
5 (c) are cross-sectional views taken along arrows AA 'and BB' in FIG. 5 (a), respectively. Note that components corresponding to the components in the first embodiment shown in FIGS. 1 to 4 are given the same numbers, and descriptions thereof are omitted. In addition, the manufacturing method is basically the same as that of the first embodiment, and thus the description is omitted.

The characteristic configuration of the present embodiment is the pattern 1
Is arranged so that the density of the dummy patterns 1a existing in the area facing the corners of the pattern 1 is higher than the density of the dummy patterns 1a existing in the area facing the side of the pattern 1. That is, as shown in FIG. 5A, the interval between adjacent dummy patterns 1a is
This means that the region facing the corner of the pattern 1 is shorter than the region facing the side of the pattern 1. Further, the dummy pattern 1a is not a space parallel to the side as shown in FIG.
The spacing between the corners may be reduced at the corners, or they may be combined.

Although FIG. 5 shows the conductor region 3 as a rectangle, the conductor region 3 may be, for example, a triangle or a trapezoid. That is, the conductor region 3 may have a shape having two corners (having an acute angle or a right angle) at least at both ends of one side. In this embodiment, a plurality of dummy patterns 1a are formed, but the number of these dummy patterns may be changed as appropriate. The shape of the dummy pattern 1a may be any shape, and may be a rectangular shape, an elliptical shape, or the like other than the square shape as shown in the figure. further,
The intervals between the dummy patterns 1a to 1a along the sides of the pattern may be arranged so as not to cause dishing between them.

It is preferable that the potential of the conductor layer 3a is fixed in order to keep the capacitance and the leak current of the insulator layer constant. In the present embodiment, similarly to the first embodiment, the polishing pressure at the corners of the pattern can be reduced, and the thickness of the stopper film 1 at the corners can be increased. Further, in the present embodiment, since the dummy patterns 1a are dispersedly arranged, the occupied area of the dummy patterns 1a can be reduced as compared with the first embodiment shown in FIGS. Therefore, the conductor region 3
The capacitance and the leak current can be reduced between the conductor and the conductor region 3a.

Next, a third embodiment according to the present invention will be described with reference to FIG. FIG. 6A is a plan view showing the configuration of the third embodiment, and FIG.
(B) and (c) are respectively AA of FIG. 6 (a).
'And a sectional view taken along line BB'. Components corresponding to those in the first embodiment shown in FIGS. 1 to 4 and the second embodiment shown in FIG. 5 are denoted by the same reference numerals, and description thereof is omitted. Also, the manufacturing method is basically the same as in the first and second embodiments, so that the description is omitted.

This embodiment is basically similar to the second embodiment shown in FIG.
However, the present embodiment is different from the second embodiment in that the conductor region 3x is constituted by a pattern of a plurality of conductor layers 3 in which a basic pattern is repeated. This embodiment can be applied to, for example, a memory configured by repeating the same cell, such as a memory.

In FIG. 6A, the dummy pattern 1a is not provided at the center of the side of the conductor region 3x, but for example, as shown in the second embodiment (see FIG. 5A), The dummy patterns 1a existing in the region facing the corners of the body region 3x may be arranged to have a higher density than the dummy patterns 1a existing in the region facing the sides of the conductor region 3x. . Also, the dummy pattern 1a
Need not necessarily be dispersed as shown in FIG. 6A, and may be composed of a single connected pattern, for example, as shown in the first embodiment (see FIG. 1 and the like).

Although the conductor region 3x is shown as a rectangle in FIG. 6, it may be, for example, a triangle or a trapezoid. That is, the conductor region 3 may have a shape having two corners (having an acute angle or a right angle) at least at both ends of one side. In the present embodiment, the shape of each pattern 1 is a square.
As shown in (a) to (e), any shape such as a rectangular shape, an elliptical shape, and a polygonal shape may be used. In this embodiment, a plurality of dummy patterns 1a are formed, but the number of these dummy patterns may be changed as appropriate. The shape of the dummy pattern 1a may be an arbitrary shape, and may be a rectangular shape, an elliptical shape, or the like other than the square shape as shown in the figure. In this case, it can be easily formed in pattern design.

It is preferable that the potential of the conductor layer 3a is fixed in order to keep the capacitance and the leak current of the insulator layer 2 constant. Also in this embodiment, similarly to the first and second embodiments, the polishing pressure at the corners of the pattern can be reduced, and the thickness of the stopper film 1 at the corners can be increased.

Next, a fourth embodiment of the present invention will be described with reference to FIGS. FIG. 8A is a plan view showing a configuration of the fourth embodiment, and FIGS. 8B and 8C are views taken along a line A-A in FIG.
It is sectional drawing of A 'and arrow BB'.

In FIG. 8, 13 is a conductor layer (corresponding to the conductor region and the fourth region) surrounded by the insulator 12 (corresponding to the fifth region), and 12a is a dummy surrounded by the conductor region 13. An insulator serving as a pattern (corresponding to the sixth region). The insulator 12 and the insulator 12a are made of the same constituent material. In FIG. 8A, a region surrounded by a dotted line indicates a contour line based on a certain height of the conductive layer 13.

Although the conductor region 13 is shown in FIG. 8 as having a rectangular shape, it may have a triangular or trapezoidal shape, for example. That is, the conductor region 3 may have a shape having two corners (having an acute angle or a right angle) at least at both ends of one side. The shape of the dummy pattern 12a may be an arbitrary shape, and may be a rectangular shape, an elliptical shape, or the like in addition to the square shape as shown in the figure. further,
In the present embodiment, a plurality of dummy patterns 12a are formed, but the arrangement of these dummy patterns may be appropriately changed. In other words, what is essentially required in the present embodiment is that the density in the side direction of the dummy pattern 12 a arranged along one side of the conductor region 13 is higher than that of the portion facing the corner of the conductor region 13. This means that the portion facing the center of the side is arranged at a higher density.

Here, an example of the manufacturing process in this embodiment will be described with reference to FIGS. 9 (a) to 9 (c).
First, the insulator 12 shown in FIG.
As shown in (b), a groove is formed using, for example, lithography and etching. The depth of the groove is, for example, 0.05
５5 μm.

Next, as shown in FIG. 9C, a conductor layer 13 is deposited on the entire surface. At this time, when the width of the groove is wider than twice the deposited film thickness, the height of the conductive layer 13 at the groove is lower than the height on the insulator 12 and a step is generated.
Therefore, it is preferable to make the width of the groove smaller than twice the thickness of the deposited film. Further, under the condition that the deposited film thickness decreases as the surface area increases, as shown in FIG. 9C, the deposited film thickness decreases above the groove.

Next, the entire surface is flattened by polishing to remove the conductive layer 13, leaving the conductive layer 13 inside the groove as shown in FIG. 8C. In the present embodiment,
Since the density near the center of the side of the conductor region 13 is higher than the density of the dummy pattern 12a near the corner, the height near the center of the side of the pattern is prevented from becoming lower than the height near the corner. Can be. Also, the dummy pattern 12a
Of the dummy pattern 12a formed of an insulator as a whole pattern because the surface density of the pattern is made smaller at the periphery of the pattern than at the center of the pattern. The occupation ratio can be reduced. Therefore, an increase in resistance due to an increase in the occupied area of the insulator can be prevented. Further, the surface area of the groove can be reduced as compared with the case where the dummy pattern 12a is formed uniformly over the entire surface. Therefore, the problem that the deposited film thickness of the conductor layer 13 is reduced can be reduced.

The present invention is not limited to the above-described embodiments, but can be modified as follows. The insulator film, the buffer insulator film, and the film serving as the polish stopper may be formed by forming a silicon oxide film by a thermal oxidation method, a method of implanting oxygen with low acceleration energy of about 30 keV, a deposition method, or the like. The silicon nitride film may be formed by a method or the like, or may be formed in combination. The method of forming the element isolation film and the insulator film itself includes a method of converting silicon into a silicon oxide film and a silicon nitride film, such as a method of implanting oxygen ions into deposited silicon and a method of oxidizing deposited silicon. May be used. Further, as the insulator film, in addition to a silicon nitride film, a silicon fluoride film, a tantalum oxide film, a ferroelectric or paraelectric film such as strontium titanate, barium titanate, and lead zirconium titanate may be used. Alternatively, a composite film of these films may be used.

The conductive layer and the film serving as a polish stopper include, in addition to polycrystalline silicon, monocrystalline silicon, porous silicon and amorphous silicon, SiGe mixed crystal and SiC mixed crystal, GaAs, metal (W, Ta, Ti). , H
f, Co, Ru, Pt, Pd, Al, Cu, etc.) and silicides thereof, nitrides thereof, and oxides thereof. Further, a stacked structure of these films may be used.

[0065]

According to the first, third and fifth aspects of the present invention, the second region (the dummy pattern having the conductor layer) is provided in the region facing the corner of the first region (the region having the conductor layer). Since the region is provided, it is possible to prevent unevenness in film thickness between the corner and the side due to the polishing.

According to the second and third aspects of the present invention, the density of the second region (the region corresponding to the dummy pattern having the conductor layer) opposed to the corner of the first region (the region having the conductor layer) is reduced to the second region. Since the density is arranged so as to be higher than the density of the second region facing the side of one region, it is possible to prevent the film thickness of the corner and the side from being uneven due to the polishing.

According to the fourth aspect of the present invention, the density of the sixth region (the region corresponding to the dummy pattern having the insulating film) opposed to the corner of the fourth region (the region having the conductive layer) is set to the fourth region. Are arranged so as to be lower than the density of the sixth region facing the side portion of. Therefore, it is possible to prevent unevenness in the film thickness between the corners and the sides of the fourth region. Further, since the low-density sixth region is provided as described above, the proportion of the sixth region occupied can be reduced as a whole, and an increase in resistance of the fourth region due to an increase in the occupied area of the insulator can be prevented. Becomes possible.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of the first embodiment of the present invention.

FIG. 3 is a diagram showing an example of a manufacturing process of the first embodiment of the present invention.

FIG. 4 is a diagram showing an application example of the first embodiment of the present invention.

FIG. 5 is a diagram showing an example of a second embodiment of the present invention.

FIG. 6 is a diagram showing an example of a third embodiment of the present invention.

FIG. 7 is a diagram showing a modification example of a part of FIG. 6;

FIG. 8 is a diagram showing an example of a fourth embodiment of the present invention.

FIG. 9 is a diagram illustrating an example of a manufacturing process according to a fourth embodiment of the present invention.

FIG. 10 is a diagram showing an example of a conventional technique.

FIG. 11 is a diagram showing an example of the manufacturing process of the prior art shown in FIG.

FIG. 12 is a diagram showing another example of the related art.

FIG. 13 is a diagram showing another example of the related art.

FIG. 14 is a diagram showing another example of the related art.

FIG. 15 is a view showing an example of the manufacturing process of the conventional technique shown in FIG.

FIG. 16 is a diagram showing another example of the related art.

FIG. 17 is a diagram showing a modification of the second embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Stopper film 1a ... Stopper film 2 ... Insulator layer (3rd area) 3 ... 1st conductor layer (1st area) 3a ... 2nd conductor layer (2nd area) 12 ... Insulator Film (fifth region) 12a: insulator film (sixth region) 13: conductor layer (fourth region)

Claims (5)

(57) [Claims] A first region having a first conductor layer, at least a pair of corners including a right angle or an acute corner, and a side portion between the pair of corners; and the first conductor layer. A second region formed in a region separated from the first region, an insulating film, and a second conductive layer using the same constituent material as the first and second constituent materials. A third region formed in a region other than the region, wherein the second region is formed to face a corner of the first region via an insulator film in the third region. Characteristic semiconductor device. 2. A first region having a first conductor layer and having at least a pair of corners including a right angle or an acute corner, and a side between the pair of corners, and the first conductor layer. A second region formed in a region separated from the first region, an insulating film, and a second conductive layer using the same constituent material as the first and second constituent materials. A third region formed in a region other than the region, wherein the second region is discretely opposed to a corner and a side of the first region via an insulator film of the third region. The semiconductor device according to claim 1, wherein the discretely formed second regions are arranged at a higher density in a portion facing the corner than in a portion facing the side. 3. The height of the insulator film in the third region is:
3. The semiconductor device according to claim 1, wherein a portion adjacent to a corner of the first region is higher than a portion adjacent to a side of the first region. 4. 4. A fourth region having a conductor layer and having at least a pair of corners including a right angle or an acute angle, and a side between the pair of corners, and a first insulator film. A fifth region formed so as to surround the periphery of the fourth region, and a second insulator film using the same constituent material as the constituent material of the first insulator film. And a sixth region formed in an enclosed region, wherein the sixth region is discretely formed facing at least corners and sides of the fourth region, and is formed discretely. The semiconductor device according to claim 6, wherein the sixth region has a lower density at a portion facing the corner portion than at a portion facing the side portion. 5. A step of forming a stopper film serving as a polishing stopper on the conductor layer, and selectively removing the stopper film and the conductor layer to form a groove. A first pattern having at least a pair of corners including a right angle or an acute angle and a side between the pair of corners;
Forming a second pattern formed in a region separated from the pattern and forming a third pattern corresponding to the groove; forming an insulator film on the stopper film and in the groove; polishing; A step of removing the insulator film on the stopper film, and a step of removing the stopper film. The second pattern faces a corner of the first pattern via the third pattern. A method for manufacturing a semiconductor device, comprising: