JP3202654B2 - Microprocessor system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a microcomputer system including a microprocessor and an external storage device, and more particularly to a microprocessor system for improving bus access efficiency to an external storage device.

[0002]

2. Description of the Related Art In recent years, the use of CMOS devices has further reduced the power consumption of microprocessors, and improved architecture (such as pipeline processing) has made it possible to process instructions at a very high speed. However, in a program read or data read with an external storage device, the access time is relatively longer than the execution time of the microprocessor due to the limitation of the access speed, and the instruction execution time of the microprocessor is reduced. Cause.

[0003] Further, various types of microprocessors having a built-in high-speed storage device such as a cache memory have been developed. When these microprocessors access the external storage device, in the instruction and data processing operation inside the microprocessor, a state of waiting for read data from the external storage device frequently occurs, so that the instruction is read ahead, Despite the fact that instruction decoding is performed and an address to be accessed next can be set in the program counter, a bus neck (a state of waiting for read data from the external storage device of the microprocessor) occurs. Couldn't get the best out of the performance.

[0004] The cause of the problem is that, when a system equipped with a microprocessor is conventionally constructed, the system is generally constituted by a microprocessor and an asynchronous storage device. Therefore, the interface between the microprocessor and the asynchronous storage device needs to be held by the address output microprocessor until the data reading is completed due to the characteristics of the asynchronous storage device.

For example, when a microprocessor executes an instruction fetch and a data read access to an external storage device, in particular, it reads out an instruction code stored at a continuous address as in a normal program. Most of the processing time of the entire microprocessor is in a state of waiting for an instruction code from an external storage device, thereby reducing the processing speed of the entire microcomputer system.

In recent years, as an example in which a microprocessor accesses an external storage device, various types of systems for performing image processing and the like have been developed. In these systems, data is stored in a continuous address from the external storage device. -Read access is also frequently occurring.

On the other hand, in order to cope with the recent increase in the speed of microprocessors and to cope with the above-mentioned case, a clock synchronous type storage device has been developed as an external storage device, and it has become possible to access at high speed. I have. However, with respect to clock synchronous storage devices, conventional microprocessors do not output addresses and respective output control signals at optimal timing, and therefore cannot be accessed at high speed. .

Therefore, in order to clarify the above problem,
One example of the configuration of a conventional microprocessor system will be described in detail with reference to FIG. 9 showing a block diagram and FIG. 10 showing a block diagram of an address generation unit incorporated in the microprocessor. This conventional system,
The system includes a microprocessor 1, a storage device control circuit 2, and a clock synchronous storage device 3. The microprocessor 1 has an address generation unit 10b, and the address signal CAD, the chip select CS bar signal, for example, the CS1 bar, the write / read control signal R / W bar, and the system clock signal generated by the address generation unit 10b. CLK to the storage device control circuit 2, and further outputs a system clock signal CLK and a chip select signal C
The S1 bar is also output to the clock synchronous storage device 3. The storage device control circuit 2 outputs a standby instruction signal WAIT to the microprocessor 1 and sends an address signal S to the clock synchronous storage device 3 which is separated into upper and lower addresses.
AD, a row address strobe signal RAS, a column address strobe signal CAS, and a write enable signal WE. In addition, between the clock synchronous storage device 3 and the microprocessor 1,
A data bus is also connected.

The conventional address generation unit 10b receives an instruction fetched by the microprocessor 1 and decodes the instruction to convert the instruction into a control signal. The control signal decoded by the instruction decoder 11 determines a jump destination. A jump destination address generation unit 12 for generating an address of an interrupt vector, an interrupt control unit 13 for generating a stack control signal for jumping to a specific address specified by an interrupt vector address in response to an interrupt signal input from the outside, A stack control unit for generating an address signal for designating a stack area of the storage control device based on a stack control signal from the interrupt control unit; a stack area address signal generated by the stack control unit and a jump destination address generation From the destination address signal output from the And a program counter address signal input from the program counter control unit 15. The program counter address signal input from the program counter control unit 15 is set and sequentially counted according to a 1-byte instruction, a 2-byte instruction, a 3-byte instruction, and the like. A program counter 16 for outputting an address after being up, and a bus control unit 17 for inputting a fetch address output from the program counter 16 and a data access address from a CPU (not shown). You.

An operation from reading of an instruction to generation of an address will be described using the above-described conventional address generation unit 10b.

Referring to FIG. 10, a program counter 16 indicates an address for the microprocessor 1 to fetch to the outside. The access address of the instruction output from the program counter 16 is
The instruction is sent to the bus control unit 17 and output to the outside as an external address output signal for fetching an instruction.

The bus control unit 17 has a C
A bus cycle is started by controlling the S1 bar signal and the R / W bar signal. The bus cycle ends when a high level of the WAIT signal is input from outside.

The instruction fetched from the outside by the above operation is input to the instruction decoder 1. Simultaneously with the input of the command, the program counter 16 automatically counts up by +1 for a normal command. At this time, if the fetched instruction is a branch instruction and branches, the jump address generation unit 2 generates a jump address from the control signal decoded by the instruction decoder, and outputs the generated signal to the program counter control unit 15. To communicate.

The program counter control unit 15 sets the transmitted jump destination address in the program counter. The program counter 16 executes a count operation according to the set program counter address, and the bus control unit 17 complexes the address of the execution result with the data access address signal,
Transmitted as an external address output signal.

When the active level of the interrupt signal is input to the interrupt controller 13, the interrupt controller 13 fetches an interrupt vector address in response to the interrupt signal and controls the stack controller 14. The stack control unit 14 controls the return address, and when returning, outputs the return address to the program counter control unit 15. That is, the program counter control unit 15 sets the jump destination address in the case of a branch instruction, and sets the stack return address in the case of an interrupt, in the program counter 16. Each of the above components operates in clock synchronization.

Next, FIG. 9 and FIG. 10 and the read / write operation for the clock synchronous storage device of the conventional microprocessor will be described.
FIG. 1 showing a timing chart for explaining an access operation
The operation will be described with reference to FIG.

Generally, the interface between the microprocessor 1 and the clock synchronous storage device 3 is performed by the storage device control circuit 2. Here, the microprocessor 1
However, a case where two-word continuous read access to the clock synchronous storage device 3 is performed will be described.

The microprocessor 1 synchronizes with the rising edge of the clock in the cycle T1 in FIG.
(Address a is an area of the clock synchronous storage device.)
And outputs the active level of the CS1 bar signal obtained by decoding this address a and the R / W bar signal.

In the storage device control circuit 2, the input CS1
The bar signal and the R / W bar signal are converted to the system clock CL.
Recognition is made at the fall of the timing T1 of K, and the active level of the RAS bar signal is output to the clock synchronous storage device 3.

The clock synchronous storage device 3 recognizes the low level of the CS1 bar signal and the low level of the RAS bar signal at the rise of the cycle TB1 of the input system clock CLK, and outputs the low level from the storage device control circuit 2. The row (row) address portion of the address a is fetched as an input address.

Next, the storage device control circuit 2 makes the RAS bar signal inactive in synchronization with the falling timing of the cycle TB1 of the system clock CLK,
Activate the CAS bar signal.

The clock synchronous memory device 3 sets the low level of the CS1 bar signal and the CA at the rising edge of the cycle TB2 of the input system clock CLK signal.
The low level of the S bar signal is recognized, and the column (column) of the address a output from the storage device control circuit 2 is output.
Take the address part as the input address.

With the above operation, the address input to the clock synchronous memory device 3 is completed. In a general clock synchronous storage device, the user can arbitrarily set the data output timing and the number of output words.

The detailed operation of the clock synchronous memory device after the above-mentioned operation is not directly related to the present invention, so that the description is omitted here.

Next, a case where the microprocessor 1 reads data continuously for two words will be described.

The clock synchronous memory device 3 stores the data a1 designated by the address a by the above-mentioned address input until the rise of the next cycle of the cycle TB3 in the system clock CLK of the microprocessor 1
It is possible to output the data a2 specified by the address a until the rise of the next cycle of the cycle TB4.

The storage device control circuit 2 outputs the active level of the WAIT signal to the microprocessor 1 in accordance with the timing of the data output from the clock synchronous storage device 3, and confirms that the data has been determined. Notify the processor 1.

The microprocessor 1 samples the WAIT signal in synchronization with each rising timing of the system clock CLK of the microprocessor. As a result, when the active level is input, the data at that time is taken. (The sampling timing of the WAIT signal and the sampling timing of the data are different depending on the type of the microprocessor, but the description of the sampling timings other than the above-mentioned timings will be omitted.) When the microprocessor 1 completes the data capture, the cycle starts. Transition to TE ends the bus cycle. The same access as that described above is performed for the address b.

When constructing an interface between the microprocessor 1 and a conventional storage device, due to the characteristics of the conventional storage device, the microprocessor 1 operates until the read data is fetched, that is, between the cycle T1 and the cycle TE.
The address had to be stored in the external storage device.

As described above, when the microprocessor 1 performs read access to the clock synchronous storage device 3, in the conventional microprocessor system shown in FIG. • As shown in the timing, 6 from cycle T1 to TE until the access of two words is completed.
A clock bus cycle is required, and the microprocessor 1 is in a standby state for processing until the data fetch is completed.

However, as described above, the clock-synchronous storage device 3 has a short address fetching period and slightly changes the address once the address is input, although the operating frequency and the device slightly vary. The data is latched in the storage device 3 and the latched addresses are sequentially counted up. Therefore, the microprocessor 1
Means that the clock synchronous storage device 3 continuously stores the data for the internally counted address in synchronization with the input system clock even if the address is not newly output to the clock synchronous storage device 3. Holds output function.

As an example, it is assumed that the above-described clock synchronous storage device 3 is capable of fetching an address in two clocks and outputting data two clocks after the completion of the address fetch.

Therefore, as can be seen from the read access timing of the clock synchronous storage device in the conventional microprocessor shown in FIG. It can be seen that the required period of the address output to the clock synchronous storage device 3 is two clocks.

Here, an example of a technique for eliminating the waste of the bus cycle of the microprocessor described above is disclosed in Japanese Patent Laid-Open No. 3-3.
No. 3951. In the microprocessor system described in the publication, two or more storage devices are prepared as an external storage device or an internal storage device, and two addresses (if one address is 0, The other outputs data corresponding to address 1) to the latch circuit, and the microprocessor has a configuration in which the output data can be read at high speed by controlling the latch circuit. However, some clock synchronous storage devices that have been developed recently have already incorporated similar circuits.

[0035]

A first problem in the above-mentioned conventional microprocessor system is that the instruction execution processing in the microprocessor is performed at a high speed, and the program counter control unit receives an instruction for the next access. Despite being able to decode and prepare the address, due to the characteristics of the conventionally used asynchronous storage device, the microprocessor uses the data input from the asynchronous storage device for the output address. It was necessary to keep the address until it was read. For this reason, even when a system in which an asynchronous storage device and a clock synchronous storage device are mixed is constructed, a read data wait state of the microprocessor occurs when reading instructions and data.

The reason is that in the conventional external storage device, it is necessary to hold the input address until the data is determined.

The second problem is that the technique described in Japanese Patent Application Laid-Open No. 3-33951 and a recent similar prior art are used as a means for reducing the bus cycle of the microprocessor, separately from the main storage device. A separate storage device holding the same data as the data in the storage device was prepared, and the microprocessor could read data for two addresses with one address output, making high-speed access possible. However, it is necessary to generate a useless storage device area.

The reason for this is that, in the conventional storage device access of the microprocessor, the storage device holding the same data is provided so that the access is performed in an image such as bank switching.

An object of the present invention is to effectively access a clock synchronous storage device in view of the above-mentioned conventional disadvantages, and alleviates the state of waiting for read data from an external storage device of a conventional microprocessor. It is in.

[0040]

According to the present invention, there is provided a microprocessor system comprising: a microprocessor; a clock synchronous storage device provided outside the microprocessor;
A memory control circuit provided between the clock synchronous memory device and the microprocessor, wherein an address output control means of the microprocessor has an access address of a program counter initialized immediately after initialization of the microprocessor. latches, together thereafter latches the updated access address, and outputs the access address latched as the external address signal in response to a second logic level of the predetermined order address update request signal, the second logic The reverse polarity of the level
Address latch means for outputting the access address incremented by the program counter in response to one logical level as it is as the external address signal as it is, and an address decoder for decoding the external address signal and converting it to a chip select signal for output An address output unit having the first address and the second address update request signal. The first address of the next address update request signal is synchronized with the system clock when the chip select signal changes to an active level.
Transition from the initial output state for outputting a logic level to the next output state to generate a second logic level having a polarity opposite to the first logic level of the next address update request signal, and control means for the program counter and the address; After outputting to the latch means respectively, after a lapse of a predetermined period, the state shifts to the initial output state again to output the first logical level of the next address update request signal, and the chip select signal changes to the active level. An address output period counting unit having a state transition unit that repeats each time it changes and a temporary storage unit having a shift register configuration that holds the respective output states is provided.

The above-mentionedOutside the microprocessor
Input the local address signal and the chip select signal
And an output enable signal from the storage device control circuit.
And an asynchronous storage device for inputting
From the storage device control circuit.
In response to a supplied buffer control signal.
For connection between the processor and the clock synchronous storage device.
Buffer means for outputting to the data bus.
You.

Further, the address output control means outputs a command.
Address prefetching by command prefetching and the prefetched address
Address of the clock synchronous storage device specified by
Bus cycle at the time of
A function of controlling by lock synchronization may be provided .

Further, the address output control means
Interrupt and data to the microprocessor
For data access operation,
Before the address specified by the above-mentioned address.
The bus and bus for data access of the clock synchronous storage device
And each cycle are controlled by system clock synchronization
A function may be provided .

Further, there is provided an address output period setting register for setting an address output period of the clock synchronous storage device and the non-clock synchronous storage device, and this register output is output to the combination circuit of the address output period count circuit section. Can be output further.

[0045]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The gist of the present invention is to provide means for latching an address output from a program counter to a storage device in a system in which a microprocessor, a clock synchronous storage device and an asynchronous storage device are mixed, An address decoding means for decoding the output address and indicating which area is to be accessed, a signal for controlling an address latch by each chip select signal determined by the address decoding means, and an address for accessing the program counter next. It has an address output period counting means for generating a request signal, and outputs an address from a microprocessor to an external storage device at an optimal timing.

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of a microprocessor system according to the present invention.
FIG. 3 is a block diagram of an address generation unit built in the microprocessor. 3 is an internal configuration diagram of the address output control circuit unit in FIG. 2, FIG. 4 is a state transition diagram of the address output period count circuit in FIG. 3, and FIG. 5 is a read access operation in the first embodiment. 6 is a timing chart for explanation.

Referring to FIG. 1, the microprocessor system includes a microprocessor 1, a storage device control circuit 2, and a clock synchronous storage device 3. The microprocessor 1 has an address generation unit 10a, and the address CAD generated by the address generation unit 10a.
Signal, chip select CS bar signal, for example, CS1
A bar signal, a write / read control R / W bar signal, and a system clock CLK signal are output to the storage device control circuit 2, and a system clock CLK signal and a chip select CS1 bar signal are also output to the clock synchronous storage device 3. I do. The storage device control circuit 2 outputs a wait instruction WAIT signal to the microprocessor 1 and
An address SAD signal, a row address strobe RAS bar signal, a column address strobe CAS bar signal, and a write enable WE bar signal, which are separated into upper and lower addresses, are output to the clock synchronous memory device 3. A data bus is also connected between the clock synchronous storage device 3 and the microprocessor 1.

The address generator 10a includes an instruction decoder 11 which inputs and decodes an instruction fetched by the microprocessor 1 and converts the instruction into a control signal.
1. A jump destination address generation unit 12 for generating a jump destination address from the control signal decoded in step 1, and a stack control for jumping to a specific address specified by an interrupt vector address in response to an externally input interrupt signal. An interrupt control unit 13 for generating a signal; a stack control unit 14 for generating an address signal for designating a stack area of the storage control device based on the stack control signal from the interrupt control unit 13;
A program counter control unit 15 for controlling a program counter to specify a predetermined access address corresponding to each of the stack area address signal generated at step 1 or the jump address signal output from the jump address generation unit 12; Program counter control unit 1
The program counter address signal to be input from 5 is set, the access address is output by sequentially counting up as +1, 2 byte instruction +2, 1 byte instruction +2, 3 byte instruction +3, and the access address is output. The counter 16 receives an access address output from the program counter 16 and a data access address from a CPU (not shown), and outputs a system clock CLK signal, an R / W bar signal, and a CS1 bar signal to the outside. And a bus control unit for outputting an access address accessed by the microprocessor 1 to an address output control circuit unit 18 described later.
A unit 17 and a circuit added in the present embodiment, which generate a NEXT address update request signal from an access address accessed by the microprocessor 1 and output the NEXT address update request signal to the program counter control unit 15; It is provided with an address output control circuit section 18 for outputting.

Referring to FIG. 3, the address output control circuit 18 includes an address output period count circuit 181 and an address output circuit 182. The address output period count circuit section 181 receives the system clock CLK signal and the CS bar signal from the address output circuit section 182, respectively, and updates the next (NEXT) address with the result of logic synthesis by a combination circuit of logical product, logical sum and negation. A flip-flop (F / F) unit 184 (formed of a shift register,
(The number is determined according to the number of S-bar signals) and N of the output logic synthesis result
The EXT address update request signal is held in the F / F section 184 and is output to the address latch section 185 and the program counter control section 15 of the address output circuit section 182, respectively.

Address output circuit section 182 latches NEXT address (access address) output from bus control unit 17 in address latch section 185 in response to a NEXT address update request signal, and externally outputs the same as an external output address signal. The output is also output to the address decoder 186. The address decoder unit 186 decodes the input external output address signal, converts it into a chip select signal CS bar signal (of course, a plurality of CS bar signals exist, and each becomes CS1, CS2,...), And stores it in the combination circuit 183. It is configured to output to the device control circuit 2 and the clock synchronous storage device 3, respectively.

As described above, the address output period count circuit section 181 can be easily composed of a combination circuit of logical product, logical sum, and negation, and the output final stage can be easily composed of the F / F section. Therefore, detailed configuration examples of the internal circuit are omitted, and FIG. 4 shows a state transition diagram thereof.

Referring to FIG. 4, the state Ai is immediately after the initial setting, and outputs the NEXT address update request signal at a high level. When each chip select CS1 bar signal is at the active level, the state Aout1 outputs a NEXT address update request signal at a low level, and transitions to the state Aout2. Subsequently, when the next chip select CS1 bar signal is at the active level, the state Aout2 outputs the NEXT address update request signal at the low level, and transitions to the state Aout3. Subsequently, when the next chip select CS1 bar signal is at the active level, the state Aout3 becomes NEXT.
An address update request signal is output at a low level, and the state Ao
transits to ut4. Subsequently, when the next chip select CS1 bar signal is at the active level, the state Aou
Transition to t5. Similarly, each time the CS1 bar signal changes to the active level, the state changes, and the respective transition states are held in the F / F section 184.

Next, the operation will be described. Referring to FIG.
The operation until the fetched address is stored in the program counter 16 is the same as that of the above-described prior art. The program counter 16 outputs the stored fetch address, that is, the access address to the address output control circuit section 18 via the bus control unit 7. That is, in the internal operation of the address output control circuit unit 18 which is a feature of the present invention, first, the access address output from the program counter 16 is output to the address latch unit 185 as a NEXT address signal.

Referring also to FIG. 3, in the address output period count circuit section 181, the state transits to the Ai state immediately after the power is turned on.
It outputs the high level of the EXT address update request signal.
Here, the address latch unit 185 has a configuration of a high-through latch, and outputs the NEXT address signal to the clock synchronous storage device 3 and the storage device control circuit 2 as an external output address signal through.

The external output address signal output from the address latch section 185 is output to the address decoder section 186 at the same time as being output to the outside as described above. The address decoder section 186 decodes and decodes the area of the input external output address signal, and outputs the active level of the chip select CS1 bar signal suitable for the area to be accessed.

The address output period count circuit 181 is
When recognizing any active level of each chip select CS bar signal output from the address decoder unit 186, the system clock CL input
Aout is synchronized with the rising timing of the K signal.
Transition to state 1. At the same time as the transition to the Aout1 state, a low level of the NEXT address update request signal is output to the program counter controller 15 in order to make a NEXT address update request to the program counter 16. In response to the NEXT address update request signal, the program counter control unit 15 outputs a program counter address signal and operates the program counter 16 to update the counter value.

The program counter 16 outputs the updated value of the program counter to the address output control circuit 18 via the bus control unit 17 again, and outputs it as a NEXT address signal to the address latch 18.
Latch to 5.

In the Aout1 state, as described above, the low level of the NEXT address update request signal is output to the program counter control unit 15 and simultaneously to the address latch unit 185. The address latch unit 185
The aforementioned address a is output, and the input N
The EXT address signal is in a state of being latched by the address latch unit 185.

Here, referring again to FIGS. 1 and 5, the microprocessor 1 performs the following operations in cycle T1.
After the power is turned on, the latched address “a” is cycled T1.
To the storage device control circuit 2. Cycle T1
In the state shown in FIG.
The state has transitioned to the i state. Next, the bus cycle transits to the state of cycle TB1. At this time, since the address output period count circuit section 181 receives, for example, the active level of the CS1 bar signal requesting access to the area of the clock synchronous storage device 3 from the address decoder section 186, the system clock CLK Aout from Ai state, Aout
Transition to state 1. At this time, the microprocessor 1
One cycle is being executed.

When the storage control circuit 2 recognizes the input of the active level of the CS1 bar signal, which is the access request signal, from the microprocessor 1, it controls the RAS bar signal and the CAS bar signal to start the access. The internal operation of the storage device control circuit 2 will not be described in detail here.

The clock synchronous memory device 3 operates in synchronization with the rising timing of the bus clock output from the microprocessor 1, and receives the input CS1 bar signal, RAS bar signal, CAS bar signal, and WE bar signal. Is recognized at the rising timing of the system clock and the operation is performed.

First, the clock synchronous storage device 3 outputs the C output from the microprocessor 1 at the rising timing of the bus cycle TB1 of the microprocessor 1.
S1 bar signal, RA output from storage device control circuit 2
Recognizing the low level of the S bar signal, the address a output from the microprocessor 1 is taken in as an address SAD signal controlled by the storage control circuit 2 as a row address.

The storage device control circuit 2 outputs the low level of the CAS bar at the falling timing of the cycle TB1 of the system clock CLK signal, and simultaneously outputs the address corresponding to the column address of the address a to the address S.
Output as an AD signal.

The clock synchronous storage device 3 has a cycle T
In synchronization with the rising timing of B2, the high level of the RAS bar signal, the low level of the CAS bar signal,
An operation of recognizing the high level of the E-bar signal and taking in the column address is performed.

By the above-described operation, the fetching of the address of the clock synchronous storage device 3 is completed, and the data output timing and the number of output data can be changed by the user arbitrarily setting.

Next, the above-mentioned clock synchronous storage device 3
The operation of the address output control circuit 18 after the column address is fetched will be described.

In the Aout1 state of the address output period count circuit section 181, the program counter control section 1
5 is the low level of the NEXT address update request signal.
The level is output, and as in the operation described above, the updated value of the currently accessed address a is input to the address latch unit 185 of the address output circuit unit 182 as a NEXT address signal.

In this embodiment, when the address output period count circuit section 181 receives the active level of the CS1 bar signal when, for example, the CS1 bar signal among the chip select CS bar signals is the target in the Aout1 state. Is designed to transit to the Ai state at the rising timing of the next system clock CLK signal, and when transiting to the Ai state, the address output period count circuit section 181 outputs a high level of the NEXT address update request signal. , The address latch unit 185 updates the external output address to the address b.

By repeating the above operations, it is possible to perform the data transmission operation in the required minimum address output period and two cycles to the clock synchronous storage device 3, and the bus cycle of the microprocessor 1 However, useless cycles can be reduced, and access efficiency can be significantly improved. Further, since the microprocessor 1 can reduce the state of waiting for instructions and data, the maximum speed of the microprocessor can be obtained.

In the above-described operation, the same effect can be obtained not only in the instruction fetch operation of the microprocessor 1 but also in the operation during interrupt processing and the data access operation.

Next, a second embodiment will be described. FIG.
FIG. 7 is a configuration diagram of a microprocessor system according to a second embodiment of the present invention, and FIG. 7 is a timing chart for explaining a read access operation in the second embodiment.

Referring to FIG. 6, the microprocessor system includes a microprocessor 1, a storage device control circuit 2, a clock synchronous storage device 3, and an asynchronous storage device 4.
And a buffer 5. The difference from the first embodiment is that the asynchronous storage device 4 receives the address CAD signal and the chip select CS1 bar signal from the microprocessor 1 and receives the output enable OE bar signal from the storage control circuit 2, and Data (DATA) output from the asynchronous storage device 4 is input, and a buffer control signal is input from the storage device control circuit 2 to a data bus connecting the microprocessor 1 and the clock synchronous storage device 3. That is, the output buffer 5 is added. The other components are the same as those of the first embodiment, and the description of the configuration is omitted here.

In the operation of the microprocessor system, first, when the microprocessor 1 accesses the clock synchronous storage device 3 for the first time, the same operation as that described in the first embodiment is performed.

Next, when the program counter 16 is updated from the area of the clock synchronous storage apparatus 3 to the area of the asynchronous storage apparatus 4 by the operation in the first embodiment, the micro counter is updated at the rising timing of the cycle TB2. Address a output from processor 1 is updated to address b. Here, since the area of the address b is the area of the asynchronous storage device 4, the microprocessor 1
Needs to hold an output address until data input from the asynchronous storage device 4 is determined.

Thus, when an access to the asynchronous storage device 4 occurs from the address decoder 186 of the address output circuit 182, the address output control circuit 18 which is a feature of the present invention, As described in the first embodiment, the access is started from the Ai state, the state transitions in the order of the Aout1, Aout2, and Aout3 states, and the output of the address b is held. The asynchronous storage device 4 is different from the clock synchronous storage device 3 in that the data output timing is asynchronous. Therefore, the buffer 5 is provided and the storage device control circuit 2 controls the output of the buffer.

By outputting the address from the microprocessor 1 to the asynchronous storage device 4 during the previous bus cycle to the asynchronous storage device 4 according to the above operation, the bus bottleneck for the asynchronous storage device access (which has conventionally been a bottleneck). The state of waiting for read data from the external storage device of the microprocessor) can also be reduced.

Next, a third embodiment will be described. The system configuration is the same as in the second embodiment. Referring to FIG. 8 which shows a block diagram of an address generation unit with a built-in microprocessor according to the third embodiment, the difference from the first embodiment is that the address output control circuit unit 18 according to the present invention outputs an address. The width setting register 19 is further added, so that the transition state of the address output period count circuit section 181 can be made variable in accordance with each chip select CS signal inside the microprocessor.

That is, the address output control circuit 181
The input signal of the address output width setting register 19 is further input as an input signal of the combinational circuit section 183 of
By sequentially shifting this signal, the transition state of the combinational circuit unit 183 is made variable.

The configuration of the address output width setting register 19 varies depending on the number of chip select CS signals to be controlled, but can be easily realized by using a register configuration provided in the conventional microprocessor. .

According to the third embodiment, even when a plurality of clock synchronous storage devices and asynchronous storage devices are connected, an address can be output to each storage device at an optimum timing. Becomes

According to the present invention, the address output control circuit section 18 is provided in a system including only the microprocessor 1 and the clock synchronous storage device 3 and a mixed system including the clock synchronous storage device 3 and the asynchronous storage device 4. The address can be output to the external storage device at an optimal timing, and the access efficiency of the microprocessor to the external storage device is improved.

However, when a write access to the external storage device of the microprocessor 1 occurs, a conventional write cycle occurs after fetching the currently accessed read data in order to avoid data collision. However, in the present embodiment, the description is omitted because it is out of the gist.

As described above, when a system is configured using a clock synchronous storage device that has been recently developed, the clock synchronous storage device has a function of holding an address internally, and therefore, a conventional synchronous storage device is provided. Addresses can be fetched in a shorter time as compared with a storage device.

However, the conventional microprocessor holds the address until the instruction and the data have been fetched from the external storage device, and when accessing the instruction and the data from the external storage device for this address holding period. Although a bus neck (a state of waiting for read data from the external storage device of the microprocessor) has occurred, which has degraded the performance of the microprocessor, the present invention enables further prefetching of instructions and data, and the operation inside the microprocessor. Can be extracted to the maximum.

[0086]

As described above, the microprocessor system according to the present invention includes the address output control means for generating the next address update request signal from the access address and controlling and outputting the output period of the access address. The address output control means controls the address holding period for holding the access address to the external storage device until the operation is completed, so that the microprocessor can output the address to the external storage device at the optimal timing, and External access bus efficiency and at the same time read inside the microprocessor faster than conventional instruction and data accesses, reducing the wait for instructions and data from external storage. it can.

A conventional microprocessor uses a two-word read cycle for a clock synchronous storage device for 10 cycles.
In the case of performing the operation successively, a conventional microprocessor requires the number of access clocks of 60 clocks.

According to the address output control method of the microprocessor of the present invention, a two-word read cycle takes one cycle.
When the operation is performed 0 times continuously, the access can be performed with 24 clocks, and the number of access clocks of 36 clocks can be reduced.
The bus efficiency of 0% is improved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a first embodiment of a microprocessor system according to the present invention.

FIG. 2 is a block diagram of an address generation unit built in the microprocessor.

FIG. 3 is an internal configuration diagram of an address output control circuit unit in FIG. 2;

FIG. 4 is a state transition diagram of the address output period count circuit of FIG. 3;

FIG. 5 is a timing chart for explaining a read access operation in the first embodiment.

FIG. 6 is a configuration diagram of a microprocessor system showing a second embodiment of the present invention.

FIG. 7 is a timing chart for explaining a read access operation in the second embodiment.

FIG. 8 is a block diagram of an address generation unit with a built-in microprocessor according to a third embodiment;

FIG. 9 is a block diagram showing a configuration example of a conventional microprocessor system.

FIG. 10 is a block diagram showing an address generation unit incorporated in the microprocessor.

FIG. 11 is a timing chart for explaining read access to a clock synchronous storage device in a conventional microprocessor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Microprocessor 2 Storage device control circuit 3 Clock synchronous storage device 4 Asynchronous storage device 5 Buffer 10 Address generation unit 11 Instruction decoder 12 Jump destination address generation unit 13 Interrupt control unit 14 Stack control unit 15 Program counter control unit 16 Program counter 17 Bus control unit 18 Address output control circuit section 19 Address output width setting register 181 Address output period count circuit section 182 Address output circuit section 183 Combination circuit section 184 F / F section 185 Address latch section 186 Address decoder section

──────────────────────────────────────────────────続 き Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 12/00-12/06

Claims (4)

(57) [Claims] 1. A microprocessor, comprising: a microprocessor; a clock synchronous storage device provided outside the microprocessor; and a storage control circuit provided between the clock synchronous storage device and the microprocessor. Address output control means latches the access address of the initialized program counter immediately after the initialization of the microprocessor, and latches the updated access address thereafter,
The latched access address is output as an external address signal in response to a second logical level of a predetermined next address update request signal, and the program counter responds to the first logical level having a polarity opposite to the second logical level. Address latch means for outputting the incremented access address as it is as the external address signal as it is, address output means having an address decoder for decoding the external address signal and converting and outputting the chip address signal to a chip select signal; and It said chip select signal inputs the system clock in synchronism with the system clock and changes to the active level, before
Transition from the initial output state for outputting the first logical level of the next address update request signal to the next output state to generate a second logical level having a polarity opposite to the first logical level of the next address update request signal After outputting to the control means of the program counter and the address latch means, respectively, after a lapse of a predetermined period , transition to the initial output state is again performed to output the first logic level of the next address update request signal. Address output period counting means having state transition means repeated each time the chip select signal changes to an active level, and temporary storage means having a shift register structure for holding the respective output states. A microprocessor system characterized by the following. 2. An asynchronous memory device to which the external address signal and the chip select signal are inputted from the microprocessor and an output enable signal is inputted from the memory device control circuit, and which is outputted from the asynchronous memory device. 2. A buffer unit for outputting data to a data bus for connection between the microprocessor and the clock synchronous storage device in response to a buffer control signal supplied from the storage device control circuit. Microprocessor system. 3. The address output control means controls an address advance by instruction prefetch and a bus cycle at the time of data access of the clock synchronous storage device designated by the advance address in synchronization with a system clock. 2. The microprocessor system according to claim 1, wherein the microprocessor system has a function of performing the following. 4. The method according to claim 1, wherein the address output control means performs an address advance by an instruction prefetch for an interrupt and a data access operation to the microprocessor.
2. The microprocessor system according to claim 1, further comprising a function of controlling a bus cycle at the time of data access of said clock synchronous storage device designated by said first address in synchronization with a system clock.