JP3196422B2 - I / O protection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output protection circuit for protecting an internal circuit of a semiconductor device or the like from electrostatic breakdown.

[0002]

2. Description of the Related Art As an input / output protection element in a semiconductor device or the like, there is an NMOS transistor having a drain connected to an input / output terminal and a source and a gate grounded. This NMO
In an S transistor, the larger the channel width, the lower the current density during discharge, the higher the electrostatic breakdown voltage, and the better the electrostatic breakdown strength. However, if the channel width is, for example, 12
If the width is as large as 00 μm, the NMOS transistor becomes very elongated, and the semiconductor device itself needs to be enlarged.

Therefore, an input / output protection circuit has been proposed in which six NMOS transistors each having a channel width of 200 μm are connected in parallel to increase the overall channel width. FIG. 4 shows a conventional example of such an input / output protection circuit. In this conventional example, the drain 14 is connected between the input / output terminal 11 and the internal circuit 12 in a state where the drains 14 and the sources 15 of the six NMOS transistors 13 are connected in parallel as the same node. Output terminal 1
1 and the source 15, gate 16 and substrate 17 are grounded.

In this conventional example, when a high voltage is applied to the input / output terminal 11, the NMOS transistor 13
A parasitic bipolar transistor corresponding to the drain 14 as a collector, the source 15 as an emitter, and the substrate 17 as a base operates, and discharge is performed through the NMOS transistor 13. Therefore, the high voltage is not applied to the internal circuit 12 as it is, and the internal circuit 12 is protected.

[0005]

However, when a plurality of NMOS transistors 13 are connected in parallel as in the conventional example shown in FIG. 4, a parasitic bipolar transistor does not necessarily operate in all the NMOS transistors 13. It does not mean that the discharge is performed. The smaller the number of NMOS transistors 13 in which the parasitic bipolar transistors operate, the narrower the effective channel width and the higher the current density at the time of discharge.

For this reason, the NMOS transistor 13 itself is liable to break down due to heat generation, and the electrostatic breakdown voltage is lower than expected. In addition, it is known that when the NMOS transistor 13 has the LDD structure or the salicide structure, the electrostatic breakdown voltage is lower than when the NMOS transistor 13 has the single drain structure.

[0007]

In the input / output protection circuit according to the present invention, the drains of the plurality of NMOS transistors are connected to the input / output terminal in parallel with each other. Each source 15 is grounded, and each gate 16 of the plurality of NMOS transistors 13 is grounded via a resistor 21 in series.

In the input / output protection circuit according to claim 2,
In the input / output protection circuit of the above, between the drain 14 and the gate 16 or between the source 15 and the gate 16
And capacitive elements 24 and 25 are connected to at least one of them.

According to the input / output protection circuit of claim 3,
Alternatively, in the input / output protection circuit of No. 2, a non-linear element 31 which is forward from the input / output terminal side 11 to the power supply side is connected to the input / output terminal 11.

[0010]

In the input / output protection circuit according to the first aspect, the gate 16 of the NMOS transistor 13 is grounded via the resistance element 21 in series, so that a positive high voltage pulse having a very short rise time is applied to the input / output terminal 11. Is applied, the parasitic capacitance 22 between the gate 16 and the drain 14 and the gate 16
The gate voltage rises to a voltage obtained by dividing the voltage between the drain 14 and the source 15 with the parasitic capacitance 23 between the source 15. For this reason, at the time of discharging, the NMOS transistor 13 is in a conductive state or a state close to the conductive state, and in many NMOS transistors 13, the parasitic bipolar transistor is easily operated.

Moreover, even if the gate voltage of the NMOS transistor 13 rises to the above-mentioned voltage, the parasitic capacitance 2 between the gate 16 and the drain 14 and between the gate 16 and the source 15
The gate voltage attenuates to 0 V due to the time constant of the resistance elements 2 and 23 and the resistance element 21. Therefore, a parasitic bipolar transistor operates in the NMOS transistor 13, and
At the same time, the channel current of the NMOS transistor 13 flows
Even if this, the channel current does not continue to flow . As a result, the destruction of the NMOS transistor 13
Is prevented.

In the input / output protection circuit according to the second aspect, the NMOS
Since the voltage applied to the gate 16 of the transistor 13 can be controlled and optimized by the capacitors 24 and 25, an excessive current flowing through the channel of the NMOS transistor 13 during discharging can be prevented.

In the input / output protection circuit according to the third aspect, the voltage of the input / output terminal 11 is reduced by the non-linear element 31 during discharge.
It is possible to reduce the voltage quickly without holding the voltage around the snapback voltage of the OS transistor 13.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, first to third embodiments of the present invention will be described with reference to FIGS. Note that the same reference numerals are given to components corresponding to those in the conventional example shown in FIG.

FIG. 1 shows a first embodiment. The first embodiment is different from the conventional one shown in FIG. 4 except that the gates 16 are also connected in parallel as the same node, and this node is grounded via a resistance element 21 in series. It has a configuration substantially similar to the example.

Parasitic capacitances 22 and 23 such as overlap capacitances exist between the gate 16 and the drain 14 and between the gate 16 and the source 15 of the NMOS transistor 13, respectively. The gate 16 is grounded via the resistor 21 in series. Therefore, when a positive high voltage pulse having a very short rise time is applied to the input / output terminal 11, the gate 16 is driven to a voltage obtained by dividing the voltage between the drain 14 and the source 15 by the parasitic capacitances 22 and 23. Voltage rises.

As described above, immediately after the high voltage is applied to the input / output terminal 11, the gate 1 of each NMOS transistor 13
Since the same positive voltage is applied to 6, each NMOS transistor 13 is in a conductive state or a state close to the conductive state, and in many NMOS transistors 13, a parasitic bipolar transistor easily operates. Therefore, the effective channel width of the entire six NMOS transistors 13 connected in parallel is wide, and the current density at the time of discharging is small.

On the other hand, if the NMOS transistor 13 is kept conductive, the current flowing through its channel becomes excessive, and the NMOS transistor 13 is easily damaged. N
When the MOS transistor 13 is broken, a leak current may flow through the broken NMOS transistor 13.

However, in the first embodiment, the resistance element 2
1 is R, the capacitance values of the parasitic capacitances 22 and 23 are c ₁ and c ₂ , respectively, and the size of each NMOS transistor 13 is the same and C ₁ = c ₁ × 6 and C ₂ = c ₂ × 6. Then
With the time constant of τ = (C ₁ + C ₂ ) R, the voltage of the gate 16 attenuates to 0V. Therefore, the NMOS transistor 1
3 does not remain conductive.

Thus, the six Ns connected in parallel
Since the effective channel width of the entire MOS transistor 13 is wide and the current density at the time of discharge is small, and the current flowing through the channel of the NMOS transistor 13 does not become excessive, the NMO is not heated.
The S transistor 13 is less likely to break down and has a high electrostatic breakdown voltage.

In the first embodiment, after the gates 16 are connected in parallel as the same node,
Are serially grounded, it is possible to apply the same bias voltage to the gate 16 as compared with the structure in which each gate 16 of each NMOS transistor 13 is grounded via the resistance element 21 in series. .

FIG. 2 shows a second embodiment. The second embodiment is different from the first embodiment shown in FIG. 1 except that capacitors 24 and 25 are connected to at least one of between the drain 14 and the gate 16 or between the source 15 and the gate 16. It has a configuration substantially similar to that of the embodiment.

The voltage applied to the gate 16 of the NMOS transistor 13 at the time of discharging may be slightly higher than the threshold voltage. If the voltage is too high, an excessive current may flow through the channel of the NMOS transistor 13.
However, in the above-described first embodiment, since the voltage applied to the gate 16 is determined by the parasitic capacitances 22 and 23,
It is difficult to control this applied voltage to an appropriate value.
On the other hand, in the second embodiment, the applied voltage can be controlled and optimized by the capacitors 24 and 25.

FIG. 3 shows a third embodiment. The third embodiment is similar to the third embodiment shown in FIG. 2 except that the source 32 of the PMOS transistor 31 is connected to the input / output terminal 11 and the drain 33, the gate 34, and the substrate 35 are connected to a power supply. It has a configuration substantially similar to that of the two embodiments.

In the third embodiment, the input / output terminal 11
Is lower than the power supply voltage, PM
Since the source 32 of the OS transistor 31 and the substrate 35 are reverse-biased, the source 32 and the substrate 35
No current flows between them. However, when a voltage higher than the power supply voltage is applied to the input / output terminal 11, the source 32 and the substrate 35 are forward-biased.
A current flows between the substrate 2 and the substrate 35. Therefore, PMOS
The source 32 of the transistor 31 and the substrate 35 function as a diode which is a non-linear element.

When a voltage higher than the power supply voltage is applied to the input / output terminal 11, the gate 3 connected to the power supply
Since the voltage of the source 32 becomes higher than the voltage of
The OS transistor 31 becomes conductive, and a current also flows through the channel as the PMOS transistor 31.

In the first and second embodiments , the positive high voltage pulse is applied to the input / output terminal 11.
Later , the voltage between the drain 14 and the source 15 becomes NMO
It is maintained at about the snapback voltage of the S transistor 13. However, in the third embodiment, the PMO
Since a current flows through the S transistor 31, the input / output terminal 1
1 can be quickly reduced without holding the voltage of about 1 at about the snapback voltage of the NMOS transistor 13.

As described above, the source 32 of the PMOS transistor 31 and the substrate 35 function as a diode. However, it is more difficult to form the PMOS transistor 31 than to form a diode instead of the PMOS transistor 31. MOS for the entire device manufacturing process
This is preferable because it can be standardized in the transistor manufacturing process.

[0029]

In the input / output protection circuit according to the first aspect, the parasitic bipolar transistors easily operate in many NMOS transistors at the time of discharge, so that the current density in each NMOS transistor is small and the parasitic bipolar transistor operates in the NMOS transistor. I do not keep doing it. For this reason, NM occurs due to heat generation during discharge.
The OS transistor is less likely to break down and has a high electrostatic breakdown voltage.

In the input / output protection circuit according to the second aspect, excessive current can be prevented from flowing through the channel of the NMOS transistor at the time of discharging.
Higher electrostatic breakdown voltage.

In the input / output protection circuit according to the third aspect, the voltage of the input / output terminal can be rapidly reduced without maintaining the voltage of the input / output terminal at the level of the snapback voltage of the NMOS transistor at the time of discharge. , And the electrostatic breakdown voltage is higher.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of a first embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of the second embodiment.

FIG. 3 is an equivalent circuit diagram of a third embodiment.

4A and 4B show a conventional example of the present invention, wherein FIG. 4A is an equivalent circuit diagram, and FIG. 4B is a plan view.

[Explanation of symbols]

 Reference Signs List 11 input / output terminal 13 NMOS transistor 14 drain 15 source 16 gate 21 resistive element 24 capacitive element 25 capacitive element 31 PMOS transistor

Claims (3)

(57) [Claims] 1. A drain of each of the plurality of NMOS transistors is connected to an input / output terminal in parallel with each other, a source of each of the plurality of NMOS transistors is grounded, and a gate of each of the plurality of NMOS transistors. An input / output protection circuit characterized in that: is grounded via a resistance element in series. 2. The input / output protection circuit according to claim 1, wherein a capacitor is connected to at least one of between the drain and the gate or between the source and the gate. 3. The input / output protection circuit according to claim 1, wherein a non-linear element extending in a forward direction from the input / output terminal side to the power supply side is connected to the input / output terminal.