JP3194381B2 - Bus management method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Detailed description of the invention]

[0002]

2. Description of the Related Art There has been proposed a communication system in which AV devices such as digital VTRs, monitors, tuners and the like, personal computers and the like are connected to a bus, and digital video signals, digital audio signals and the like are transmitted and received between these devices.

[0003] As this type of communication system, the one shown in FIG. 8 has been proposed. This communication system includes a root (root) node 21, a leaf (leaf) node 22, a branch (branch) node 23, a leaf node 24, a leaf node 2
5 is provided. Then, between the nodes 21 and 22, between the nodes 21 and 23, between the nodes 23 and 24, and between the nodes 23 and 2
The input / output ports between the five are connected by two twisted pair cables. As described above, the nodes 21 to 25 are a digital VTR, a monitor, a tuner, a personal computer, and the like, and each have one or more input / output ports.
Since each node 21 to 25 has a built-in amplifier and repeater, the communication system in FIG. 8 is the same as the communication system in which each node 21 to 25 is connected to the bus 26 as shown in FIG. Are equivalent.

FIG. 8 shows a hierarchical structure in which a node 22 and a node 23 are connected below a node 21, and a node 24 and a node 25 are connected below the node 23. In other words, node 21 is node 2
2 and 23 are parent nodes, and node 23 is node 24
And the parent node of the node 25. First, a procedure for determining the hierarchical structure will be described.

[0005] Between nodes 21-22, 21-23, 23
If cables are connected between -24 and 23-25, 1
A node in which only the I / O ports are connected to another node transmits to the node connected thereto that the other party is the parent node. In the case of the communication system shown in FIG. 8, the nodes 24 and 25 communicate to the node 23 that the node 23 is the parent node, and the node 22 informs the node 21 that the node 21 is the parent node. introduce.

A node having a plurality of input / output ports connected to another node is a parent node with respect to a node other than the node that has transmitted the fact that the node is a parent node to itself. Communicate to the effect. In the case of FIG. 8, node 2
3 informs node 21 that node 21 is the parent node, and node 21 informs node 23 that node 23 is the parent node. At this time, node 2
Since node 1 and node 23 communicate with each other that the partner node is the parent node, the node that has previously been notified of the parent node is the parent node. FIG.
Indicates that the node 21 has become the parent node.

Next, a procedure for assigning an address of each node will be described. The address of a node is basically obtained by allowing a parent node to assign an address to a child node. If there are multiple child nodes, for example,
Permits in order from the child node connected to the port with the lowest port number.

In FIG. 8, when the node 22 is connected to the port # 1 of the node 21 and the node 23 is connected to the port # 2, the node 21 permits the node 22 to assign an address. The node 22 assigns an address to itself, and sends data indicating that the address has been assigned to itself to the bus. Next, the node 21
Allows the address to be determined. The node 23 permits the node 24 connected to the port # 1 to assign an address. The node 24 assigns an address to itself. Next, the node 23 permits the node 25 connected to the port # 2 to assign an address.
The node 25 assigns an address to itself. Node 2
3 assigns an address to itself when the address assignment of the child nodes 24 and 25 is completed. The node 21 assigns an address to itself when the address assignment of the child nodes 22 and 23 is completed.

In the communication system shown in FIG. 8, both synchronous communication for continuously communicating at a constant data rate like a digital video signal and asynchronous communication for transmitting a control command or the like irregularly as necessary. It can be performed.

In this communication system, as shown in FIG. 10, communication is performed in a communication cycle of a predetermined cycle, for example, a cycle of 125 μs. At the beginning of the communication cycle, there is a cycle start packet csp, followed by a period for transmitting a packet for synchronous communication. A plurality of synchronous communications can be performed by assigning channel numbers 1, 2, 3,... N to each bucket for performing the synchronous communications. For example, assuming that channel 1 is allocated to the communication from the node 22 to the node 23, the node 22 transmits a synchronous communication packet with the channel number 1 immediately after the cycle start packet csp, and the node 23 monitors the bus. The communication is performed by taking in a synchronous communication packet with channel number 1. Similarly, channel 2 can be assigned to communication from node 24 to node 21, for example. A plurality of nodes can receive a packet of one channel.

When a plurality of synchronous communications are performed, transmission of synchronous communication packets of a plurality of channels is attempted immediately after the cycle start packet csp. In this case, arbitration means (for example, CSMA / CSM) determined by a bus is used. C
According to D), first, a synchronous communication packet of one channel is transmitted, and subsequently, a synchronous communication bucket of another channel is sequentially transmitted.

After the transmission of the synchronous communication packets of all the channels is completed, a period until the next cycle start packet csp is used for asynchronous communication. Asynchronous communication buckets (buckets A and B in FIG. 10) have addresses of the transmitting node and the receiving node, and each node takes in a packet with its own address.

Since the details of the communication system described above are disclosed as "IEEE P1394 Serial Bus Specifications", further detailed description will be omitted.

[0014]

In order for the above-mentioned communication system to operate properly, each synchronous communication has a different channel number and the total communication time of synchronous communication packets of all channels is determined by the synchronous communication. It is necessary to manage so as not to exceed the cycle of To do this, before a node starts synchronous communication, it is necessary to first check whether the communication capacity required for the communication remains on the bus, and if so, assign a channel that is not being used. is there.

In order to manage the communication capacity and the channel number used in the synchronous communication, one of the nodes connected to the bus usually serves as a bus management node to perform necessary management. In this case, before starting the synchronous communication, the other nodes first indicate the communication capacity to be used to the bus management node using the asynchronous communication packet, and request the channel management to allocate the channel. The bus management node checks whether adding the requested communication capacity to the already used synchronous communication communication capacity does not exceed the maximum communication capacity of the bus. Then, if it does not exceed, it notifies the permission of the synchronous communication together with the unused channel number, and if it exceeds, it notifies that the channel assignment is rejected. When the synchronous communication is completed, the communication capacity and the channel number which are not used are notified to the bus management node.

As described above, the bus management requires complicated processing. For example, in a communication system centering on a personal computer or the like, by using a personal computer as a bus management node, the software provided in the personal computer can be used. Processing is usually performed. When this method is applied to a communication system between AV devices such as a digital VTR, a tuner, and a modem,
Since it is necessary to connect a device having a powerful data processing function, such as a personal computer, to the bus in addition to the device, the cost of the communication system increases.

The present invention has been proposed to solve such a problem. In a system for performing synchronous communication between a plurality of nodes connected to a bus, a method for easily managing a bus is proposed. The purpose is to provide.

[0018]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention relates to a bus management method in a system for performing synchronous communication between a plurality of nodes connected to a bus. Medium, first storage means for storing the use status of the channel, and second storage means for storing the use status of the bus
A predetermined node provided with the storage means is defined as a bus management node, and when each node starts synchronous communication, the contents of the first and second storage means are read out, and if there is a free channel and a free capacity, use is started. The number of the channel to be used and the bus capacity are written in the first and second storage means, respectively.

Here, each node has a plurality of communication clocks having different frequencies.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a bus management method according to the present invention will be specifically described with reference to the drawings.

FIG. 1 is a diagram for explaining the concept of the present invention, and FIG. 2 is a diagram showing an example of the configuration of the used channel register and the bus capacity register in FIG.

Here, as shown in FIG. 1, the bus management node 11 is provided with a used channel register REG1 and a bus capacity register REG2. Further, as shown in FIG. 2A, the used channel register REG1 is
For example, it has a capacity of 32 bits, and each bit indicates the use state of channels 0 to 31 (1: in use, 0: unused). Further, the bus capacity register REG2 is
As shown in (b), for example, it has a capacity of 32 bits,
It has a value indicating the total remaining capacity of the bus or the capacity in use.

Before starting the synchronous communication, the other nodes 12 in the communication system use the used channel register REG1 provided in the bus management node 11 with an asynchronous communication packet.
Then, a read command is transmitted to the bus capacity register REG2 and the contents thereof are read to confirm the number of the unused channel and the remaining capacity of the bus. If there is an unused channel and the remaining capacity of the bus, the number of the channel to be used and the capacity of the bus to be used are stored in these registers so that they are stored in the used channel register REG1 and the bus capacity register REG2, respectively. Send a write command to it. When the bus management node 11 starts synchronous communication, the same processing is performed by giving a write command and a read command to the internal use channel register REG1 and the bus capacity register REG2.

When the present invention is applied to the communication system shown in FIG. 8 described above, all the nodes 11 and 12 are provided in the used channel register REG1 and the bus capacity register REG2. Then, the bus management node 11 is set to the node 21 which is the root node. If the use channel register REG1 and the bus capacity register REG2 are provided for all nodes, the bus can be managed regardless of which node becomes the root node. Also, a node other than the root node can be set as a bus management node.

Hereinafter, the method of the present invention will be described more specifically with reference to FIGS. In the following flowchart, YES in the determination step is Y,
NO is abbreviated as N.

FIG. 3 is a flowchart showing an example of a procedure for taking a channel before starting synchronous communication.

In this figure, node 1 which performs synchronous communication
2. First, in step S1, a command for reading the contents of the used channel register REG1 in the bus management node 11 is transmitted, and the read contents of REG1 are checked to determine whether or not there is a bit of 0. If there is no 0 bit, the process is terminated because there is no free channel. Also,
If there is a pit of 0, a write command for setting the bit corresponding to the channel number to be used to 1 is transmitted in step S2.

Next, at step S3, the bus management node 1
2. The instruction to read the contents of the bus capacity register REG2 is transmitted to the channel register REG2.
Look at the contents of 1. Then, the value of the bus capacity register RED2, ie, the remaining capacity of the bus, is compared with the bus capacity value newly used in the synchronous communication. If the value of the bus capacity register RED2 is larger or equal, the synchronous communication is possible. In step S4, a write command is transmitted to set a value obtained by subtracting the newly used bus capacity value from the value of the bus capacity register RED2 as a new value of the bus capacity register RED2. In step S5, synchronous communication is started. I do. On the other hand, if the newly used bus capacity value is larger in step S3, synchronous communication cannot be performed.
Transmits a write command for returning the bit set to 1 in step S2 to 0 (step S6).

FIG. 4 is a flowchart showing an example of a procedure for returning a channel after ending synchronous communication. In the following description, the description of transmitting a read command when reading the contents of the registers RED1 and RED2 and transmitting a write command when rewriting the contents of the registers RED1 and RED2 will be omitted.

In FIG. 4, when the communication is completed in step S11, first, in step S12, the bit corresponding to the channel number for which the use channel register REG1 has been used is reset to 0. Next, step S13
Then, the used bus capacity value is added to the value of the bus capacity register RED2.

According to the above-described procedure, the bus management node 11 can allocate the channel by a simple operation merely responding to the write command and the read command. In this procedure, a plurality of nodes compete. In this case, correct processing cannot be performed. Therefore, a procedure that can cope with such a case will be described with reference to FIGS.

FIG. 5 shows the used channel register RED1.
4 is a flowchart showing a procedure for setting the bit of the data, that is, a procedure corresponding to steps S1 and S2 shown in FIG.

First, in step S21, the node 2 reads the value of the used channel register RED1. This value is a
Then, in step S22, the node 12 determines whether or not a has a 0 bit. The above processing is substantially the same as step S1 in FIG. Then, if there is no pit of 0 in a, there is no free channel, so the node 2 ends the procedure for taking a channel. If a has a bit of 0, a value obtained by setting the bit of the channel to be used for the synchronous communication to 1 is set to b in step S23.
And Then, in step S24, if the value of the used channel register RED1 is a, this is rewritten to b.

Step S24 is a process provided to avoid a conflict with another node 12. This step S2
4 indicates that the node that actually wants to take a channel notifies the bus management node 11 of the used channel register RED1.
If the value of a is a, this is realized by sending an instruction to rewrite this to b. The fact that the value of the used channel register RED1 is a means that this node
Means that another node 12 has not rewritten the value of the used channel register RED1 between the time when the value of the used channel register RED1 was read and the step S24. On the other hand, the used channel register R
That the value of ED1 is not a means that another node 12 has rewritten the value of the used channel register RED1.

Next, the node 12 determines whether or not the rewriting has succeeded in step S25. If the rewriting has succeeded, the node 12 ends the processing. If the rewriting has failed, the node 12 proceeds to step S21. Here, the success / failure is determined, for example, by the bus management node 11.
May be performed based on the notification of the write result transmitted from the CPU, or may be performed by reading the value of the used channel register RED1 and confirming whether or not the value has been rewritten to b.

FIG. 6 shows a bus capacity register RED2.
The procedure for subtracting the bus capacitance value from the value in FIG.
6 is a flowchart showing a procedure corresponding to steps S3 and S4 of FIG.

First, in step S31, the node 12
Read the value of the bus capacity register RED2. Assuming that this value is c, a magnitude relationship between c and the newly used bus capacity value is determined in step S32. The above processing is substantially the same as step S3 in FIG. If c is smaller than the newly used bus capacity value, synchronous communication cannot be performed, so that the value of the used channel register RED1 is returned to the original value as in step S6 of FIG. Also,
If c is larger than the newly used bus capacity value, synchronous communication is possible, and the node 12 proceeds to step S33.
Then, a value obtained by subtracting the bus capacity value to be used from c is d. Then, in step S34, the bus capacity register RE
If the value of D2 is c, node 2 rewrites it to d.

Step S34 is a process provided to avoid a conflict with another node 12. The fact that the value of the bus capacity register RED2 is c indicates that this node 12
Means that no other node has rewritten the value of the bus capacitance between the time when the value of the bus capacitance register RED2 was read in step S31 and the time in step S34. On the other hand, the fact that the value of the bus capacity register RED2 is not c means that another node has rewritten the value of the bus capacity register.

Next, the node 2 determines whether or not the rewriting has succeeded in step S35. If the rewriting has succeeded, the node 2 ends the process. If the rewriting has failed, the process proceeds to step S31.

FIG. 7 shows a procedure for adding the bus capacity value to the value of the bus capacity register RED2, that is, step S shown in FIG.
13 is a flowchart illustrating a procedure corresponding to No. 13.

First, in step S41, the node 12
The value of the bus capacity register RED2 is read, and this value is set to e. Next, in step S42, the node 12 sets f to a value obtained by adding the used bus capacitance value to e. Next, in step S43, the node 12 sets the bus capacity register RED.
If the value of 2 = e, this is rewritten to f. And
In step S44, the node 12 determines whether the rewriting has succeeded. If the rewriting has succeeded, the node 12 ends the process. If the rewriting has failed, the node 12 proceeds to step S41. The meaning of each process in this procedure is clear from the description of FIGS. 5 and 6 described above, and thus detailed description is omitted.

Here, the values stored in the bus capacity register RED2 will be described.

In this example, the bus capacity register RED2 is
In the synchronous communication cycle of 125 μs, a value obtained by counting, for example, a basic clock for communication as a unit of a time not used yet, that is, a value in units of time, of a period usable for synchronous communication is stored. As an example, 98.304 Mb
ps bus system, the communication basic clock is 49.1
In the case of 52 MHz, 100 μs out of 125 μs can be used for synchronous communication (the remaining 25 μs corresponds to FIG.
As shown by 0, it is used for transmission of a cycle start bucket and asynchronous communication. ), The maximum value of the bus capacity is equivalent to 4915 basic clocks. Therefore, the bus capacity register RED2 is initially set to 4915, and each time a channel is allocated to the node 12, the value is reduced by the number of clocks corresponding to the used bus capacity value.

For example, when starting 10 Mbps synchronous communication, 1250 bits of data are transmitted per synchronous communication cycle. The time required to transmit this data is the time obtained by adding the overhead time required for bus arbitration and the like to the 625 basic clock cycle for transmitting the data body. Assuming that the overhead is 1 μs, this corresponds to 50 basic clock periods, so that a total of 6
75 is subtracted from the bus capacity register RED2.

Each node in the communication system has a plurality of basic clocks having different frequencies (eg, 4.152 MHz,
× 49, 152 MHz, 4 × 4 9.152 MHz, etc.)
In the case where synchronous communication is performed using different basic clocks, the value stored in the bus capacity register RED2 is a value selected from a plurality of basic clocks when performing synchronous communication using any of the basic clocks. What is necessary is just to make it the value counted by the basic clock.

Next, the operation when the configuration of the communication system changes during the synchronous communication will be described. For example, in the communication system of FIG.
If the cable between the node 21 and the node 23 is disconnected during the synchronous communication between the nodes 4, the bus management node disappears in the communication system including the nodes 23 and 24.

Therefore, in order to avoid such a problem,
When a node is disconnected or connected during synchronous communication, a node (root node) having the largest address in a communication system having a new configuration is set as a new bus management node. Then, the node that was performing the synchronous communication executes the channel acquisition procedure for the new management node within a predetermined time after the bus management node is determined, and the node that newly starts the synchronous communication executes the predetermined time lapse. It is configured to execute the channel acquisition procedure later. The node that was performing the synchronous communication may start the synchronous communication immediately after the new management node is determined, and may execute the channel acquisition procedure in parallel.

In this way, even when the management node changes, a channel is preferentially allocated to the node that was performing synchronous communication before the management node changed,
The state before the change of the management node is reflected in the register of the new management node.

As described above, all nodes in the communication system use the used channel register REG1 and the bus capacity register R.
Although it is assumed that the node has EG2, otherwise, for example, a node having the used channel register REG1 and the bus capacity register REG2 is searched in order from the node at address 0, and the first node found is set as the bus management node. Good.

[0050]

As described above, according to the present invention, the bus management node responds to the read command and the write command for the first storage means and the second storage means, and manages the channel number and the bus capacity. It can be implemented with simple hardware.

Further, since each node performs communication using a plurality of communication clocks having different frequencies, communication at different speeds can be mixed for each channel.
It can handle data of different transmission rates such as video data and audio data.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a communication system in which a bus management method according to the present invention is used.

FIG. 2 is a diagram illustrating an example of a configuration of a used channel register and a bus capacity register provided in a bus management node.

FIG. 3 is a flowchart illustrating an example of a procedure for taking a channel before starting synchronous communication.

FIG. 4 is a flowchart illustrating an example of a procedure for returning a channel after ending synchronous communication.

FIG. 5 is a flowchart showing a procedure for setting a bit of a used channel register while avoiding contention between nodes.

FIG. 6 is a flowchart showing a procedure for subtracting a bus capacity value from a value of a bus capacity register while avoiding competition between nodes.

FIG. 7 is a flowchart showing a procedure for adding a bus capacity value to the value of a bus capacity register while avoiding contention between nodes.

FIG. 8 is a diagram illustrating an example of a communication system that performs synchronous communication between a plurality of nodes connected to a bus.

FIG. 9 is a block diagram equivalently showing the communication system shown in FIG. 8;

FIG. 10 is a diagram illustrating an example of a data structure on a bus in the communication system illustrated in FIG. 8;

[Explanation of symbols]

11 bus management node, 12 other nodes, 21
Root node, 22, 24, 25 leaf node,
23 branch node, REG1 used channel register, REG2 bus capacity register

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Hisato Shima 6-7-35 Kita Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (56) References JP-A-3-218139 (JP, A) JP-A Heisei 3-249838 (JP, A) JP-A-63-46837 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 12/28

Claims (2)

(57) [Claims] 1. A bus management method in a system for performing synchronous communication between a plurality of nodes connected to a bus, wherein the first storage means for storing a use state of a channel among the plurality of nodes and use of the bus. A predetermined node provided with a second storage means for storing a situation is defined as a bus management node. Each node reads the contents of the first and second storage means when starting synchronous communication, and determines whether an available channel and an available capacity are available. If there is, a bus management method characterized by writing the number of the channel to start using and the bus capacity to the first and second storage means, respectively. 2. The bus management method according to claim 1, wherein each node has a plurality of communication clocks having different frequencies.