JP3193533B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and
SFET (Metal Insulator Semiic)
conductor Field Effect Tra
(nsistor) manufacturing method.

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, "The 43rd Integrated Circuit Symposium 1992
Held on December 10-11, 2000. 102 to 107 ".

FIG. 9 is a sectional view of such a conventional general N-type MOS transistor.

In FIG. 1, a P-type silicon substrate 21
A gate oxide film 23 and a field oxide film 25 are formed thereon by heat-treating an N-type source and drain 22 and a silicon substrate 21 on the surface, and a gate electrode made of polycrystalline Si is formed on the gate oxide film 23. 24, and a wiring isolation insulating film 26 is formed thereon. Therefore, a contact hole is formed in the wiring isolation insulating film 26 by selective etching, and the wiring metal film 27 is wired.

One problem of the MOS transistor having such a structure is that the reliability of the MOS transistor is reduced due to dielectric breakdown of the gate insulating film (oxide film) 23.

FIG. 10 shows the configuration of an apparatus for examining the electric breakdown voltage characteristics of the gate oxide film 23. As shown in FIG.

As shown in FIG. 1, a gate oxide film 32 is formed on a P-type substrate 31, and an oxide film of 10 to 50 nm is generally used as the gate oxide film 32 at present. In addition, a polycrystalline Si gate electrode 33 is formed on the gate oxide film 32. In this investigation, in order to improve the sensitivity of the breakdown voltage, the area is much larger than that of a normal transistor, for example, 10 to 30 mm ^2. Is used.

In the structure thus manufactured, the terminal 34 is brought into contact with the polycrystalline Si gate electrode 33, and the breakdown voltage of the gate oxide film 32 is measured. As a measuring method at this time, the voltage at which the specified current flows is determined by the ammeter 36 to be the withstand voltage of the gate oxide film 32 by sequentially increasing the variable voltage source 35 from a low voltage.

At this time, the gate oxide film 32 (film thickness 20 n
FIG. 11 shows the breakdown voltage distribution of m), where the horizontal axis represents the breakdown voltage (V) and the vertical axis represents the failure rate (%).

The gate oxide film 32 has a thickness of 20 nm.
The area of the polycrystalline Si gate electrode 33 is 20 mm ² ,
The judgment current is 4 μA / mm ² . The breakdown voltage of the gate oxide film 32 is divided into a low voltage group called an A mode group, a medium voltage B mode group, and a general breakdown voltage distribution which is distributed in a C mode group indicating the intrinsic breakdown voltage of the oxide film. Is shown.

[0011]

As described above, in a gate oxide film of a generally formed transistor, A
Since there is a low breakdown voltage section called a mode or a B mode, there is a problem that reliability is reduced.

In order to solve this problem, Japanese Patent Application No. Hei 4-217080 proposed by the inventor of the present application charges the surface of the gate oxide film, grows uniform CVD polycrystalline Si, and controls the breakdown voltage. There has been proposed a method of improving the particle size, and a method of cleaning in an ionic solution since particles are attached by the charging treatment. FIG. 12 shows the result. It can be seen that this method significantly reduces the failure in the AB mode. However, A.
The B mode is not completely eliminated, and the occurrence of several% is measured.

[0013] As described above, Japanese Patent Application No. 4-217080 discloses that the withstand voltage of the gate oxide film is improved.
Particles adhering to the oxide film surface are completely removed by the brush scrub, and after that, by washing in an ionic solution, charged charges are released to the oxide film surface, and the electrostatically adsorbed particles are removed. It is assumed that the polycrystalline Si film thereafter grows uniformly and the withstand voltage of the gate oxide film is improved, and the change of the oxide film due to charging is not specifically shown.

However, the subsequent research (43
Integrated Circuit Symposium 102-107)
It is reported that the withstand voltage of the oxide film is improved by eliminating the weak spots of the oxide film by the charging treatment as shown in FIG.

That is, as shown in FIG. 13A, in the oxide film 42 on the silicon substrate 41, the silicon substrate 4
1A and an oxide film defect (generally called a weak spot) 43A generated during the growth of the oxide film.

When the oxide film 42 is rubbed with pure water, charges 44 are charged on the surface of the oxide film 42 as shown in FIG. When the electric field strength of the electric charge 44 becomes equal to or higher than the breakdown voltage strength of the weak spot 43A, breakdown occurs in the oxide film part 43 'including the weak spot 43A, a current flows, and Joule heat is generated. When the Joule heat approaches the melting temperature of the oxide film, a flow phenomenon occurs, and a stable SiO bond is obtained.

The charge charging due to the friction, the breakdown at the weak spot 43A, the generation of Joule heat, and the phenomenon of stable SiO bonding due to the flow occur intermittently, and as shown in FIG. The weak spot 43A of 42 disappears, the breakdown voltage of the oxide film 42 improves, and the A-mode and B-mode defects disappear.

However, on the surface of the oxide film 42, electric charges 44
As shown in FIG. 13D, particles 45 are deposited on the surface of the oxide film 42 during the heat treatment during the growth of polycrystalline Si and the dwell time until the charge reduction step in the ionic solution cleaning, as shown in FIG. Adsorb electrostatically.

The particles 45 are difficult to remove even in the subsequent cleaning, and become a source of contamination in the heat treatment during the growth of the polycrystalline Si 46, thereby generating a new weak spot 43B as shown in FIG. Then, the integrity of oxide film 42 is lost. That is, there is a problem that the A and B modes are not completely eliminated and a few percent of the A and B mode defects are generated.

An object of the present invention is to provide a method for manufacturing a highly reliable semiconductor device which eliminates the above problems and eliminates the A mode and B mode defects of the gate oxide film breakdown voltage described above.

[0021]

According to the present invention, there is provided a method for manufacturing a semiconductor device, comprising the steps of: (a) forming a gate insulating film on a substrate; A step of charging the substrate with water to eliminate defects in the gate insulating film; and a step of eliminating defects in the gate insulating film.
And a step of subjecting the surface of the gate insulating film to static elimination with a mixed solution of pure water and CO ₂ .

[2] In the method of manufacturing a semiconductor element,
Forming a gate insulating film on a board;
The surface of the film is charged with pure water and defects in the gate insulating film are detected.
Eliminating the defect of the gate insulating film.
Isopropyl alcohol
Removing the surface of the gate insulating film.
It was made.

[3] In the method of manufacturing a semiconductor element,
Forming a gate insulating film on a plate, the gate insulating
The surface of the film is charged with pure water and defects in the gate insulating film are detected.
Eliminating the defect of the gate insulating film.
Subsequent to the step of heat treatment, heat treatment
And a step of subjecting the surface to static elimination.
You.

[4] In the method for manufacturing a semiconductor device according to the above [1] , [2] or [3], the step of eliminating defects in the gate insulating film and the step of removing the surface of the gate insulating film are performed. They are performed by the same device.

[0025]

According to the present invention, as described above, MISFE
In the method of manufacturing T, in the step after the growth of the gate insulating film, the surface of the gate insulating film is charged to a predetermined potential, and then the charge removing process is immediately performed. After that, a gate electrode is formed.

Therefore, the particles mechanically attached to the gate insulating film and the particles attached by the electrostatic force are completely removed, and the electric breakdown voltage of the gate insulating film is improved.

As a method of removing the static electricity, a method of reducing the resistance of pure water by CO ₂ and rinsing the same is used, and isopropyl alcohol (hereinafter referred to as IPA) is used.
In this method, the withstand voltage of the gate insulating film is improved by selecting or combining a method of rinsing and removing static electricity and a method of removing static electricity by high temperature baking.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a MISFET showing an embodiment of the present invention.
5 is a manufacturing process flowchart of FIG.

(1) First, a process prior to a gate oxide film (gate insulating film) forming process such as an active process is performed to form a gate oxide film SiO ₂ for the purpose of improving withstand voltage, for example, 20
It is formed with a thickness of nm (Step S1).

(2) Next, withstand voltage improvement processing is performed (step S2). This is because the surface of the oxide film is charged by friction between the pure water and the gate oxide film, and when the electric field reaches an electric field exceeding the withstand voltage of the weak spot in the oxide film, a breakdown occurs. Is used to restore the image.

(3) Next, following the process for improving the withstand voltage, the static elimination process is immediately performed (step S3). This static elimination treatment includes static elimination with pure water containing CO ₂ ,
Examples include static elimination by PA and static elimination by high-temperature baking.

(4) Thereafter, a polycrystalline silicon film serving as a gate electrode, which is a general process, is grown (step S).
4).

(5) Next, POCl ₃ diffusion is performed on the polycrystalline silicon film serving as a gate electrode (step S5).

FIG. 2 is a configuration diagram of an apparatus for charging a gate oxide film and eliminating weak spots by self-healing according to an embodiment of the present invention.

First, the semiconductor wafer 1 which has completed the gate oxidation step is vacuum-sucked by a spin chuck 2 having conductivity, and is rotated by a rotating shaft 3.
The surface of the semiconductor wafer 1 is rinsed with pure water discharged from a pure water nozzle 4. At this time, the surface of the gate oxide film is charged with static electricity due to friction with pure water. As described above, this charging causes breakdown at the weak spot portion, and the weak spot disappears. This charging and breakdown development are repeated to sufficiently eliminate weak spots and improve the quality of the gate oxide film.

Thereafter, the semiconductor wafer 1 is dried by a spin drive, and the process proceeds to the next process of growing a polycrystalline Si film. If the surface of the oxide film is still charged, particles are generated by electrostatic attraction. Adheres, contaminates the gate oxide film by the heat treatment during the growth of the polycrystalline Si film, and causes a breakdown voltage failure. For this reason, after the weak spot extinction process, it is desirable to quickly remove the charge.

First, as a first static elimination method, rinsing is performed with pure water containing CO ₂ .

FIG. 3 is a diagram schematically showing an apparatus for implementing the first static elimination method of the present invention.

As shown in the figure, the static elimination process is performed at the same stage following the process of improving the gate oxide film breakdown voltage using pure water.

That is, first, in order to perform a charging process for eliminating weak spots, the valves V1 and V2 of the pure water line are opened to rinse pure water on the surface of the semiconductor wafer 1 and to rotate the semiconductor by the rotating shaft 3. The wafer 1 is rotated. As a processing condition at this time, processing is performed at a semiconductor wafer rotation speed of 6000 rpm for 40 seconds.

Thereafter, the valves V1 and V2 are closed, the valves V3 and V4 are opened, and the CO ₂ valve V5 is opened.
Is also opened, CO ₂ is mixed into the pure water by the mixer 5 to increase the ion concentration of the pure water to produce pure water having a specific resistance of 1 MΩcm or less, and the CO ₂ pure water nozzle 6 Rinse. Here, 2 is a spin chuck, and 4 is a pure water nozzle.

FIG. 4 is a diagram showing the charging voltage of the oxide film at a semiconductor wafer rotation speed of 6000 rpm by rinsing with pure water of 18 MΩcm and 1 MΩcm. The horizontal axis represents the processing time (second), and the vertical axis represents the charging voltage (V). ing.

As shown in this figure, what was charged by rinsing with pure water was converted into pure water by rinsing with CO ₂ .
It can be seen that the charge has been removed.

As a second static elimination method, rinsing is performed with isopropyl alcohol.

FIG. 5 is a diagram schematically showing an apparatus for implementing the second static elimination method of the present invention.

As shown in this figure, after the gate oxide film withstand voltage treatment with pure water, the valves V1 and V2 of the pure water line are closed, and the valve V6 of the IPA line is opened to supply IPA to the surface of the semiconductor wafer 1. , To be rinsed. The static elimination effect of IPA is used for static elimination of a semiconductor wafer as a known method, and is also an effective method in this method. Here, 1 is a semiconductor wafer, 2 is a spin chuck, 3 is a rotating shaft, 4 is a pure water nozzle, and 7 is IPA.
Nozzle.

A third static elimination method is static elimination by high-temperature baking.

FIG. 6 is a diagram showing a change in the amount of charge when the semiconductor wafer is dried by spin drying and baked in the air after the gate oxide film withstand voltage improvement treatment with pure water, using the baking temperature as a parameter. The horizontal axis represents the baking time (second), and the vertical axis represents the charging time (V).

The discharge voltage due to baking largely depends on temperature, and is substantially stable at a certain value. At 300 ° C., in about 60 seconds, the charge was rapidly removed from the charging voltage of −24 V to −4 V, and it can be seen that the electrostatic attraction force was suppressed at 300 ° C. or more.

FIG. 7 shows a rinsing treatment with pure water at 6000 rpm for 40 seconds, supersaturation at −24 V to eliminate weak spots on the oxide film, and immediately thereafter at 350 ° C.
FIG. 5 is a diagram showing a breakdown voltage distribution of a semiconductor wafer which has been subjected to a baking process for 60 seconds in FIG. 5, where the horizontal axis represents the breakdown voltage (V) and the vertical axis represents the failure rate (%).

As shown in this figure, it can be seen that the low voltage withstand mode of the A mode and the B mode has disappeared and the mode has shifted to the C mode.

FIG. 8 is a diagram showing a situation of studying the improvement of the withstand voltage by the static elimination method of the present invention.

As shown in FIG. 8A, the oxide film 12 on the silicon substrate 11 has a defect of the silicon substrate 11 in the same manner as the improvement by the charging method disclosed in Japanese Patent Application No. Hei. And weak spots 13 generated during the growth of the oxide film. When such an oxide film 12 is rubbed with pure water, as shown in FIG.
Charges 14 are charged on the surface of oxide film 12.

When the electric field strength of the electric charge 14 becomes higher than the withstand voltage of the weak spot 13, breakdown occurs in the oxide film portion 12 'including the weak spot 13, a current flows, and Joule heat is generated. When the Joule heat approaches the melting temperature of the oxide film 12, a flow phenomenon occurs, and a stable SiO bond is obtained.

The charge charging due to the friction, the breakdown at the 13 weak spots, the generation of Joule heat, and the phenomenon of stable SiO bonding due to the flow occur intermittently, and as shown in FIG. The 12 weak spots 13 disappear, and the withstand voltage of the oxide film 12 improves. That is, the weak spot 13 in the oxide film is
It breaks down due to the high electric field due to charging and disappears due to self-healing.

The disappearance of the weak spot 13 is approximately 2
It is completed during the supersaturated charging process for 0 to 40 seconds.

Thereafter, the charged electric charge is unnecessary, and conversely, it is electrostatically adsorbed to the floating particles during the dwell time until the next process in the charged state, and contaminates the gate oxide film. For this reason, it is desirable that static electricity be removed immediately after the weak spot disappearance processing.

In this embodiment, as shown in FIG.
After the weak spot extinction treatment, the charge can be quickly eliminated by mixing CO ₂ and rinsing with pure water having a high ion concentration. After the same process, the charge is removed by IPA. Static electricity is removed by baking at 300 ° C. or higher. By these individual charge eliminating methods or a method by a combination thereof, electric charges are released, the electrostatic attraction force is lost, and the adhesion of particles can be prevented. Therefore, polycrystalline Si
Particle adhesion can be reduced even during the standing time until film growth.

This eliminates contamination of the oxide film during the heat treatment of the polycrystalline Si, prevents a decrease in breakdown voltage, and maintains excellent oxidation breakdown voltage characteristics.

It should be noted that the present invention is not limited to the above embodiment, and various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

[0062]

As described above, according to the present invention, the surface of the gate insulating film of the MISFET is charged,
Immediately after the step of eliminating the weak spots of the oxide film by self-healing, the charge on the oxide film surface is rinsed with pure water containing CO ₂ or IP.
By removing the charge by rinsing with A and spin-drying, or by performing high-temperature baking immediately after spin-drying, the electric charge can be completely discharged, and the adhesion of particles due to electrostatic adsorption can be eliminated.

Therefore, at the time of heat treatment of polycrystalline Si, contamination of the oxide film caused by the adhesion of particles is eliminated, good breakdown voltage distribution characteristics can be obtained, and reliability can be improved.

[Brief description of the drawings]

FIG. 1 is a flow chart of a MISFET manufacturing process showing an embodiment of the present invention.

FIG. 2 is a configuration diagram of an apparatus for charging a gate oxide film and eliminating weak spots by self-healing according to an embodiment of the present invention.

FIG. 3 is a diagram schematically showing an apparatus for implementing a first static elimination method according to an embodiment of the present invention.

FIG. 4 shows 18 MΩcm and 1 MΩc showing an embodiment of the present invention.
semiconductor wafer rotation speed 6000 rpm by pure water rinsing
FIG. 6 is a diagram showing a charging voltage of an oxide film according to m.

FIG. 5 is a diagram schematically showing an apparatus for performing a second static elimination method according to the embodiment of the present invention.

FIG. 6 shows a change in the amount of charge when a semiconductor wafer is dried by spin dry and baked in the air after a process of improving the breakdown voltage of a gate oxide film with pure water as a third charge removing method showing an embodiment of the present invention. FIG.

FIG. 7 is a diagram showing a breakdown voltage distribution of a semiconductor wafer which has been subjected to a baking process by a third charge removing method according to the embodiment of the present invention.

FIG. 8 is a diagram showing a study state of improvement in withstand voltage by a static elimination method according to an embodiment of the present invention.

FIG. 9 is a cross-sectional view of a conventional general N-type MOS transistor.

FIG. 10 is a diagram showing the configuration of a conventional device for examining the electrical breakdown voltage characteristics of the gate oxide film of a transistor.

FIG. 11 shows a gate oxide film (film thickness 2) of a conventional transistor.
FIG. 3 is a diagram showing a breakdown voltage distribution of 0 nm).

FIG. 12 is a diagram showing a breakdown voltage distribution of a gate oxide film of a transistor when the conventional method is improved.

FIG. 13 is a diagram showing a problem of a gate of a transistor when the conventional method is improved.

[Explanation of symbols]

1 a gate oxide process semiconductor wafer 2 spin chuck 3 rotary shaft completing 4 pure water nozzle 5 mixer 6 CO ₂ water nozzle 7 IPA nozzle 11 silicon substrate 12 oxide film 12 'Week oxide film 13 weak spots 14 comprising spot charge

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-92472 (JP, A) Proceedings of the 53rd Autumn Meeting of the Japan Society of Applied Physics, 1992 (Heisei Era 4), p. Proceedings of the 43rd Symposium on Semiconductor and Integrated Circuit Technologies (Heisei 4-12-3), p. 102-107 (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/78 H01L 21/336 H01L 21/304 H01L 21/316

Claims (4)

(57) [Claims] 1. A method of manufacturing a semiconductor device, comprising: a step of forming a gate insulating film on a substrate; a step of charging the surface of the gate insulating film with pure water to eliminate defects in the gate insulating film; Following the process of eliminating defects in the insulating film ,
Removing the surface of the gate insulating film with a mixed solution of pure water and CO ₂ . 2. A method for manufacturing a semiconductor device, comprising: Forming a gate insulating film on the substrate; The surface of the gate insulating film is charged with pure water,
Removing the defects in the insulating film; Following the step of eliminating defects in the gate insulating film,
The surface of the gate insulating film is treated with isopropyl alcohol.
And a step of performing a static elimination process.
Child manufacturing method. 3. A method for manufacturing a semiconductor device, comprising: Forming a gate insulating film on the substrate; The surface of the gate insulating film is charged with pure water,
Removing the defects in the insulating film; Following the step of eliminating defects in the gate insulating film,
A step of removing the surface of the gate insulating film by heat treatment
A method for manufacturing a semiconductor device, comprising: 4. The production of a semiconductor device according to claim 1, 2 or 3, wherein the performing by the same apparatus and process for charge elimination of a step to eliminate the defect of the gate insulating film of the gate insulating film surface Method.