JP3192366B2 - Light receiving element and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light receiving element used for, for example, an optical coupling device, and more particularly to a light receiving element having a Darlington transistor configuration and a method of manufacturing the same.

[0002]

2. Description of the Related Art In general, the breakdown voltage between the collector and the emitter of a transistor decreases as _hFE increases, as shown in equation (1).

[0003]

(Equation 1)

Here, BV _CE0 : breakdown voltage between collector and emitter, BV _CB0 : breakdown voltage between collector and base, h
_FE : DC current amplification factor, n ≒ 3-6 This is because the dark current generated at the collector-base junction is h _FE
It is amplified and causes the avalanche breakdown process. Therefore, in order to obtain a predetermined collector-emitter breakdown voltage, there is a limit to the output should be kept to a certain size of h _FE.

To increase the output, a Darlington transistor is generally used. One way to obtain a higher output and a higher breakdown voltage is to incorporate a resistor between the base and the emitter as shown in FIG. Darlington transistors are used. In FIG. 8, NPN
A Darlington connection is made between an NPN type output stage transistor 101 and a NPN type output stage transistor 101. The resistors 102 and 1 are connected between the base and the emitter of the first-stage transistors 100 and 101, respectively.
03 is inserted. This configuration is generally used for power transistors and the like.

[0006] configuration of Figure 8, resistor dark current 102,
By flowing between the base and the emitter via 103,
Dark current is prevented from being h _FE amplified, is obtained so as to prevent a decrease in the collector-emitter breakdown voltage due to an increase in h _FE.

[0007]

When the above-described Darlington transistor configuration is applied to a light receiving element, the input base current is a photocurrent generated by a built-in photodiode. In consideration of the sensitivity of the photodiode serving as a part, unless the first-stage transistor is driven by at least a base current of several μA, its use is limited to a very narrow range.

Therefore, when the light receiving element is used under the condition that a base current of, for example, several μA or more can be generated, the ON-voltage between the base and the emitter of the first-stage transistor 100 can be obtained with the configuration of FIG. Is about 0.5 V, the resistance 102 between the base and the emitter in the first-stage transistor 100 needs to have a resistance value of about 1 MΩ or more in consideration of design margin. The resistance 103 between the base and the emitter of the transistor 101 in the output stage may be, for example, several tens of KΩ because the photocurrent is amplified by _hFE times in the first stage transistor 100.

By the way, it is very difficult to accurately incorporate a high resistance 102 such as about 1 MΩ required for the first-stage transistor 100 into one chip by a normal phototransistor process (very large area is required). You need it). Even if we dare to provide this resistor, we have to attach this resistor externally and we cannot make it into one chip.

Therefore, an object of the present invention is to provide a light-receiving element, particularly a structure in which a Darlington transistor is applied to a light-receiving element, to have a high output, to set a high collector-emitter breakdown voltage, to obtain a high breakdown voltage, and to obtain a high breakdown voltage. An object of the present invention is to realize a light-receiving element that can be formed into a single chip in which a resistance value inserted between a base and an emitter can be suppressed to be low and can be used as a built-in resistor.

[0011]

In order to achieve the above object, a first aspect of the present invention is to provide a photoelectric conversion unit and a Darlington-connected first stage and an output stage for amplifying a photocurrent obtained by the photoelectric conversion unit. A transistor and the output stage transistor
Current-suppressing resistor inserted between the base and emitter of the star
If, in the light-receiving element having, wherein said formed by large comb the amplification factor of the output stage transistor than the amplification factor of the first stage transistor of the Darlington transistor.

According to a second aspect of the present invention, in the light-receiving element according to the first aspect, the difference in the amplification factor of each transistor is set by the difference in the dose of impurity implantation into the base region of each transistor. It is characterized by becoming.

[0013] According to a third aspect of the invention, a method for manufacturing a photodiode according to the present invention, in the manufacturing method of the light-receiving element according to any Re without gall claim 1 or 2, formed on a semiconductor substrate A first step of ion-implanting impurities into the base regions of both the first-stage and output-stage transistors using an oxide film as a mask, and then covering the base region of the output-stage transistor with a photoresist; And a second step of selectively implanting ions into the region.

According to a fourth aspect of the present invention, the dose of the impurity implanted in the first step is a low dose, and the dose of the impurity implanted in the second step is a high dose. And

Hereinafter, the operation according to each claim will be described.

According to the first aspect of the present invention, since the dark current suppressing resistor is built only between the base and the emitter of the output stage transistor, the collector-emitter breakdown voltage as the light receiving element is increased by the amplification factor h of the first stage transistor. Determined by _FE . Therefore, by controlling the _hFE of the first-stage transistor, a predetermined collector-emitter breakdown voltage can be obtained. Here, since it is set to be smaller than the h _FE of the output stage transistor h _FE of the first-stage transistor, the collector and the
The breakdown voltage between the emitters can be increased (high breakdown voltage can be achieved).

[0017] On the other hand, since the h _FE of the output stage transistor 2, which does not affect the collector-emitter breakdown voltage is taken largely on the reverse, h as a Darlington transistor
_FE can be increased (high output can be achieved). That is, a light-receiving chip with high output and high withstand voltage can be realized.

By controlling the dose of each transistor to the base region, a desired h _{FE can be obtained.}
Can be obtained with high accuracy.

According to the third aspect, the light receiving element according to the first or second aspect can be obtained without making a significant change from the conventional light receiving element manufacturing process.

According to claim 4, even if the ratio of the amplification factor of the output stage transistor / the amplification factor of the first stage transistor is large,
The configuration can be easily realized.

[0021]

Features of the embodiment of the present invention includes a light receiving element, especially in the structure for applying the Darlington transistor to the light receiving element, it has a high output and reduce the h _FE of the first stage transistor, h _FE of the transistor of the output stage In addition, by incorporating a resistor for suppressing dark current only in the output transistor, the breakdown voltage between the collector and the emitter can be set high, a high breakdown voltage can be obtained, and the resistance value of the built-in resistor can be suppressed low. That is, a light receiving element that can be integrated into one chip is realized.

Hereinafter, description will be made with reference to the drawings. 1 and 2 are an equivalent circuit diagram and a schematic sectional view of a Darlington phototransistor chip according to an embodiment of the present invention, respectively.

As shown in FIGS. 1 and 2, the Darlington phototransistor chip (hereinafter simply referred to as a light receiving chip) of the present embodiment has an NPN type first stage transistor 1.
Similarly, the NPN type output stage transistor 2 is Darlington connected. That is, the collector 11 of the first-stage transistor 1 and the collector 21 of the output-stage transistor 2 are commonly connected, and the emitter 12 of the first-stage transistor 1 is connected to the base 22 of the output-stage transistor 2.
The photodiode 3 is connected between the collector 11 and the base 13 of the first-stage transistor 1, and the diffused resistor 4 is connected between the base 22 and the emitter 23 of the output-stage transistor 2.

In FIG. 1, 5 is a collector electrode, 6 is an emitter electrode of the output stage transistor 2, and 3 in FIG.
0 is a semiconductor substrate, 31 is an oxide film, and 34 is a channel stopper layer.

Here, the input base current of the output stage transistor 2 is increased to about several hundred μA by the amplification of the first stage transistor 1. Therefore, the resistance value of the diffusion resistor 4 may be about 10 KΩ to several tens KΩ. With such a resistance value, it can be formed with high precision by diffusion resistance by a normal phototransistor process.

Although not clear in the equivalent circuit of FIG. 1, the base (layer) of the output stage transistor 2 is more than the base (layer) 13 of the first stage transistor 1 as described later.
22 it is a low concentration, therefore, towards the h _FE of the output stage transistor 2 than h _FE of the first stage transistor 1 is increased.

According to such a structure of this embodiment, since the diffusion resistor 4 for suppressing the dark current is built only between the base and the emitter of the output stage transistor 2, the collector-emitter breakdown voltage as the light receiving chip is provided. Is determined by _hFE of the first-stage transistor 1. Therefore, by controlling the _{hFE of the} first-stage transistor 1, a predetermined collector-emitter breakdown voltage can be obtained. Here, since the smaller the h _FE of the first stage transistor 1, as described above, it is possible to increase the collector-emitter breakdown voltage.

[0028] On the other hand, since h _FE of the output stage transistor 2, which does not affect the collector-emitter breakdown voltage is taking large, it can be increased the h _FE as a Darlington transistor. That is, a light-receiving chip with high output and high withstand voltage can be obtained.

Next, the manufacturing method of the embodiment shown in FIG. 2 will be described. 3A to 3E are manufacturing process diagrams of the present embodiment.

First, as shown in FIG. 3A, after an oxide film 31 is formed on the surface of the N-type substrate 30 by a thermal oxidation method or the like, the oxide film 31 is selectively removed.

Next, as shown in FIG. 3B, using this oxide film 31 as a mask, the base regions of the first and output stage transistors, the anode and cathode regions of the photodiode, and the diffusion resistance region at a relatively low dose. P-type impurities 32 such as boron are selectively ion-implanted.

Next, as shown in FIG. 3C, the base region and the diffusion resistance region of the output stage transistor are covered with a photoresist 33, and a relatively high dose of P such as boron is used.
A second ion implantation of the type impurity 32 is performed. In this second ion implantation, ions are selectively implanted into the base region of the first transistor and the anode (cathode) region of the photodiode.

Next, after the photoresist 33 is removed, the structure shown in FIG. 3D is obtained by performing thermal diffusion. Here, the impurity concentration of the base layer and the diffusion resistance layer (P portion) of the output stage transistor is changed to the base layer of the first stage transistor and the anode and cathode layers (Q
Part).

Next, by diffusing an N-type impurity such as phosphorus by thermal diffusion or the like, an emitter layer channel stopper layer 34 of the first and output stage transistors is simultaneously formed.
(E) structure is obtained. Finally, by providing the required electrodes, the structure shown in FIG. 2 is obtained.

In the above embodiment, the dose in the step shown in FIG. 3B is 7 × 10 ¹³ cm ⁻² , and the dose in the step shown in FIG. 3C is 2.3 × 10 ¹⁴ cm. ^-2 .

As described above, according to the manufacturing method of the present invention, the output dose of the impurity to the base region 13 of the first transistor 1 is made larger than that of the impurity to the base region 22 of the output transistor 2. It is set to be larger towards the h _FE of the transistor 4. Thus, with reference to FIG. 4 to be varied the h _FE of the transistor will be described by varying the dose.

FIG. 4 is a characteristic diagram obtained as a result of an experiment conducted by the inventor. In the light-receiving chip having the same structure as that of FIG. 2, the ion implantation dose to the base region 13 of the first-stage transistor 1 is made constant. Base region 2 of output stage transistor 2
The ratio of the two doses (A: dose to the base region of the first-stage transistor / dose amount to the base region of the output-stage transistor) when the dose of the ion implantation into 2 is changed;
The ratio of h _FE of the transistors: shows the relationship between the (B h _FE of h _FE / first stage transistor of the output stage transistor).

As can be seen from FIG. 4, the ratio of the output stage / first stage transistor _hFE can be changed by changing the ratio of the ion implantation dose to each base region of the first stage / output stage. I understand.

That is, in the above manufacturing method, FIG.
Dose during the second ion implantation (c), the words, it is possible to easily control the h _FE of the receiving chip by controlling an ion implantation dose of the first stage transistor 1.

Further, the inventor has proposed that the output stage / first stage h
It has been confirmed that the collector-emitter breakdown voltage increases as the _FE ratio increases. This will be described with reference to FIG. 5 4 Similarly, a result inventors have confirmed experimentally, the output stage / first stage h _{FE (B} in FIG. 4) as a parameter, h _FE as Darlington transistors
3 shows the relationship between the breakdown voltage between the collector and the emitter of the first-stage transistor 1. As is clear from FIG. 5, the output stage transistor 2 is
Enough to take the h _FE large, the collector-emitter breakdown voltage is higher than the h _FE of the same Darlington transistor.

That is, by controlling the _hFE of the first-stage transistor to a predetermined value and increasing the _{hFE of the} output-stage transistor, it is possible to increase the breakdown voltage of the light receiving chip without impairing the value of the collector-emitter breakdown voltage. . Moreover, the structure of this embodiment adopts a Darlington transistor configuration, thereby high output because it takes a large h _FE of the output stage transistors.

By the way, in the circuit configuration of FIG. 1, by obtaining the h _FE of the Darlington transistor, the following formula. In order to make the explanation easy to understand, FIG.
(The light receiving element is omitted).

[0043]

(Equation 2)

[0044] Here, each of the I _C and I _B, the collector and base currents when h _FE measurement, h _FE of h _FE1 first stage transistor, h _FE2 is a resistor between the h _FE (base-emitter of the output stage transistor H _FE without built-in), R _BE
Is the resistance of the internal resistor for suppressing a dark current, V _BE2 is the base-emitter voltage of the output stage transistors at the time of h _FE measurements (about 0.7 V).

Therefore, for the output as the light receiving element, a set value that improves the output as the Darlington transistor based on equation (2) is obtained, and for the breakdown voltage, the output stage / first stage is determined as described above. By setting h _FE high, a light-receiving element with high withstand voltage and high output can be realized.

[0046] Specifically, in the above embodiment was 5-6 the value of the output stage / first stage h _FE. Here, the size of the resistor R _BE for suppressing dark current was about 25 KΩ. As a result, the withstand voltage can be increased from the rated 340 V of the conventional structure to about 380 V, and the output can be increased about two to three times.

In the embodiments described with reference to FIGS. 1 to 3, the Darlington transistor is of the NPN type, but it goes without saying that the Darlington transistor can be applied to a PNP type transistor. The circuit diagram shown in FIG. It is the same as FIG. 1 except that the transistor type is different and the connection direction of the photodiode is reversed.

[0048]

As described above, according to the present invention, since the dark current suppressing resistor is built only between the base and the emitter of the output stage transistor, the collector-emitter breakdown voltage as the light receiving element is reduced by the first stage transistor. Amplification factor h
Determined by _FE . Therefore, by controlling the _hFE of the first-stage transistor, a predetermined collector-emitter breakdown voltage can be obtained. Here, (attained a high breakdown voltage) so is set to be smaller than the output stage transistor to h _FE of the first stage transistor, it is possible to increase the collector-emitter breakdown voltage.

[0049] On the other hand, since h _FE of the output stage transistor 2, which does not affect the collector-emitter breakdown voltage is taken largely on the reverse, h as a Darlington transistor
_FE can be increased (high output can be achieved). That is, a light-receiving chip with high output and high withstand voltage can be realized.

Further, since the dark current suppressing resistor is provided in the output stage transistor, the photocurrent is amplified by the first stage transistor, so that a relatively small resistance value is sufficient. Therefore, it can be built in the light receiving element using a normal process, and it is easy to realize one chip.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of a light receiving element according to an embodiment of the present invention.

FIG. 2 is a specific chip sectional view of the light receiving element of FIG.

3 (a) to 3 (e) are manufacturing process diagrams of a light receiving element according to one embodiment of the present invention.

Is a characteristic diagram showing the relation between the dose and the h _FE in the structure of FIG. 4 FIG.

5 is a characteristic diagram showing the relationship between the collector-emitter breakdown voltage of the h _FE and the first stage transistor of the Darlington transistor in the structure of FIG.

FIG. 6 is a circuit diagram for explaining an output of the embodiment of FIG. 1;

FIG. 7 is an equivalent circuit diagram of a light receiving element according to another embodiment of the present invention.

FIG. 8 is a circuit diagram of a conventional general Darlington transistor.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 first-stage transistor 2 first-stage transistor 3 photoelectric conversion unit 4 dark current suppressing resistor 13 first-stage transistor base region 22 output-stage transistor

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 31/00-31/119 H04B 10/00-10/30

Claims (4)

(57) [Claims] 1. A photoelectric conversion unit, a Darlington-connected first-stage and an output-stage transistor for amplifying a photocurrent obtained by the photoelectric conversion unit, and a base of the output- stage transistor.
A resistor for current suppression interposed between Suemitta, the light-receiving element having a light receiving element, characterized in that said formed by large comb the amplification factor of the output stage transistor than the amplification factor of the first stage transistor of the Darlington transistor. 2. The light-receiving element according to claim 1, wherein the difference in the amplification factor of each transistor is set by the difference in the dose of impurity implantation into the base region of each transistor. element. 3. A method of manufacturing a light receiving device according to any Re without gall claim 1 or 2, the oxide film formed on a semiconductor substrate as a mask, impurity in the base region of the two transistors of the first stage and the output stage And a second step of covering the base region of the output stage transistor with a photoresist and selectively implanting impurities into the base region of the first stage transistor. Of manufacturing a light receiving element. 4. The method according to claim 3, wherein the dose of the impurity implanted in the first step is a low dose, and the dose of the impurity implanted in the second step is a high dose. Method for manufacturing a light receiving element.