JP3191782B2 - Integrated circuit failure inspection apparatus and method, and recording medium recording control program - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure inspection apparatus for an integrated circuit, and more particularly, to an apparatus for inspecting an integrated circuit for failure by detecting an abnormality in a power supply current of the integrated circuit.

[0002]

2. Description of the Related Art Integrated circuit testing is performed, for example, in the literature "Inte
grated Circuit Quality and Reliability (Eugene R. H
natek, 1995) ”on pages 151 to 156.
Screening has been done to reduce the proportion of product defects.

[0003] There are roughly three types of tests. Of these, the DC test is for checking the basic characteristics of an integrated circuit product, and includes a threshold voltage, a leak current, a maximum / minimum value of an input / output voltage, Check the value of input / output current. Function test (functional test)
Is performed to check the function expected of the integrated circuit product, that is, the input / output logic state. The AC test is performed to check the propagation delay time of a signal, the rise and fall times of a pulse, the operating frequency capability, and the like.

[0004] In recent years, due to the high integration, large scale, and high functionality of integrated circuits, the time required for testing has been lengthened, and an increase in test cost has become a problem.

In such a situation, an IDDQ test (IDD quiescent tess) for determining a pass / fail by measuring a quiescent power supply current (hereinafter referred to as "IDDQ") of the integrated circuit.
t) is drawing attention.

[0006] The IDDQ test is described in, for example,
As described on pages 56 to 157, CMOS
It is used for detecting failures such as oxide film short circuit, polysilicon bridge failure, transistor failure, and PN junction leak in an integrated circuit.

[0007]

However, the IDDQ test has a problem in that it is not possible to perform a very high-speed observation because it is necessary to measure a quiescent power supply current. For example, the function test is performed at a test frequency of several tens to several hundreds of megahertz, while the IDDQ test is performed at a maximum of several kilohertz to several tens of kilohertz, and the inspection speed is slow.

A power supply current flowing through an integrated circuit, particularly a CMOS integrated circuit, includes a switching current of a transistor flowing when a signal called a test vector is applied to the integrated circuit and a leakage of the transistor flowing when the operation of the transistor is stopped. Consist of current. Most of the quiescent power supply current of the integrated circuit has this leakage current.
The Q test utilizes the fact that the leakage current is very small,
A static power supply current, which hardly flows normally, is observed, and an abnormally large static power supply current is detected to detect a physical failure or the like.

In order to accurately measure the quiescent power supply current,
Due to the influence of parasitic components of an integrated circuit which is a device under test (also referred to as a “DUT”), for example, a bypass capacitor or a parasitic capacitance inserted between a power supply ground and a time constant of a power supply unit, After applying the test vector to the test device, it is necessary to wait for a certain time (for example, 0.1 to 10 milliseconds), which makes it difficult to speed up the IDDQ test.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a device for inspecting an integrated circuit by observing a power supply current of the integrated circuit, thereby increasing the speed of the test. An object of the present invention is to provide a failure inspection device that improves reliability.

[0011]

According to a first aspect of the present invention, there is provided a method for testing a failure of an integrated circuit, comprising: applying a unit test signal having a predetermined period T comprising a plurality of test vectors to a device under test; The power supply current of the device under test during signal application is sampled and Fourier-transformed to obtain a frequency spectrum with 1 / T as a fundamental frequency, and the magnitude and phase information of the frequency spectrum or the real part of the frequency spectrum For the value of the imaginary part, the quality of the device under test is calculated based on the degree of being within the standard value with respect to the reference value, and in the case of a failure, the degree is calculated, and the quality of the device under test is determined.

An integrated circuit failure inspection apparatus according to the present invention comprises:
A test signal for generating a test signal to be applied to the device under test in an integrated circuit failure inspection apparatus for measuring a power supply current of an integrated circuit which is a device under test and performing a defect inspection of the integrated circuit based on a frequency spectrum of the power supply current Generating means, a power supply observing means for supplying power to the device under test and observing the value of the supplied power current, and a frequency spectrum obtained by Fourier transforming the observation information of the power current obtained by the power supply observing means. And the strength information of the frequency spectrum obtained by the Fourier transform means are input, and the strength information is compared with a predetermined reference value to determine the degree of failure of the device under test. Strength determining means and phase information of the frequency spectrum obtained by the Fourier transform means, and inputting the phase information to a predetermined reference A phase determination unit that determines a degree of failure of the device under test by comparing the value with a value, and receives the determination result obtained by the intensity determination unit and the phase determination unit as an input and the device under test according to a predetermined determination criterion. And a main control means for controlling each of the above means.

[Outline of the Invention] An outline of the present invention will be described. According to the present invention, the failure of the integrated circuit is determined by observing the frequency spectrum of the power supply current. More specifically,
The test signal generating means (1 in FIG. 1) is connected to the main control means (4 in FIG. 1), generates a test signal in accordance with an instruction from the main control means (4 in FIG. 1), and connects to the connected device under test (FIG. 1). 1
5). The power supply observation means (2 in FIG. 1)
The main control means (4 in FIG. 1) is connected to the main control means (FIG. 1).
The power supply voltage determined by the instruction in 4) is generated and supplied to the device under test (5 in FIG. 1) connected to the power supply observation means (2 in FIG. 1). Device under test (5 in FIG. 1)
The magnitude of the power supply current supplied to the power supply is observed by the power supply observation means (2 in FIG. 1) and sent to the Fourier transform means (3 in FIG. 1) connected to the power supply observation means (2 in FIG. 1). . The Fourier transform means (3 in FIG. 1) is connected to the main control means (4 in FIG. 1), and information transmitted from the power supply observation means (2 in FIG. 1) according to an instruction from the main control means (4 in FIG. 1). Is Fourier-transformed and transmitted to the intensity determining means (6 in FIG. 1) and the phase determining means (7 in FIG. 1). The intensity determining means (6 in FIG. 1) and the phase determining means (7 in FIG. 1) are additionally connected to the main control means (4 in FIG. 1) and the Fourier transform means (3 in FIG. 1). In accordance with the instruction from 1-4), the pass / fail of the device under test (5 in FIG. 1) is determined based on the information sent from the Fourier transform means (3 in FIG. 1), and the judgment information is determined by the comprehensive judgment means (5). It is sent to 8) in FIG. The overall determination means (8 in FIG. 1) is connected to the intensity determination means (6 in FIG. 1) and the phase determination means (7 in FIG. 1), respectively, and is also connected to the main control means (4 in FIG. 1). . Comprehensive judgment means (Fig. 1
8) is based on the determination information transmitted from the intensity determining means (6 in FIG. 1) and the phase determining means (7 in FIG. 1) according to the instruction of the main control means (4 in FIG. 1), and finally the device under test ( FIG.
5) Pass / fail judgment is made and the result is output.

The principle and operation of the present invention will be described with reference to FIG. The test signal generated by the test signal generation means (1 in FIG. 1) is applied to the device under test (5 in FIG. 1). It is assumed that a unit test signal whose application time is T is repeatedly applied to the test signal.

The operation of the device under test (5 in FIG. 1) requires the supply of power. The power is generated and supplied by the power supply observing means (2 in FIG. 1). FIG. 27 shows the concept of the power supply current flowing at that time. The unit test signal is composed of many test vectors, and the device under test (5 in FIG. 1) operates by applying each test vector. Here, when the same test signal is applied to the non-defective device and the non-defective device, the power supply current flowing therethrough differs between the non-defective device and the non-defective device as shown in FIG.

Here, it is assumed that a unit test signal is repeatedly applied as a test signal. Since the application time of the unit test signal is T, the same unit test signal is applied to the test signal at a period of T. Since the same unit test signal is applied, the same power supply current flows in the device under test (5 in FIG. 1) in cycle T.

This means that the frequency spectrum of the power supply current has a fundamental frequency of 1 / T and is composed of its harmonics.

By the way, since the power supply current flowing when the same unit test signal is applied is different between the non-defective product and the non-defective product, as shown in FIG. A), the values of the frequency spectra of the power supply currents are different from each other. Since the value of the frequency spectrum is composed of an intensity component and a phase component, it is possible to detect a difference in the power supply current by comparing these components.

In order to observe the frequency spectrum, the value of the power supply current for one cycle of the test signal is sampled, and the Fourier transform is performed on the sampled data to obtain the intensity component and the phase component.

That is, power supply observation means (2 in FIG. 1)
Sample the value of the power supply current. The start and end of the sampling timing are instructed by instructions from the main control means (4 in FIG. 1), and the value of the power supply current for one cycle of the test signal is sampled.

The sampled data is subjected to Fourier transform by a Fourier transform means (3 in FIG. 1) and divided into an intensity component and a phase component. Each component is compared by using a spectrum value of a non-defective product prepared in advance by an intensity determination unit (6 in FIG. 1) and a phase determination unit (7 in FIG. 1) as a reference value. ), A non-defective / defective product of the device under test (5 in FIG. 1) is determined.

[0022]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

[First Embodiment] FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention. Referring to FIG. 1, a first embodiment of the present invention includes a test signal generating unit 1, a power supply observing unit 2, a Fourier transform unit 3, a main control unit 4, an intensity determining unit 6, a phase determining unit 7, and It is provided with a comprehensive judgment means 8.

The test signal generator 1 is connected to the main controller 4, generates a test signal in accordance with an instruction from the main controller 4, and applies the test signal to the connected device under test 5. The power supply observing means 2 is connected to the main control means 4,
The device under test 5 which generates a power supply (power supply voltage and current) determined by the instruction of
To supply.

The magnitude of the power supply current supplied to the device under test 5 is observed by the power supply observation means 2 and sent to the Fourier transform means 3 connected to the power supply observation means 2.

The Fourier transforming means 3 is connected to the main control means 4, and the power supply observing means 2 is instructed by the main control means 4.
(Time-series data of a sample of the power supply current) is Fourier-transformed by, for example, Fast Fourier Transform (FFT) to obtain a frequency spectrum, which is transmitted to the intensity determining means 6 and the phase determining means 7.

The intensity judging means 6 and the phase judging means 7 are both connected to the main control means 4 and the Fourier transforming means 3, and based on information sent from the Fourier transforming means 3 according to an instruction from the main control means 4. Then, the pass / fail judgment of the device under test 5 is made, and the judgment information is sent to the comprehensive judgment means 8.

The overall judging means 8 is connected to the intensity judging means 6 and the phase judging means 7 respectively, and is also connected to the main control means 4. Based on the determination information transmitted from the means 7, it is finally determined whether the device under test 5 is a non-defective product or a defective product, and a determination result is output.

Next, the test signal generating means 1 and the power supply observing means 2 will be described in more detail.

FIG. 2 is a block diagram showing a configuration of the test signal generating means 1 according to the first embodiment of the present invention. Referring to FIG. 2, the test signal generating means 1 includes a program storing means 101, a test pattern storing means 102,
It comprises a control means 103 and a signal generation means 104.

The control means 103 is connected to the main control means 4, and the signal generation means 104 is connected to the device under test 5. The signal generating means 104 is connected to a program storing means 101 and a test pattern storing means 102, respectively. The program storage unit 101 and the test pattern storage unit 102 are both connected to the control unit 103.

The control means 103 issues an instruction to the program storage means 101 based on the instruction from the main control means 4, and sends the program information to the signal generation means 104.

The control means 103 issues an instruction to the test pattern storage means 102 and sends out test pattern information to the signal generation means 104.

The signal generating means 104 generates a test signal having a predetermined test frequency and a predetermined signal waveform from the program information and the test pattern information in accordance with an instruction from the control means 103, and outputs the test signal through a driver (not shown). Is applied.

FIG. 3 is a block diagram showing the configuration of the power supply observing means 2 according to the first embodiment of the present invention.
Referring to FIG. 3, the power supply observation unit 2 includes a controlled voltage source 201, a current detection unit 202, and a voltage control unit 20.
3 is provided. Voltage control means 203 is connected to main control means 4 and receives an instruction. Controlled voltage source 2
01 is connected to the voltage control means 203.

The voltage control means 203 causes the controlled voltage source 201 to generate an appropriate voltage according to an instruction from the main control means 4. The generated voltage is supplied as the power supply voltage (VDD) of the device under test 5 via the current detecting means 202 connected to the controlled voltage source 201.

The current detection means 202 is connected to the main control means 4, observes the magnitude of the power supply current supplied to the device under test 5 according to the instruction of the main control means 4, and outputs the current information to the Fourier transform means 3. It is sent out as current information.

Next, the operation of the first embodiment of the present invention will be described.

FIG. 15 is a flowchart for explaining the operation of the first embodiment of the present invention.

In the test signal generating means 1, the main control means 4
, A test signal for determining whether the device under test 5 is good or bad is generated (step S in FIG. 15).
1). The test signal includes various test signal information stored in the program storage unit 101 shown in FIG. 2, for example, physical information of the test signal such as an amplitude value of each signal, a rise time, a fall time, and a test signal application speed. The signal is output from the signal generator 104 and applied to the device under test 5 based on information on logical operations such as 1 and 0 of the test signal stored in the test pattern storage 102.

The power supply observing means 2 generates a predetermined voltage and supplies it to the device under test 5 in order to supply power required for the operation of the device under test 5 in accordance with an instruction from the main control means 4 ( Step S2 in FIG. 15). The power supply current supplied at this time is supplied via current detection means 202. The magnitude of the supplied power supply current depends on the main control unit 4.
And sent to the Fourier transform means 3 as power supply current information (steps S3 and S4 in FIG. 15).

FIG. 4 is a diagram showing the relationship between the test signal generated by the test signal generation means 1 and the observation timing of the power supply current observed by the power supply observation means 2. The test signal 301 generated by the test signal generating means 1 is generated by repeating a series of unit test signals. The application time of the unit test signal to the device under test 5 is T, and the unit test signal is applied to the device under test 5 at a period T.

The sampling signal 302 represents a power supply current observation instruction sent from the main control unit 4 to the power supply observation unit 2. That is, when the unit test signal is applied to the device under test 5 by 0 or an integer number of times equal to or more than one, a current observation start signal is supplied from the main control unit 4 to the power supply observation unit 2. The supplied power supply observing means 2 starts observing the power supply current (step S3 in FIG. 15).

When the unit test signal is applied to the device under test 5, a current observation end signal is sent from the main control means 4 to the power supply observing means 2, and upon receipt of this signal, the power supply observing means 2 observes the power supply current. (Step S in FIG. 15)
4).

In FIG. 4, the sampling signal 30
Reference numeral 3 denotes another method for instructing current observation sent from the main control means 4 to the power supply observation means 2. That is, when the unit test signal is applied to the device under test 5 by zero or one or more integer times, a current observation start signal is sent from the main control unit 4 to the power supply observation unit 2, and the power supply current is monitored. Is started (step S3 in FIG. 15).

The unit test signal is output plural times.
When the voltage is applied, a current observation end signal is sent from the main control unit 4 to the power supply observation unit 2, and the observation of the power supply current ends (step S4 in FIG. 15).

As described above, the section from the current observation start signal to the current observation end signal is the section in which the power supply current is observed, and information on the power supply current during this period is sent to the Fourier transform means 3.

The Fourier transforming means 3 Fourier transforms the power supply current information observed by the power supply observing means 2 in accordance with an instruction from the main control means 4 (step S5 in FIG. 15).
When the current observation section is specified by the sampling signal 302, the current observation information during the application period T of the unit test signal is Fourier transformed.

The result of the Fourier transform is a DC component and spectral information at a frequency (n / T) that is an integral multiple of the frequency 1 / T. The spectrum information has intensity information and phase information. The intensity information is sent to the intensity judging means 6, and the phase information is sent to the phase judging means 7.

The strength judging means 6 judges the received strength information based on the reference information prepared in advance according to the instruction of the main control means 4, judges good / bad of the device under test 5, and 8 is supplied with the determination information (step S6 in FIG. 15). This determination information is not a clear one such as good / bad, but expresses the degree of good or bad by an analog amount (numerical value).

The phase determining means 7 determines the received phase information based on reference information prepared in advance according to an instruction from the main control means 4, and determines whether the device under test is good or bad.
It is sent to the comprehensive judgment means 8 (step S7 in FIG. 15).
The judgment information is not clear information such as good / bad, but expresses the degree of good or bad by an analog amount (numerical value).

The comprehensive judgment means 8 receives judgment information from the intensity judgment means 6 and the phase judgment means 7 according to the instruction of the main control means 4, and judges whether the device under test 5 is good or bad (step in FIG. 15). S8). Based on the judgment criteria given in advance, pass / fail of the device under test 5 is determined from the respective judgment information, and the result is output.

The main control means 4 may describe the control operation as a control program, and control the operation of each section by executing the control program by the computer of the main control means 4. In this case, for example, the control program is stored in a recording medium (not shown) such as a ROM or a floppy disk attached to the main control means 4 and loaded into the memory of the main control means 4 for execution.

Next, in order to describe the first embodiment of the present invention more specifically, first and second embodiments will be described below with reference to the drawings.

[First Embodiment] FIG. 5 is a block diagram showing a configuration of a first embodiment of the present invention. Referring to FIG.
In this embodiment, a logic tester 31 and a power supply unit 32
, A current sampling unit 33, a main controller 34, a Fourier transform unit 36, an intensity determination unit 37, a phase determination unit 38, and an overall determination unit 39, and tests the device under test 35.

The logic tester 31 is connected to the main controller 34 and generates a test signal according to a command from the main controller 34. The generated test signal is applied to the device under test 35 connected to the logic tester 31.

The power supply unit 32 is connected to the main controller 34 and generates a predetermined power supply voltage for the device under test in accordance with a command from the main controller 34. The generated power supply voltage is supplied as the power supply voltage of the device under test 35 via the current sampling unit 33.

The current sampling unit 32 is connected to the power supply unit 32, supplies the power supply voltage generated by the power supply unit 32 to the device under test 35 connected to the current sampling unit 33, and monitors the supplied power supply current. .

The observation method of the power supply current is as follows. The observation of the power supply current value is started by the observation start command from the main controller 34 connected to the current sampling unit 33, and the observation end command sent from the main controller 34 is received again. The sampling of the value of the power supply current ends.

The power supply current observed during the period from the reception of the observation start instruction to the reception of the observation end instruction is supplied to the Fourier transform unit 36 connected to the current sampling unit 33 as power supply current information.

The Fourier transform unit 36 is connected to the main controller 34, and performs Fourier transform on the power supply current information according to a Fourier transform process execution command sent from the main controller 34.

The result of the Fourier transform is separated into intensity information and phase information and sent to an intensity judgment unit 37 and a phase judgment unit 38, respectively.

The intensity judging unit 37 is connected to the Fourier transform unit 36 and the main controller 34, and in accordance with a command from the main controller 34, intensity information sent from the Fourier transform unit 36, predetermined reference information, and the like. Are compared with each other to determine whether the device under test 35 is good /
The degree of failure is determined, and the determination result is determined by the comprehensive determination unit 39.
To send to.

The phase judging unit 38 is connected to the Fourier transform unit 36 and the main controller 34, and converts the phase information sent from the Fourier transform unit 36 according to an instruction from the main controller 34 and predetermined reference information. Then, the degree of pass / fail of the device under test 35 is determined, and the determination result is sent to the overall determination unit 39.

The overall judgment unit 39 includes an intensity judgment unit 37, a phase judgment unit 38, and the main controller 3
4 based on the determination results sent from the intensity determination unit 37 and the phase determination unit 38 according to an instruction from the main controller 34, and determines whether the device under test is good or defective and outputs the result.

Next, the operation of the first embodiment of the present invention will be described. FIG. 19 is a flowchart for explaining the operation of the first embodiment of the present invention.

The logic tester 31 generates a test signal to be applied to the device under test 35 in accordance with an instruction from the main controller 34 (step S4 in FIG. 19).
1).

The generated test signal is transmitted to the device under test 35.
Is applied to In the power supply unit 32, the device under test 3
The power supply voltage for the operation of No. 5 is generated according to an instruction from the main controller 34 (step S4 in FIG. 19).
2).

The generated power supply voltage is supplied to the power supply of the device under test 35 via the current sampling unit 33. The magnitude of the supplied power supply current is observed by the current sampling unit 33 over an appropriate section according to an instruction from the main controller 34, and the power supply current information is sent to the Fourier transform unit 36 (step S4 in FIG. 19).
3 and step S44). First, sampling of the current value is started by an instruction from the main controller 34 (step S43 in FIG. 19), and after sampling of an appropriate section is performed, sampling of the current value is again performed by an instruction from the main controller 34. Stops (step S44 in FIG. 19).

The Fourier transform unit 36 performs a Fourier transform on the supplied power supply current information in accordance with an instruction from the main controller (step S45 in FIG. 19).

The result of the Fourier transform is nothing but a frequency spectrum value for the section where the power supply current is observed. The intensity component and the phase component are separated and sent to the intensity determination unit 37 and the phase determination unit 38, respectively.

The intensity determination unit 37 compares the intensity information sent from the Fourier transform unit 36 with a predetermined reference data in accordance with an instruction from the main controller 34, and determines whether the device under test 35 is a non-defective product or to what extent It is determined whether or not it is a non-defective product, and a determination result according to the degree of failure is sent to the overall determination unit 39 (step S46 in FIG. 19).

Similarly, the phase judging unit 38 compares the phase information sent from the Fourier transform unit 36 with predetermined reference data, and determines whether the device under test 35 is good or defective. And sends the result to the comprehensive judgment unit 39 (step S47 in FIG. 19).

The comprehensive determination unit 39 comprehensively determines the non-defective or defective product information of the device under test 35 determined from the strength information and the non-defective or defective product information of the device under test 35 determined from the phase information. Judgment of good / bad of the device under test 35 is performed according to the determined judgment criteria, and the result is output (step S4 in FIG. 19).
8).

Next, an example of a determination method performed by the intensity determination unit 37, the phase determination unit 38, and the overall determination unit 39 will be described.

FIG. 6 is a diagram for explaining an example of the determination method. Referring to FIG. 6, there are five items as intensity information and five items as phase information. Reference values are prepared in advance, and their standard ranges are shown. If the observed value falls within the standard range, the device under test 35 is a non-defective product. If the observed value does not fall within the standard range, the degree of failure is determined depending on how many devices do not fit.

Referring to FIG. 6, with respect to device A, from the intensity information, all the observation values of device A are:
It is within the reference value ± the specified range. That is, all five items fall within the standard range, and the degree of conformity is set to 5/5.

Regarding the strength information of the device B, some items (strengths 2, 3, and 4) deviate from the standard range, and the non-defective degree is 3/5. The device C has a non-defective degree of 3/5.

As a result, in the strength determination unit 37,
For the device A, the degree of conformity was 5/5, and the other 2
Regarding the two devices B and C, the conformity is determined to be 3/5.

Similarly, the phase determination unit 38 determines whether or not the observed value falls within the standard range, and outputs a determination result as the degree of conformity. In the example shown in FIG. 6, device A and device B are 5/5,
Device C is 1/5.

The overall judgment unit 39 judges whether the device under test 35 is good or bad based on the judgment results from the intensity judgment unit 37 and the phase judgment unit 38.

As an example of the judgment criterion, the judgment criterion of the comprehensive judgment A is such that one of the intensity judgment result or the phase judgment result is 1 and the other is 0.6 or more.
As shown in the comprehensive judgment A, the device A and the device B are judged as non-defective, and the device C is judged as defective.

On the other hand, as another example of the judgment criterion, a general judgment B
In the example shown in FIG. 6, only the device A is a non-defective product, and the device B and the device C
Is defective. These criteria are appropriately determined according to the reliability and cost required for the device under test 35.

[Embodiment 2] Next, a second embodiment of the present invention will be described. FIG. 23 is a block diagram showing a configuration of the second exemplary embodiment of the present invention. Referring to FIG. 23, the tester 43 includes a logic tester main unit 42, a power supply unit 32, a current sampling unit 33, a Fourier transform unit 36, an intensity determination unit 37,
A phase determination unit 38, a comprehensive determination unit 39, and a main controller 34 are provided.

Referring to FIG. 23, the present embodiment is provided with a logic tester main unit 42 instead of the logic tester 31 in the embodiment shown in FIG. 5, and other than that shown in FIG. This is the same as the previous embodiment. In this embodiment, the various functions of the embodiment shown in FIG. 5 are incorporated in one tester 43.

[Second Embodiment] Next, a second embodiment of the present invention will be described. FIG. 7 is a block diagram showing a configuration of the second exemplary embodiment according to the present invention. Referring to FIG. 2, a second embodiment of the present invention is different from the configuration of the first embodiment shown in FIG. 1 in that the intensity judgment means 6, the phase judgment means 7, and the comprehensive judgment means 8 are used instead. , Complex number determining means 9.

The complex number judging means 9 is the Fourier transforming means 3
And the main control means 4. Fourier transform means 3
The frequency spectrum information obtained by Fourier-transforming the power supply current information is judged by the complex number judging means 9 according to an instruction from the main control means 4, and the pass / fail judgment of the device under test 5 is performed, and the judgment result is output.

Next, the operation of the second embodiment of the present invention will be described.

FIG. 16 is a flowchart for explaining the operation of the second embodiment according to the present invention. In the first embodiment, the power supply current information is converted into a frequency spectrum by the Fourier transform means 3 and is separated and output into the intensity information and the phase information of the spectrum. However, in the second embodiment of the present invention, The spectral element is output as one piece of information (step S15 in FIG. 16).

That is, the information (spectral element) subjected to the Fourier transform is expressed in a complex number expression such as a + jb in each term. Here, a and b represent real numbers, and j ²
= -1.

In the first embodiment, the information represented by a + jb is represented by ｔ (a ² + b ² ) as intensity information,
Although an ^-1 (b / a) is output as the phase information, in the second embodiment of the present invention, it is output in the form of a + jb complex number.

The complex number judging means 9 compares the information from the Fourier transform means 3 with a predetermined reference value in accordance with an instruction from the main control means 4 to determine whether the device under test 5 is good or bad.
A defect is determined and a result of the determination is output (step S16 in FIG. 16).

The other operations are the same as those described in the first embodiment. That is, steps S1, S2, S3, S4 in FIG. 15 and step S1 in FIG.
1, S12, S13, and S14 are the same processing operations.

The operation of the main control means 4 may be described in a control program, and the operation of each section may be controlled according to the control program. In this case, the control program may be stored in the recording means attached to the main control means 4 although not shown in FIG.
The recording means can be realized by a ROM, a floppy disk, or the like.

Next, in order to describe the second embodiment of the present invention more specifically, third and fourth embodiments will be described below.

[Embodiment 3] FIG. 8 is a block diagram showing a configuration of a third embodiment of the present invention. Referring to FIG.
This embodiment is different from the embodiment of FIG.
A complex number judgment unit 40 is provided instead of the intensity judgment unit 37, the phase judgment unit 38, and the total judgment unit 39.

The complex number judging unit 40 is connected to the Fourier transform unit 36 and the main controller 34, and based on the result of the Fourier transform unit 36 and a reference value prepared in advance according to an instruction from the main controller 34, determines the complex number of the device under test 35. The pass / fail judgment is made and the result is output.

Next, the operation of the third embodiment of the present invention will be described. FIG. 20 is a flowchart for explaining the operation of the third embodiment of the present invention.

The Fourier transform unit performs Fourier transform on the power supply current information sent from the current sampling unit 33 (step S55 in FIG. 20).

As a result of the Fourier transform, each term is represented by a complex number. The result of this conversion is the complex number determination unit 40
Is compared with a reference value prepared in advance, the pass / fail judgment of the device under test 35 is performed based on a predetermined criterion, and the result is output (FIG. 2).
0 step S56).

Note that steps S51, S52, S in FIG.
53 and S54 correspond to steps S41, S42, and S in FIG.
43 and S44, and a description thereof will be omitted.

FIG. 9 is a diagram for explaining an example of a method of judging good / bad of the device under test 35 performed by the complex number judging unit 40.

From the Fourier transform unit 36, data of five items is sent. Reference values are defined for each of the five items, and a standard range A for the real part and a standard range B for the imaginary part of each item are defined.

If the standard part falls within the standard range, that is, if the real part is within the range of the reference value ± standard range A and the imaginary part is within the range of the reference value ± standard range B, a pass judgment is made in the judgment of the relevant item.

In the example shown in FIG. 9, device A satisfies the standard range for all five items, and the determination result is 5
/ 5. Regarding the device B, two of the five items do not satisfy the standard range, and the determination result is 3/5. For device C, only one of the five items falls within the standard range, and the determination result is 1/5.

If the criterion A satisfies the standard with respect to 60% or more of the items, a non-defective item is determined.
As shown in determination result A, device A and device B
Is determined to be non-defective. The device B is determined to be defective.

If another criterion B is a criterion that all items are judged to be defective if they do not satisfy the specified range, as shown in the judgment result B, only the device A is a non-defective product. It is determined that the device B and the device C are defective. The criterion is appropriately determined according to the required reliability of the device under test and the allowable cost.

FIG. 10 is a diagram for explaining another example of a method of judging good / bad of the device under test 35 performed by the complex number judging unit 40. FIG. 10 shows a complex plane, in which the horizontal axis represents the real part and the vertical axis represents the imaginary part, and the standard range of each item is defined as a certain area on the complex plane.
If each item falls within the standard range based on the observation value of the device under test 35, a path determination is made. As a criterion,
If all of the items do not fall within the specification range, the product is determined to be defective, or as another determination criterion, the device under test 35 is determined to be non-defective if the specification is satisfied in 60% of the items.

[Embodiment 4] Next, a fourth embodiment of the present invention will be described. FIG. 24 is a block diagram showing the configuration of the fourth embodiment of the present invention. Referring to FIG. 24, in the present embodiment, the tester 44 includes a logic tester main unit 42, a power supply unit 32, a current sampling unit 33, a Fourier transform unit 36, a complex number determination unit 40, a main controller 34, It is provided with. Referring to FIG. 24, this embodiment is different from the logic tester 3 in the embodiment shown in FIG.
Instead of 1, a logic tester main unit 42 is provided. Other configurations, functions, and operations are the same as those of the embodiment shown in FIG. In this embodiment, the various functions of the embodiment shown in FIG.

[Embodiment 3] Next, a third embodiment of the present invention will be described. FIG. 11 is a block diagram showing a configuration of the third exemplary embodiment of the present invention. Referring to FIG. 11, a third embodiment of the present invention is different from the configuration of the first embodiment shown in FIG.
0 is provided.

The frequency selecting means 10 is provided between the Fourier transform means 3, the intensity judging means 6 and the phase judging means 7 in FIG. 1, and the Fourier transform means 3, the intensity judging means 6, the phase judging means 7 It is connected to the main control means 4.

The power supply current information which has been Fourier transformed by the Fourier transforming means 3 is sent to the frequency selecting means 10, and the frequency selecting means 10 selects only items corresponding to a predetermined frequency among the data subjected to the Fourier transform. Is extracted, and the intensity information and the phase information are sent to the intensity judging means 6 and the phase judging means 7, respectively.

Next, the operation of the third embodiment according to the present invention will be described. FIG. 17 is a flowchart for explaining the operation of the third embodiment according to the present invention.

The result of the conversion by the Fourier transform means 3 is the length T of the section of the power supply current observed by the power supply observation means 2.
, The spectrum of the frequency 1 / T and the frequency of an integer multiple thereof.

If the frequency required for performing the pass / fail judgment of the device under test 5 is predetermined, the result of the Fourier transform (frequency spectrum) by the Fourier transform means 3 requires all the elements. However, only the spectrum data of the required frequency is required. Therefore, only the spectrum of the necessary frequency is extracted by the frequency selection unit 10 and sent to the intensity determination unit 6 and the phase determination unit 7 (Step S26 in FIG. 17). The determination operation is the same as the operation of the first embodiment. In the third embodiment of the present invention, steps S21, S22, S2 in FIG.
3, S24, S25, S27, S28 and S29 correspond to FIG.
Steps S1, S2, S3, S4, S5, S6, S
7 and S8 respectively.

The main control means 4 may describe the control operation as a control program, and control the operation of each section by executing the control program by the computer of the main control means 4. In this case, for example, the control program is stored in a recording medium (not shown) such as a ROM or a floppy disk attached to the main control means 4 and loaded into the memory of the main control means 4 for execution.

Next, in order to describe the third embodiment of the present invention more specifically, fifth and sixth embodiments will be described below.

[Embodiment 5] FIG. 12 is a block diagram showing a configuration of a fifth embodiment of the present invention. Referring to FIG. 12, in the present embodiment, a frequency selection unit 41 is newly provided between the Fourier transform unit 36, the intensity judgment unit 37 and the phase judgment unit 38 in the configuration of the embodiment shown in FIG. I have. The frequency selection unit 41
The Fourier transform unit 36, the intensity determination unit 37, the phase determination unit 38, and the main controller 34 are connected. The frequency selection unit 41 extracts only data corresponding to a predetermined frequency from the data sent from the Fourier transform unit 36 in accordance with an instruction from the main controller 34, and determines the intensity information and the phase information based on the respective intensity determinations. It is sent to the unit 37 and the phase determination unit 38.

Next, the operation of the fifth embodiment of the present invention will be described. FIG. 21 is a flowchart for explaining the operation of the fifth embodiment of the present invention.

The current sampling unit 33 samples the power supply current value over a certain section (steps S63 and S64 in FIG. 21). That is, sampling of the current value is started according to an instruction from the main controller 34 (step S63 in FIG. 21), and after sampling for a predetermined time T, sampling is stopped according to the instruction from the main controller 34 (step S64 in FIG. 21).

The sampled data is Fourier-transformed by the Fourier-transform unit 36 (step S65 in FIG. 21). Since the original data is the data for the section T, the Fourier-transformed value is the frequency 1 / T, And a spectrum value at a frequency that is an integral multiple of the frequency. Of these frequency spectra, the good /
Since the frequency spectrum necessary for performing the failure determination is limited, only the frequency spectrum predetermined by the frequency selection unit 41 is extracted and sent to the intensity determination unit 37 and the phase determination unit 38 (step S in FIG. 21).
66). Other operations are the same as those in the first embodiment.
Steps S61, S62, S67, S68, S69 of 1
Correspond to steps S41, S42, S4 in FIG.
6, S47 and S48.

[Embodiment 6] Next, a sixth embodiment of the present invention will be described. FIG. 25 is a block diagram showing the configuration of the sixth embodiment of the present invention. Referring to FIG. 25, the tester 45 includes a logic tester main unit 42, a power supply unit 32, a current sampling unit 33, a Fourier transform unit 36, and a frequency selection unit 41.
, Intensity determination unit 37 and phase determination unit 38
, The overall judgment unit 39 and the main controller 34
And, it consists of. Referring to FIG. 25, this embodiment is different from the logic tester 31 of the embodiment shown in FIG.
, A logic tester main unit 42 is provided. Other configurations, functions, and operations are the same as those of the embodiment shown in FIG. In this embodiment, various functions of the fourth embodiment shown in FIG. 12 are incorporated in one tester 45.

[Fourth Embodiment] Next, a fourth embodiment of the present invention will be described. FIG. 13 is a block diagram showing a configuration of the fourth exemplary embodiment of the present invention. Referring to FIG. 13, a fourth embodiment of the present invention is different from the configuration of the second embodiment shown in FIG.
0 is provided. The frequency selecting means 10 is provided between the Fourier transform means 3 and the complex number judging means 9 and is connected to the Fourier transform means 3, the complex number judging means 9 and the main control means 4. The frequency selecting means 10 extracts only data relating to a necessary frequency from the data sent from the Fourier transform means 3 and sends it to the complex number judging means 9.

Next, the operation of the fourth embodiment of the present invention will be described. FIG. 18 is a flowchart for explaining the operation of the embodiment of the present invention. The power supply current value observed over the section T by the power supply observation means is subjected to Fourier transform by the Fourier transform means 3 on the power supply current information. Since the data is in the section T, each value subjected to the Fourier transform indicates a spectrum value at a frequency of 1 / T and a frequency that is an integral multiple of the frequency. Since the frequency spectrum necessary for the determination of good / defective of the device under test 5 is limited, it is appropriately extracted by the frequency selection means 10 and sent to the complex number determination means 9 (step S36 in FIG. 18). Other operations are the same as the operations of the second embodiment, and FIG.
8, steps S31, S32, S33, S34, S3
5 and S37 correspond to steps S11 and S1 in FIG.
2, S13, S14, S15, and S16.

The main control means 4 may describe the control operation as a control program, and control the operation of each section by executing the control program by the computer of the main control means 4. In this case, for example, the control program is stored in a recording medium (not shown) such as a ROM or a floppy disk attached to the main control means 4 and loaded into the memory of the main control means 4 for execution.

In order to describe the fourth embodiment of the present invention more specifically, seventh and eighth embodiments will be described below.

[Embodiment 7] FIG. 14 is a block diagram showing a configuration of a seventh embodiment of the present invention. Referring to FIG. 14, in a seventh embodiment of the present invention, a frequency selection unit 41 is newly provided in the configuration of the third embodiment shown in FIG. The frequency selection unit 41 is connected to the Fourier transform unit 36, the complex number judgment unit 40, and the main controller 34. From the data sent from the Fourier transform unit 36, only corresponding data of a predetermined frequency is extracted and sent to the complex number judging unit 40 in accordance with an instruction from the main controller.

Next, the operation of the seventh embodiment of the present invention will be described. FIG. 22 is a flowchart for explaining the operation of the seventh embodiment of the present invention.

The data sampled over the section T by the current sampling unit 33 is Fourier transformed by the Fourier transform unit 36 (step S7 in FIG. 22).
5). The result of the Fourier transform is nothing but a spectrum of a frequency 1 / T and a frequency that is an integral multiple thereof. The frequency spectrum required for the non-defective / defective product determination of the device under test 35 is limited, and only the required frequency is extracted by the frequency selection unit 41 and sent to the complex number determination unit 40 (step S76 in FIG. 22). Other operations are the same as those of the example of the second embodiment according to the present invention.
Steps S71, S72, S73, S74, S77 of the second
Respectively correspond to steps S51, S52, S5 in FIG.
3, S54 and S56.

[Embodiment 8] Next, an eighth embodiment of the present invention will be described. FIG. 26 is a block diagram showing the configuration of the eighth embodiment of the present invention. Referring to FIG. 26, in this embodiment, the tester 46 includes a logic tester main unit 42, a power supply unit 32, a current sampling unit 33, a Fourier transform unit 36, a frequency selection unit 41, and a complex number determination unit 40. , And a main controller 34. Referring to FIG. 26, this embodiment has the same configuration, function, and operation as FIG. 14 except that a logic tester main unit 42 is provided instead of the logic tester 31 of the embodiment. This is the same as the embodiment shown in FIG. This embodiment incorporates various functions of the embodiment shown in FIG. 14 into one tester 45.

[0131]

As described above, according to the present invention, the following effects can be obtained.

A first effect of the present invention is that the defect inspection is performed with high accuracy.

The reason for this is that, in the present invention, the failure determination is performed based on information having two components of a frequency spectrum, an intensity component and a phase component, and substantially two components as a complex number.

A second effect of the present invention is that the inspection speed is increased.

The reason is that it takes time to observe the value of the power supply current required for the inspection of the integrated circuit in the time domain with the required accuracy, but to observe it in the frequency domain, it takes Fourier transform. This is because only the time is required, and the inspection can be performed at a higher speed as compared with the observation in the time domain.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a block diagram illustrating details of a configuration according to the first exemplary embodiment of the present invention.

FIG. 3 is a block diagram illustrating details of a configuration according to the first exemplary embodiment of the present invention.

FIG. 4 is a diagram for explaining the first embodiment of the present invention, and is a diagram showing a relationship between power supply current observation timings.

FIG. 5 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 6 is a schematic diagram illustrating a defect determination according to the first embodiment of the present invention.

FIG. 7 is a block diagram illustrating a configuration of a second exemplary embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a third exemplary embodiment of the present invention.

FIG. 9 is a schematic diagram illustrating a defect determination according to the second embodiment of the present invention.

FIG. 10 is a schematic diagram illustrating a defect determination according to the second embodiment of the present invention.

FIG. 11 is a block diagram showing a configuration of a third exemplary embodiment of the present invention.

FIG. 12 is a block diagram showing a configuration of a fifth example of the present invention.

FIG. 13 is a block diagram illustrating a configuration of a fourth exemplary embodiment of the present invention.

FIG. 14 is a block diagram showing a configuration of a seventh exemplary embodiment of the present invention.

FIG. 15 is a flowchart illustrating the operation of the first exemplary embodiment of the present invention.

FIG. 16 is a flowchart illustrating an operation of the second exemplary embodiment of the present invention.

FIG. 17 is a flowchart illustrating an operation of the third exemplary embodiment of the present invention.

FIG. 18 is a flowchart illustrating an operation of the fourth exemplary embodiment of the present invention.

FIG. 19 is a flowchart illustrating an operation of the first exemplary embodiment of the present invention.

FIG. 20 is a flowchart illustrating the operation of the third embodiment of the present invention.

FIG. 21 is a flowchart illustrating the operation of the fifth embodiment of the present invention.

FIG. 22 is a flowchart illustrating the operation of the seventh embodiment of the present invention.

FIG. 23 is a block diagram showing a configuration of a third example of the present invention.

FIG. 24 is a block diagram showing a configuration of a fourth example of the present invention.

FIG. 25 is a block diagram showing a configuration of a sixth example of the present invention.

FIG. 26 is a block diagram showing a configuration of an eighth example of the present invention.

FIG. 27 is a diagram illustrating the principle of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Test signal generation means 2 Power supply observation means 3 Fourier transform means 4 Main control means 5 Device under test 6 Strength judgment means 7 Phase judgment means 8 Total judgment means 9 Complex number judgment means 10 Frequency selection means 31 Logic tester 32 Power supply unit 33 Current Sampling unit 34 Main controller 35 Device under test 36 Fourier transform unit 37 Intensity judgment unit 38 Phase judgment unit 39 Total judgment unit 40 Complex number judgment unit 41 Frequency selection unit 42 Logic tester main unit 43 Tester 44 Tester 45 Tester 46 Tester 101 Program storage means Reference Signs List 102 test pattern storage means 103 control means 104 signal generation means 201 controlled voltage source 202 current detection means 203 voltage control means

Claims (23)

(57) [Claims] 1. A predetermined cycle T consisting of a plurality of test vectors
Is repeatedly applied to the device under test, the power supply current of the device under test during the application of the test signal is sampled, the sampled value of the power supply current is subjected to Fourier transform, and a frequency spectrum having 1 / T as a fundamental frequency The magnitude / phase information of the frequency spectrum or the values of the real part and the imaginary part of the frequency spectrum are determined to be good / bad for the device under test based on the degree of being within a standard value with respect to a reference value. A failure test method for calculating the degree of failure, and determining whether the device under test is good or bad. 2. An integrated circuit failure inspection apparatus for measuring a power supply current of an integrated circuit, which is a device under test, and checking whether the integrated circuit is good or defective based on a frequency spectrum of the power supply current. Test signal generating means for repeatedly applying a unit test signal having a period T to the device under test, means for supplying power to the device under test, and sampling power supply current of the device under test during application of the test signal; Fourier-transform the sampled value of the power supply current to obtain 1 / T
The frequency spectrum having the fundamental frequency is obtained, and the magnitude and phase information of the frequency spectrum or the values of the real part and the imaginary part of the frequency spectrum are each based on the degree of being within a standard value with respect to a reference value. A failure inspection apparatus comprising: means for calculating a degree of a device when the device is defective; and means for comprehensively determining whether or not the device under test is good or bad based on data of the degree of the defect. 3. An integrated circuit failure inspection apparatus for measuring a power supply current of an integrated circuit, which is a device under test, and inspecting a pass / fail of the integrated circuit based on a frequency spectrum of the power supply current, wherein the test is applied to the device under test. Test signal generating means for generating a test signal; power supply observing means for supplying power to the device under test and observing the value of the supplied power current; and observation information of the power current obtained by the power supply observing means Fourier transform means for obtaining a frequency spectrum by performing a Fourier transform on the device under test by inputting intensity information of the frequency spectrum obtained by the Fourier transform means and comparing the intensity information with a predetermined reference value. Strength determining means for determining the degree of failure of the frequency spectrum; and phase information of the frequency spectrum obtained by the Fourier transform means. Is compared with a predetermined reference value to determine the degree of failure of the device under test, and a predetermined determination using the determination results obtained by the intensity determining means and the phase determining means as an input. An integrated circuit failure inspection apparatus, comprising: a comprehensive determination unit that determines a non-defective / defective product of the device under test according to a standard; and a main control unit that controls each of the units. 4. The main control means includes means for generating the test signal in the test signal generating means, starting and ending the supply of power in the power supply observing means and observing the value of the power supply current, and controlling the Fourier transform means. The execution of a Fourier transform, the execution of the determination by the intensity determination unit and the phase determination unit, and the execution of a determination of a non-defective / defective product of the device under test by the comprehensive determination unit are command-controlled, respectively. An integrated circuit failure inspection apparatus according to claim 2. 5. An integrated circuit failure inspection apparatus for measuring a power supply current of an integrated circuit, which is a device under test, and checking whether the integrated circuit is good or defective based on a frequency spectrum of the power supply current, is applied to the device under test. Test signal generating means for generating a test signal; power supply observing means for supplying power to the device under test and observing the value of the supplied power current; and observation information of the power current obtained by the power supply observing means Fourier transforming means for obtaining a frequency spectrum by Fourier transforming, and a frequency spectrum in a complex number format obtained by the Fourier transforming means is inputted, and a real part and an imaginary part of the frequency spectrum are respectively compared with predetermined reference values. And a main control unit that controls each of the units under test. Failure detection apparatus for an integrated circuit according to claim. 6. The fault inspection system for an integrated circuit according to claim 3, wherein a frequency spectrum output from said Fourier transform means is input, a frequency is selected, and intensity information and phase information of the selected frequency spectrum are respectively obtained. A fault inspection apparatus for an integrated circuit, comprising: a frequency selection unit that supplies the intensity determination unit and the phase determination unit. 7. The integrated circuit failure inspection apparatus according to claim 5, wherein a frequency spectrum output from said Fourier transform means is input, a frequency is selected, and the selected frequency spectrum is supplied to said complex number judging means. An integrated circuit failure inspection device comprising a selection unit. 8. A failure tester for an integrated circuit for testing a failure of the integrated circuit based on a frequency spectrum of a power supply current of the integrated circuit as the device under test, wherein the logic tester generates a test signal to be applied to the device under test. A power supply unit that generates a power supply of the device under test; a current sampling unit that observes a power supply current supplied by the device under test; a Fourier transform that inputs current observation information from the current sampling unit and performs a Fourier transform A strength determination unit for determining the degree of failure of the device under test by inputting strength information of the frequency spectrum obtained by the Fourier transform unit and comparing the strength information with a reference value prepared in advance; Enter the phase information of the frequency spectrum obtained by the conversion unit By comparing with a reference value prepared for, a phase determination unit that determines the degree of failure of the device under test, and the determination result of the intensity determination unit, from the determination result of the phase determination unit, In accordance with a predetermined determination criterion, a comprehensive determination unit that determines a non-defective / defective product of the device under test, and issues a command to the logic tester, generates the test signal, issues a command to the power supply unit, Generating the power supply, issuing a sampling start command and an end command to the current sampling unit, executing the sampling of the value of the power supply current, issuing a command to the Fourier transform unit, Fourier transforming the power supply current information, A command is issued to the strength determination unit to determine the degree of failure of the device under test. Command to the
A main controller for determining the degree of failure of the device under test, issuing a command to the overall determination unit, and performing a non-defective / defective determination of the device under test according to a predetermined determination criterion. Characteristic integrated circuit failure inspection device. 9. The fault inspection apparatus for an integrated circuit according to claim 8, wherein said Fourier transform unit is used instead of said intensity judgment unit, said phase judgment unit and said comprehensive judgment unit.
Input the obtained frequency spectrum of complex number format,
Predetermine the real and imaginary parts of the frequency spectrum respectively
Pass / fail of the device under test as compared to the reference value
Failure detection apparatus for an integrated circuit, characterized by comprising a complex determination unit determines. 10. The fault inspection apparatus for an integrated circuit according to claim 8, wherein a frequency spectrum output from the Fourier transform unit is input, a frequency is selected, and the intensity information and the phase information of the selected frequency spectrum are respectively obtained. A fault inspection apparatus for an integrated circuit, comprising: an intensity determination unit; and a frequency selection unit that supplies the frequency determination unit to the phase determination unit. 11. The fault testing apparatus for an integrated circuit according to claim 9, wherein a frequency is selected from a frequency spectrum output from said Fourier transform means, and the selected frequency spectrum is supplied to said complex number judging unit. An integrated circuit failure inspection device comprising a selection unit. 12. An integrated circuit failure inspection method for inspecting a failure of the integrated circuit based on a frequency spectrum of a power supply current of the integrated circuit as the device under test. (A) A test signal is generated and applied to the device under test. (B) generating and supplying power to the device under test; (c) starting observation of the power supply current value; and (d) stopping observation of the power supply current value. (E) Fourier transforming the information of the observed power supply current; and (f) comparing the intensity information of the spectrum obtained by the Fourier transform with a reference value prepared in advance to obtain the device under test. (G) comparing the phase information of the spectrum obtained by the Fourier transform with a reference value prepared in advance, and Determining the degree of failure of the device under test; (h) based on the degree of failure determined from the intensity information and the phase information, according to a previously prepared determination criterion. Performing a failure determination; and a failure inspection method for an integrated circuit. 13. A failure test method for an integrated circuit for performing a failure test on an integrated circuit based on a frequency spectrum of a power supply current of an integrated circuit which is a device under test. (A) generating a test signal and applying the test signal to the device under test (B) generating and supplying power to the device under test; (c) starting observation of the power supply current value; and (d) stopping observation of the power supply current value. (E) Fourier transforming the information of the observed power supply current; and (f) receiving a result of the Fourier transform in a complex number format .
Comparing the real and imaginary parts with a reference value set in advance, respectively, fault test method for an integrated circuit including, determining a pass / fail of the integrated circuit under test. 14. An integrated circuit failure inspection method for inspecting a failure of the integrated circuit based on a frequency spectrum of a power supply current of the integrated circuit as the device under test. (A) generating a test signal and applying the test signal to the device under test (B) generating and supplying power to the device under test; (c) starting observation of the power supply current value; and (d) stopping observation of the power supply current value. (E) Fourier transforming the observed power supply current information; (f) extracting only a predetermined frequency from the Fourier transformed result; (g) extracting the extracted spectrum. Comparing the strength information with a reference value prepared in advance to determine the degree of failure of the device under test; Comparing the phase information of the device with a reference value prepared in advance to determine the degree of failure of the device under test; (i) determining the degree of failure determined from the intensity information and the phase information. Determining whether the device under test is good or bad based on a previously prepared criterion. 15. An integrated circuit failure inspection method for inspecting a failure of an integrated circuit based on a frequency spectrum of a power supply current of the integrated circuit as a device under test, comprising: (a) generating a test signal and applying the test signal to the device under test; (B) generating and supplying power to the device under test; (c) starting observation of the power supply current value; and (d) stopping observation of the power supply current value. (E) Fourier transforming the observed power supply current information; (f) extracting only a predetermined frequency spectrum from the Fourier transformed result; (g) the extracted spectrum receive with complex format
Risono real and imaginary parts is compared with the reference value set in advance, respectively, fault test method for an integrated circuit including, determining a pass / fail of the integrated circuit under test. 16. A program-controlled failure inspection apparatus for performing a failure inspection of an integrated circuit as a device under test from a frequency spectrum of a power supply current of the integrated circuit, wherein: (a) a test signal is generated by a test signal generation means; A process of controlling a test signal to be applied to the device under test; (b) generating a power to the power supply observing means, supplying the power to the device under test, and starting the sampling of the value of the power supply current. (C) a process of controlling the sampling of the power supply current to be performed by the Fourier transforming means, and (d) a process of performing the Fourier transform on the sampling information of the power supply current. Determining the degree of failure of the device under test from the strength information among the results, (e) the Fourier Determining the degree of failure of the device under test from the phase information, and (f) determining whether the device under test is good based on the determination result from the intensity information and the determination result from the phase information. A recording medium on which a control program for causing the failure inspection device to execute each of the above-described processes (a) to (f) is described. 17. A failure inspection apparatus under program control for performing a failure inspection of an integrated circuit as a device under test from a frequency spectrum of a power supply current of the integrated circuit, wherein: (a) a test signal is generated by test signal generation means; A process of controlling a test signal to be applied to the device under test; (b) generating a power to the power supply observing means, supplying the power to the device under test, and starting the sampling of the value of the power supply current. (C) processing to stop sampling of the value of the power supply current, (c) processing to perform Fourier transformation of the sampling information of the power supply current by the Fourier transform means, and (d) the Fourier transformation. receives the results were converted in a complex number format
Predetermined reference for the real part and imaginary part respectively
A recording medium storing a control program for causing the apparatus to execute each of the above-described processes (a) to (d) by comparing the value with a value to determine whether the device under test is good or bad. 18. A failure control apparatus for performing a failure test on an integrated circuit, which is a device under test, from a frequency spectrum of a power supply current of the integrated circuit, the failure signal being controlled by a program control. A process of controlling a test signal to be applied to the device under test; (b) generating a power to the power supply observing means, supplying the power to the device under test, and starting the sampling of the value of the power supply current. (C) a process of controlling so as to stop sampling of the value of the power supply current, (c) a process of controlling the Fourier transform means to perform a Fourier transform of the sampling information of the power supply current, and (d) a process of performing the Fourier transform. (E) extracting a frequency spectrum for a predetermined frequency from the extracted values. And of the frequency spectrum, the process determines defective degree of the device under test from the intensity information, (f) among the extracted frequency spectrum, the process determines defective degree of the device under test from the phase information,
And (g) a process of determining whether the device under test is good or defective based on the determination result from the intensity information and the determination result from the phase information. A recording medium on which a control program to be executed by the failure inspection device is recorded. 19. A failure control apparatus for performing a failure test on an integrated circuit, which is a device under test, from a frequency spectrum of a power supply current of the integrated circuit, wherein the test signal generation means generates a test signal. A process of controlling a test signal to be applied to the device under test; (b) generating a power to the power supply observing means, supplying the power to the device under test, and starting the sampling of the value of the power supply current. (C) a process of controlling the sampling of the power supply current to be stopped, and (c) a process of controlling the Fourier transform means to perform a Fourier transform of the sampling information of the power supply current. Extracting a frequency spectrum with respect to a predetermined frequency from the calculated values; In the complex format issued frequency spectrum
Receive the real part and imaginary part of each
A recording medium in which a control program for causing the apparatus to execute each of the above-described processes (a) to (f) of comparing the reference value with the reference value to determine whether the device under test is good or bad. 20. A tester for inspecting a failure of an integrated circuit, comprising: a logic tester main unit for generating a test signal to be applied to a device under test; a power supply unit for generating power for the device under test; and a connection to the power supply unit. A current sampling unit for observing a power supply current supplied by the device under test; a Fourier transform unit connected to the current sampling unit for performing Fourier transform from current observation information; and a Fourier transform connected to the Fourier transform unit. By receiving the converted intensity information and comparing it with a reference value prepared in advance, an intensity determination unit that determines the degree of failure of the device under test, and a Fourier transform unit connected to the Fourier transform unit, Received phase information of the result is prepared in advance A phase determination unit that determines the degree of failure of the device under test by comparing the measured value with the reference value, the intensity determination unit, and the phase determination unit that are connected to the determination result of the intensity determination unit; From the determination result in the determination unit, according to a predetermined determination criterion, a comprehensive determination unit that performs a non-defective / defective determination of the device under test, and issues a command to the logic tester main unit to generate the test signal. Causing the power supply unit to issue a command, causing the power supply to be generated, issuing a sampling start command and an end command to the current sampling unit, executing sampling of the value of the power supply current, issuing a command to the Fourier transform unit, The power supply current information is Fourier-transformed, and a command is issued to the intensity determination unit, The degree of failure of the device under test, issue a command to the phase determination unit, determine the degree of failure of the device under test, issue a command to the overall determination unit, and according to a predetermined determination criterion, An integrated circuit tester comprising: a main controller for executing a good / defective product determination; 21. A tester for an integrated circuit according to claim 20, further comprising a complex number judgment unit instead of said intensity judgment unit, said phase judgment unit and said general judgment unit. 22. An integrated circuit tester according to claim 20, further comprising a frequency selection unit. 23. An integrated circuit tester according to claim 22, further comprising a complex number judgment unit instead of said intensity judgment unit, said phase judgment unit and said general judgment unit.