JP3191112U - Semiconductor device and case for semiconductor device - Google Patents

Semiconductor device and case for semiconductor device Download PDF

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JP3191112U
JP3191112U JP2014001612U JP2014001612U JP3191112U JP 3191112 U JP3191112 U JP 3191112U JP 2014001612 U JP2014001612 U JP 2014001612U JP 2014001612 U JP2014001612 U JP 2014001612U JP 3191112 U JP3191112 U JP 3191112U
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case
semiconductor device
sealing material
protrusion
insulating substrate
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直樹 三枝
直樹 三枝
尚 香月
尚 香月
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Priority to CN201520138599.5U priority patent/CN204558442U/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

【課題】ケースの上面近傍まで封止材を注入した場合であっても、外観不良や蓋との接着性低下を招くことのない半導体装置を提供する。【解決手段】半導体装置１は、絶縁基板２と、絶縁基板２上に搭載された半導体素子３と、絶縁基板２の周縁を囲い、半導体素子３を収容する中空のケース６と、ケース６内に充填され、ケース内を封止する封止材１０とを備える。ケース６は、ケース６の上面６ｃから部分的に突出する突起部６ｆを有する。【選択図】図１PROBLEM TO BE SOLVED: To provide a semiconductor device which does not cause poor appearance or deterioration of adhesiveness to a lid even when a sealing material is injected to the vicinity of the upper surface of a case. A semiconductor device (1) includes an insulating substrate 2, a semiconductor element (3) mounted on the insulating substrate (2), a hollow case (6) surrounding the peripheral edge of the insulating substrate (2) and accommodating the semiconductor element (3), and a case (6). It is provided with a sealing material 10 which is filled in and seals the inside of the case. The case 6 has a protrusion 6f that partially protrudes from the upper surface 6c of the case 6. [Selection diagram] Fig. 1

Description

本考案は、半導体装置及び半導体装置用ケースに関する。   The present invention relates to a semiconductor device and a case for a semiconductor device.

半導体装置として、１又は２以上のパワー半導体素子（半導体チップ）をケース内に内蔵し、ケース内が封止材で封止されたパワー半導体モジュールが知られている。これらのパワー半導体素子は、絶縁基板上に搭載された半導体チップを、当該絶縁基板に形成された電気回路や端子と電気的に接続するために、アルミニウム製のボンディングワイヤ等が用いられている。   As a semiconductor device, a power semiconductor module in which one or more power semiconductor elements (semiconductor chips) are built in a case and the inside of the case is sealed with a sealing material is known. In these power semiconductor elements, an aluminum bonding wire or the like is used to electrically connect a semiconductor chip mounted on an insulating substrate to an electric circuit or a terminal formed on the insulating substrate.

ケース内の封止材は、エポキシ樹脂等からなり、ケース内に収容された半導体チップやボンディングワイヤ等を保護し、かつ、絶縁するためのものである。したがって、パワー半導体モジュールにおいて、封止材は、ケース内のボンディングワイヤを十分に覆い絶縁する高さでケース内に充填される。その一方で、パワー半導体モジュールは小型化、薄型化の要請があり、ケースの高さについても支障のない限り低くすることが望ましい。このような封止材によるケース内の絶縁性と小型化、薄型化との兼ね合いにより、液状の封止材をケース内に注入する際は、当該封止材を、ケースの上面近傍まで注入していた。
封止材が、ケースの上縁近傍まで注入されるため、注入の際に封止材がケースの上面まで乗り上げることがあった。また注入後、封止材を固化するまでの間の搬送時に、封止材がケースの上面まで乗り上げることがあった。
このような封止材のケースの上面への乗り上げは、パワー半導体モジュールの外観不良を招き、またケースを蓋で覆い接着固定する場合に、ケースの接着面である上面が平坦でないために接着性の低下を招く場合があった。 The sealing material in the case is made of epoxy resin or the like, and is intended to protect and insulate semiconductor chips, bonding wires, and the like housed in the case. Therefore, in the power semiconductor module, the sealing material is filled in the case at a height that sufficiently covers and insulates the bonding wires in the case. On the other hand, there is a demand for miniaturization and thinning of the power semiconductor module, and it is desirable to reduce the height of the case as long as there is no problem. When injecting liquid sealing material into the case, the sealing material is injected to the vicinity of the upper surface of the case due to the balance between insulation and downsizing and thinning in the case. It was.
Since the sealing material is injected up to the vicinity of the upper edge of the case, the sealing material sometimes runs up to the upper surface of the case during the injection. In addition, the sealing material sometimes climbs up to the upper surface of the case during the transportation after the injection until the sealing material is solidified.
Such a sealant climbing onto the upper surface of the case causes poor appearance of the power semiconductor module, and when the case is covered with a lid and bonded and fixed, the upper surface, which is the bonding surface of the case, is not flat. In some cases, this could lead to a decrease.

封止材の乗り上げを防止するために、ケースの内面にフランジを設けること（特許文献１）やケースの内面に段付き部を設けること（特許文献２）が提案されている。   In order to prevent the sealing material from running, it has been proposed to provide a flange on the inner surface of the case (Patent Document 1) and to provide a stepped portion on the inner surface of the case (Patent Document 2).

特開平８−１３０２９１号公報JP-A-8-130291 特開平４−３５４３５４号公報JP-A-4-354354

しかし、ケース内面に設けられたフランジや段付き部は、ケースの内側に向けて形成されたものであるから、封止材がケースの上面に達するのを未然に防ぐものであり、封止材の注入量は、そのフランジや段付き部が形成された高さまでに制限される。したがって、封止材をできる限りケースの上面近傍まで注入して絶縁性を高めるという要請に十分に応えるものではなかった。また、仮に封止材をケースの上面近傍まで注入した場合には、封止材のケース上面への乗り上げを防止するのが困難であった。   However, since the flange and the stepped portion provided on the inner surface of the case are formed toward the inside of the case, the sealing material prevents the sealing material from reaching the upper surface of the case. The injection amount is limited to the height at which the flange and the stepped portion are formed. Therefore, it did not fully meet the demand to improve the insulation by injecting the sealing material as close to the upper surface of the case as possible. Further, if the sealing material is injected to the vicinity of the upper surface of the case, it is difficult to prevent the sealing material from climbing onto the upper surface of the case.

本考案は、上記した従来の半導体装置の問題を有利に解決するものであり、ケースの上面近傍まで封止材を注入した場合であっても、外観不良や蓋との接着性低下を招くことのない半導体装置及び半導体装置用ケースを提供することを目的とする。   The present invention advantageously solves the above-described problems of the conventional semiconductor device, and even when the sealing material is injected up to the vicinity of the upper surface of the case, it causes a poor appearance and a decrease in adhesion to the lid. It is an object of the present invention to provide a semiconductor device and a case for the semiconductor device that are free from defects.

上記目的を達成するために以下のような半導体装置及び半導体装置用ケースが提供される。
本考案の半導体装置は、絶縁基板と、該絶縁基板上に搭載された半導体素子と、該絶縁基板の周縁を囲い、該半導体素子を収容する中空のケースと、該ケース内に充填され、該ケース内を封止する封止材とを備える。かつ、本考案の半導体装置は、該ケースが、該ケースの上面から部分的に突出する突起部を有するものである。 In order to achieve the above object, the following semiconductor device and semiconductor device case are provided.
A semiconductor device of the present invention includes an insulating substrate, a semiconductor element mounted on the insulating substrate, a hollow case that surrounds the periphery of the insulating substrate and accommodates the semiconductor element, and the case is filled, And a sealing material for sealing the inside of the case. In the semiconductor device of the present invention, the case has a protrusion that partially protrudes from the upper surface of the case.

本考案の半導体装置用ケースは、絶縁基板の周縁を囲い、半導体素子を収容し、封止材が充填される中空のケースであって、該ケースの上面から部分的に突出する突起部を有するものである。   A case for a semiconductor device according to the present invention is a hollow case that surrounds the periphery of an insulating substrate, accommodates a semiconductor element, and is filled with a sealing material, and has a protrusion partly protruding from the upper surface of the case. Is.

本考案の半導体装置は、ケースの上面に部分的に突起が形成され、封止材が当該ケースの上面に乗り上げたとしても突起部上には乗り上げられない。したがって外観不良を防止することができる。また、ケース上面の平坦性が維持され、ケース上面と蓋とを接着する際の接着性を十分に確保することができる。   In the semiconductor device of the present invention, a protrusion is partially formed on the upper surface of the case, and even if the sealing material rides on the upper surface of the case, it does not ride on the protrusion. Therefore, appearance defects can be prevented. Further, the flatness of the upper surface of the case is maintained, and sufficient adhesion can be ensured when the upper surface of the case and the lid are bonded.

本考案の実施形態のパワー半導体モジュールの断面図である。It is sectional drawing of the power semiconductor module of embodiment of this invention. 図１のパワー半導体モジュールの平面図である。It is a top view of the power semiconductor module of FIG. 図１のパワー半導体モジュールの断面図である。It is sectional drawing of the power semiconductor module of FIG. 図１のパワー半導体モジュールの部分拡大平面図である。FIG. 2 is a partially enlarged plan view of the power semiconductor module of FIG. 1. 蓋を備えるパワー半導体モジュールの断面図である。It is sectional drawing of a power semiconductor module provided with a cover. 本考案の実施形態のパワー半導体モジュールの変形例の平面図である。It is a top view of the modification of the power semiconductor module of embodiment of this invention. 本考案の実施形態のパワー半導体モジュールの変形例の平面図である。It is a top view of the modification of the power semiconductor module of embodiment of this invention. 図６のパワー半導体モジュールの部分拡大平面図である。FIG. 7 is a partially enlarged plan view of the power semiconductor module of FIG. 6. 図７のパワー半導体モジュールの部分拡大平面図である。FIG. 8 is a partially enlarged plan view of the power semiconductor module of FIG. 7. 参考例のパワー半導体モジュールの平面図である。It is a top view of the power semiconductor module of a reference example. 従来のパワー半導体モジュールの断面図である。It is sectional drawing of the conventional power semiconductor module. 図１１のパワー半導体モジュールの断面図である。It is sectional drawing of the power semiconductor module of FIG. 図１１のパワー半導体モジュールの部分拡大平面図である。FIG. 12 is a partially enlarged plan view of the power semiconductor module of FIG. 11.

本考案の半導体装置及び半導体装置用ケースの実施形態を、図面を用いて具体的に説明する。
図１に本考案の実施形態１の半導体装置としてのパワー半導体モジュールの断面図を示す。図１に示されたパワー半導体モジュール１は、絶縁基板２上に半導体チップ３が搭載されている。絶縁基板２は、金属基板２ａと、この金属基板２ａ上に設けられた絶縁板２ｂと、絶縁板２ｂ上に設けられた金属箔２ｃとを備えている。絶縁板２ｂは、窒化珪素、アルミナ、窒化アルミニウム等のセラミックス材料や、エポキシ樹脂等の有機絶縁材料よりなる。金属箔２ｃは、具体的には例えば銅箔である。金属箔２ｃは絶縁板２ｂ上で選択的に形成されていて、これにより半導体チップ３の下面に形成された電極や後述するリードと接続する回路パターンが形成されている。 Embodiments of a semiconductor device and a case for a semiconductor device of the present invention will be specifically described with reference to the drawings.
FIG. 1 shows a cross-sectional view of a power semiconductor module as a semiconductor device according to Embodiment 1 of the present invention. A power semiconductor module 1 shown in FIG. 1 has a semiconductor chip 3 mounted on an insulating substrate 2. The insulating substrate 2 includes a metal substrate 2a, an insulating plate 2b provided on the metal substrate 2a, and a metal foil 2c provided on the insulating plate 2b. The insulating plate 2b is made of a ceramic material such as silicon nitride, alumina, or aluminum nitride, or an organic insulating material such as an epoxy resin. Specifically, the metal foil 2c is, for example, a copper foil. The metal foil 2c is selectively formed on the insulating plate 2b, whereby a circuit pattern connected to an electrode formed on the lower surface of the semiconductor chip 3 and a later-described lead is formed.

半導体チップ３は、接合材としての例えばはんだ４によって、金属箔２ｃよりなる配線パターン上に接合されて、電気的に接合されている。半導体チップ３は、例えばダイオードやトランジスタチップであり、トランジスタチップとしてはＩＧＢＴチップやＭＯＳＦＥＴチップ等を用いることができ、半導体チップ３の種類は特に限定されない。また、半導体チップ３の基板として単結晶シリコンの他、シリコンカーバイド（ＳｉＣ）やガリウムナイトライド（ＧａＮ）を用いることもできる。図１では、半導体チップ３がダイオードチップである例を説明している。なお、図１では、一つの絶縁基板２の金属箔２ｃ上に１個の半導体チップ３が搭載されているところを図示しているが、一つの絶縁基板２の金属箔２ｃ上に２個以上の半導体チップ３が搭載されてもよい。
また、図１では、金属箔２ｃよりなる配線パターンにコンデンサチップ５が接続されている。 The semiconductor chip 3 is bonded and electrically bonded onto the wiring pattern made of the metal foil 2c by, for example, solder 4 as a bonding material. The semiconductor chip 3 is, for example, a diode or a transistor chip, and an IGBT chip or a MOSFET chip can be used as the transistor chip, and the type of the semiconductor chip 3 is not particularly limited. In addition to single crystal silicon, silicon carbide (SiC) or gallium nitride (GaN) can be used as the substrate of the semiconductor chip 3. FIG. 1 illustrates an example in which the semiconductor chip 3 is a diode chip. 1 shows that one semiconductor chip 3 is mounted on the metal foil 2c of one insulating substrate 2, two or more are provided on the metal foil 2c of one insulating substrate 2. The semiconductor chip 3 may be mounted.
In FIG. 1, a capacitor chip 5 is connected to a wiring pattern made of a metal foil 2c.

半導体チップ３が搭載された絶縁基板２の周縁にケース６が取り付けられている。具体的に、ケース６は、ＰＰＳ樹脂等の絶縁性樹脂からなる中空（枠形状）の概略直方体形状であり、上端部６ａが開口となり、ケース６内の中空空間に上端部６ａから封止材１０を注入可能になっている。ケース６の下端部６ｂは、絶縁基板２の金属基板２ａ及び絶縁板２ｂに対して、絶縁性接着剤７によって接合されている。絶縁性接着剤７によって接合されることにより、絶縁基板２とケース６との絶縁性を確保するとともに、絶縁基板２とケース６との隙間をなくし、隙間から封止材１０が外部に漏れ出るのを防止している。   A case 6 is attached to the periphery of the insulating substrate 2 on which the semiconductor chip 3 is mounted. Specifically, the case 6 has a hollow (frame shape) substantially rectangular parallelepiped shape made of an insulating resin such as PPS resin, the upper end portion 6a is an opening, and the sealing material is formed in the hollow space in the case 6 from the upper end portion 6a. 10 can be injected. The lower end 6 b of the case 6 is bonded to the metal substrate 2 a and the insulating plate 2 b of the insulating substrate 2 with an insulating adhesive 7. By being joined by the insulating adhesive 7, the insulation between the insulating substrate 2 and the case 6 is ensured, and the gap between the insulating substrate 2 and the case 6 is eliminated, and the sealing material 10 leaks outside through the gap. Is preventing.

ケース６は、内面６ｄの高さ方向の途中に内側へ突き出た段差部６ｄａを有している。段差部６ｄａを有していることにより、ケース６の上端部６ａにおける当該ケース６の厚さ、すなわちケース６の内面６ｄと外面６ｅとの間の距離よりも、この段差部６ｄａにおける当該ケース６の厚さが厚くなっている。この段差部６ｄａには、銅板よりなるリード８の一端部が露出して取り付けられている。ケース６の内面６ｄの段差部６ｄａに露出しているリード８の一端は、ボンディングワイヤ９によって絶縁基板２の金属箔２ｃ又は半導体チップ３の電極と電気的に接続されている。   The case 6 has a stepped portion 6da protruding inward in the middle of the inner surface 6d in the height direction. By having the step portion 6da, the thickness of the case 6 at the upper end portion 6a of the case 6, that is, the distance between the inner surface 6d of the case 6 and the outer surface 6e, the case 6 in the step portion 6da. The thickness of is increased. One end of a lead 8 made of a copper plate is exposed and attached to the stepped portion 6da. One end of the lead 8 exposed at the step portion 6da of the inner surface 6d of the case 6 is electrically connected to the metal foil 2c of the insulating substrate 2 or the electrode of the semiconductor chip 3 by the bonding wire 9.

リード８とケース６とは、インサート成型により一体的に成形されている。リード８は、ケース６の厚み方向に延在し、他の一端部がケース６の外面６ｅよりも外方に現れている。   The lead 8 and the case 6 are integrally formed by insert molding. The lead 8 extends in the thickness direction of the case 6, and the other end portion appears outside the outer surface 6 e of the case 6.

ケース６の内部空間には、半導体チップ３等の部材を封止するための封止材１０が充填されている。封止材１０には、シリコーンを主成分とするゲル状の封止材やエポキシ樹脂等の熱硬化性樹脂よりなる封止材がある。これらの封止材１０のうち、熱硬化性樹脂よりなる封止材は絶縁性が高く、耐熱性が高いので好ましく、本実施形態では封止材１０に熱硬化性樹脂、より具体的にはエポキシ樹脂を用いている。もっともゲル状の封止材を排除するものではない。封止材１０は、固化前の液状の封止材１０をケース６の上端部６ａの開口から内部空間に注入し、加熱することにより固化することにより半導体チップ３やボンディングワイヤ９等を封止する。   An internal space of the case 6 is filled with a sealing material 10 for sealing a member such as the semiconductor chip 3. The sealing material 10 includes a sealing material made of a thermosetting resin such as a gel-like sealing material mainly composed of silicone or an epoxy resin. Among these sealing materials 10, a sealing material made of a thermosetting resin is preferable because it has high insulation and high heat resistance, and in this embodiment, the sealing material 10 is a thermosetting resin, more specifically. Epoxy resin is used. However, it does not exclude the gel-like sealing material. The sealing material 10 seals the semiconductor chip 3, the bonding wire 9, etc. by injecting the liquid sealing material 10 before solidification into the internal space from the opening of the upper end portion 6 a of the case 6 and solidifying by heating. To do.

封止材１０の注入量は、ボンディングワイヤ９の絶縁性を確保するために、封止材１０がボンディングワイヤ９を十分に覆うことができるような高さ、具体的には、ボンディングワイヤ９が少なくとも１ｍｍ覆われるような高さになるように注入される。一方、ケース６は、小型化、薄型化のために、絶縁性に支障がない範囲で可能な限り薄い高さを有している。そこで、封止材１０は、ケース６内での高さが、ケース６の上面６ｃ近傍になるような所定量で注入される。   The injection amount of the sealing material 10 is set to such a height that the sealing material 10 can sufficiently cover the bonding wire 9 in order to ensure the insulation of the bonding wire 9. Injected to a height that covers at least 1 mm. On the other hand, the case 6 has a height that is as thin as possible within a range that does not hinder the insulation properties in order to reduce the size and the thickness. Therefore, the sealing material 10 is injected in a predetermined amount such that the height in the case 6 is in the vicinity of the upper surface 6 c of the case 6.

封止材１０を注入する時の当該封止材の流動，又は注入後に搬送される時の振動により、封止材１０がケース６の上面６ｃに乗り上げたとしても外観不良とならないように、本実施形態のパワー半導体モジュール１は、ケース６の上面６ｃに部分的な突起部６ｆを有している。   In order that the appearance of the sealing material 10 does not deteriorate even if the sealing material 10 rides on the upper surface 6c of the case 6 due to the flow of the sealing material when the sealing material 10 is injected or the vibration when the sealing material 10 is conveyed after the injection. The power semiconductor module 1 of the embodiment has a partial protrusion 6 f on the upper surface 6 c of the case 6.

この突起部６ｆの平面形状について図２の平面図を用いて説明する。なお図２において、本考案の理解を容易にするために半導体チップ３、コンデンサチップ５、ボンディングワイヤ９、封止材１０の記載を省略している。本実施形態のパワー半導体モジュール１において、突起部６ｆは、ケース６の一つの角部においてケースの長手方向及び短手方向に沿って当該角部に隣接する位置にそれぞれ一つずつ離れて形成されている。ケース６は４つの角部を有するため合計８個の突起部６ｆが形成されている。   The planar shape of the projection 6f will be described with reference to the plan view of FIG. 2, illustration of the semiconductor chip 3, the capacitor chip 5, the bonding wire 9, and the sealing material 10 is omitted for easy understanding of the present invention. In the power semiconductor module 1 of the present embodiment, the protrusion 6f is formed at one corner of the case 6 at a position adjacent to the corner along the long and short sides of the case. ing. Since the case 6 has four corners, a total of eight protrusions 6f are formed.

図３、図４を用いて本実施形態のパワー半導体モジュール１の作用効果について説明する。図３は、ケース６の上面６ｃに封止材１０が乗り上げた場合の状況を示す断面図であり、図４は、ケース６の上面６ｃに封止材１０が乗り上げた場合の状況を示す平面的な部分模式図である。封止材１０の注入時、又は封止材１０が注入された後であって固化前の搬送時に、ケース６の上面６ｃに封止材１０が乗り上げた場合であっても、封止材１０は、突起部６ｆの側面に回り込み上面には乗り上げない。したがって、本実施形態のパワー半導体モジュール１は、外観不良にならない。また、封止材１０を注入するときの作業性を向上させることができる。   The effect of the power semiconductor module 1 of this embodiment is demonstrated using FIG. 3, FIG. 3 is a cross-sectional view showing a situation when the sealing material 10 rides on the upper surface 6 c of the case 6, and FIG. 4 is a plan view showing a situation when the sealing material 10 rides on the upper surface 6 c of the case 6. It is a typical partial schematic diagram. Even when the sealing material 10 rides on the upper surface 6c of the case 6 during the injection of the sealing material 10 or after the injection of the sealing material 10 and before the solidification, the sealing material 10 Goes around the side surface of the protrusion 6f and does not ride on the upper surface. Therefore, the power semiconductor module 1 of the present embodiment does not have a poor appearance. Moreover, workability | operativity when inject | pouring the sealing material 10 can be improved.

更に、ケース６の上面６ｃに封止材１０が乗り上げた場合であっても、封止材１０は、突起部６ｆには乗り上げないことから、本実施形態のパワー半導体モジュール１は、図５に蓋１１を取り付けた場合の斜視図を示すように、蓋１１を接着固定するときの接着性の低下を招くことはない。   Further, even when the sealing material 10 rides on the upper surface 6c of the case 6, the sealing material 10 does not run on the protrusion 6f. Therefore, the power semiconductor module 1 of this embodiment is shown in FIG. As shown in the perspective view when the lid 11 is attached, the adhesiveness is not lowered when the lid 11 is bonded and fixed.

本実施形態のパワー半導体モジュール１において、突起部６ｆの数は、蓋１１を平坦に支持できるという観点から、最低３個があればよい。もっとも、ケース６の寸法精度や突起部６ｆの高さの精度を考慮すると、確実に支持できるように図２に示したように角部に隣接しケース長手方向及び短手方向に沿ったそれぞれに突起部６ｆを有することが好ましい。   In the power semiconductor module 1 of this embodiment, the number of the protrusions 6f may be at least three from the viewpoint that the lid 11 can be supported flat. However, in consideration of the dimensional accuracy of the case 6 and the accuracy of the height of the protrusion 6f, as shown in FIG. 2, adjacent to the corners and along the longitudinal and short sides of the case so as to be surely supported. It is preferable to have a protrusion 6f.

また、突起部６ｆの位置は、ボンディングワイヤ９をワイヤボンディングする際に、押さえ治具と干渉しない位置とすることが望ましい。   Further, it is desirable that the position of the protrusion 6f be a position that does not interfere with the pressing jig when the bonding wire 9 is wire-bonded.

ケース６の上面６ｃからの突起部６ｆの高さは、封止材１０が上面に乗り上げた場合であっても突起部６ｆには乗り上げない高さとして、０．１〜１ｍｍ程度あれば十分である。考案者らによる検証の結果、封止材１０がケース６の上面６ｃに乗り上げた場合に、そのケース６上面６ｃにおける封止材１０の厚さは３０〜８０μｍ程度であった。したがって突起部６ｆの高さが０．１ｍｍ程度以上であれば突起部６ｆ上に封止材１０が乗り上げることを回避できる。また、突起部６ｆの高さが１ｍｍ程度を超えると、ケース６の高さを薄型化することへの寄与が薄れる。   The height of the protrusion 6f from the upper surface 6c of the case 6 is sufficient if it is about 0.1 to 1 mm as a height that does not ride on the protrusion 6f even when the sealing material 10 rides on the upper surface. is there. As a result of verification by the inventors, when the sealing material 10 rides on the upper surface 6c of the case 6, the thickness of the sealing material 10 on the upper surface 6c of the case 6 is about 30 to 80 μm. Therefore, if the height of the protruding portion 6f is about 0.1 mm or more, the sealing material 10 can be prevented from riding on the protruding portion 6f. Moreover, when the height of the protrusion 6f exceeds about 1 mm, the contribution to reducing the height of the case 6 is reduced.

ケース６は、図１に示したように上端部６ａの厚さに比べて段差部６ｄａよりも下方の厚さが大きい形状を有している。このため、ケース６を金型で成型し、常温まで温度を下げたときに、ケース６の上端部６ａと下端部６ｂとで熱収縮量が異なる。その結果、ケース６は、必然的に長手方向中央が凸になるような反った形状を有している。この反り量は、ケースの寸法にもよるがケースの長手方向端部に比べて中央部で０．１ｍｍ程度高くなる。   As shown in FIG. 1, the case 6 has a shape in which the thickness below the step portion 6da is larger than the thickness of the upper end portion 6a. For this reason, when the case 6 is molded with a mold and the temperature is lowered to room temperature, the amount of heat shrinkage differs between the upper end 6a and the lower end 6b of the case 6. As a result, the case 6 inevitably has a warped shape such that the center in the longitudinal direction is convex. The amount of warpage is about 0.1 mm higher at the center than at the longitudinal end of the case, although it depends on the case dimensions.

このようなケース６の反りを考慮すれば、突起部６ｆは、ケース６の上面６ｃの長手方向端部近傍に設けることが、蓋１１を平坦に支持するのが容易になり、接着性を向上させることから好ましい。   Considering such warping of the case 6, it is easy to support the lid 11 flatly by providing the protrusion 6f in the vicinity of the end in the longitudinal direction of the upper surface 6c of the case 6, thereby improving the adhesiveness. Is preferable.

また、ケース６の反りを考慮して、ケース６の上面６ｃの長手方向端部近傍に設けた突起部６ｆの高さを、ケース６の上面６ｃの長手方向中央部寄りに設けた突起部６ｆの高さよりも、相対的に高くすることも、蓋１１を平坦に支持するのが容易になり、接着性を向上させることから好ましい。   In consideration of the warping of the case 6, the height of the protrusion 6f provided in the vicinity of the longitudinal end portion of the upper surface 6c of the case 6 is set to be closer to the longitudinal center of the upper surface 6c of the case 6. It is also preferable that the height of the lid 11 is relatively higher than the height, because it is easy to support the lid 11 flatly and the adhesiveness is improved.

本実施形態のパワー半導体モジュール１は、蓋１１の代わりに図示しない平板がケース６上に載置され、この平板上に他の部品を搭載して積層するのに利用することができる。平板上に他の部品を搭載して積層すれば、高密度実装が可能になる。平板がケース６上に載置される場合、従来のパワー半導体モジュールでは封止材がケース６の上面６ｃに乗り上げると、平板の平坦性、ケース６の上面６ｃとの平行性が確保し難いのに対して、本実施形態のパワー半導体モジュール１は封止材がケース６の上面６ｃに乗り上げたとしても、平板を突起部６ｆで支持するから、平板の平坦性、ケース６の上面６ｃとの平行性を確保できるという効果を有する。   In the power semiconductor module 1 of this embodiment, a flat plate (not shown) is placed on the case 6 instead of the lid 11 and can be used for mounting and stacking other components on the flat plate. If other components are mounted and stacked on a flat plate, high-density mounting becomes possible. When the flat plate is placed on the case 6, in the conventional power semiconductor module, when the sealing material runs on the upper surface 6 c of the case 6, it is difficult to ensure flatness of the flat plate and parallelism with the upper surface 6 c of the case 6. On the other hand, since the power semiconductor module 1 of the present embodiment supports the flat plate with the protrusion 6f even if the sealing material rides on the upper surface 6c of the case 6, the flatness of the flat plate and the upper surface 6c of the case 6 This has the effect of ensuring parallelism.

また平板がケース６上に載置されたパワー半導体モジュール１は、平板の上方にばねが設けられ、ばねの付勢力によりパワー半導体モジュール１の金属基板２ａを、当該金属基板２ａと接する放熱フィンに対して押し付け固定し、これにより、金属基板２ａと放熱フィンとの良好な接触性を確保し、よって放熱性を向上させる構造に用いることができる。この場合もパワー半導体モジュール１は、平板の平坦性、ケース６の上面６ｃとの平行性を確保できるという効果を有する。   Moreover, the power semiconductor module 1 in which the flat plate is placed on the case 6 is provided with a spring above the flat plate, and the metal substrate 2a of the power semiconductor module 1 is radiated by the urging force of the spring to the radiating fin in contact with the metal substrate 2a. It can be pressed against and fixed to the metal substrate 2a, thereby ensuring good contact between the metal substrate 2a and the heat radiating fins, thereby improving the heat radiability. Also in this case, the power semiconductor module 1 has an effect that flatness of the flat plate and parallelism with the upper surface 6c of the case 6 can be ensured.

ケース６の突起部の変形例について、図６及び図７の平面図を用いて説明する。
図６に示す変形例の半導体装置２１において、ケース６の上面６ｃが厚さ方向に二分され、外面６ｅ側が内面６ｄ側よりも高さが高い、突起部６ｇとなっている。この突起部６ｇは、ケース６の上面６ｃの長手方向中央部には形成されていない。ケース６の上面６ｃの長手方向中央部にこの突起部６ｇが形成されていないことにより、上述したケース６の反りに対して。蓋１１を平坦に支持するのが容易になり、接着性を向上させている。 A modification of the protruding portion of the case 6 will be described with reference to the plan views of FIGS.
In the semiconductor device 21 of the modification shown in FIG. 6, the upper surface 6c of the case 6 is divided into two in the thickness direction, and the outer surface 6e side is a protruding portion 6g that is higher than the inner surface 6d side. The protrusion 6g is not formed at the longitudinal center of the upper surface 6c of the case 6. The protrusion 6g is not formed at the longitudinal central portion of the upper surface 6c of the case 6, thereby preventing the case 6 from warping. It is easy to support the lid 11 flatly, and the adhesiveness is improved.

図７に示す変形例の半導体装置３１において、突起部６ｈは、図２に示した突起部６ｆと比べて、ケース６の上面６ｃ上における位置はほぼ同じであり、各突起部６ｈの厚さが、厚さ方向で二分の一になり、ケース６の外面６ｅ側に突起部６ｈが形成されている。   In the semiconductor device 31 of the modified example shown in FIG. 7, the position of the protrusion 6h on the upper surface 6c of the case 6 is substantially the same as that of the protrusion 6f shown in FIG. However, it is halved in the thickness direction, and a protrusion 6 h is formed on the outer surface 6 e side of the case 6.

図６に示した突起部６ｇ及び図７に示した突起部６ｈは、図２に示した突起部６ｆとは突起の形状が異なるが、突起の高さは図２に示した突起部６ｆと同様とすることができる。また、ケース６の反りを考慮して、ケース６の上面６ｃの長手方向端部近傍に設けた突起部６ｇ、６ｈの高さを、ケース６の上面６ｃの長手方向中央部寄りに設けた突起部６ｇ、６ｈの高さよりも、相対的に高くすることもできる。   The protrusion 6g shown in FIG. 6 and the protrusion 6h shown in FIG. 7 are different in protrusion shape from the protrusion 6f shown in FIG. 2, but the height of the protrusion is the same as that of the protrusion 6f shown in FIG. The same can be said. Further, in consideration of the warp of the case 6, the protrusions 6 g and 6 h provided in the vicinity of the longitudinal end portion of the upper surface 6 c of the case 6 are provided closer to the longitudinal center of the upper surface 6 c of the case 6. It can also be made relatively higher than the height of the parts 6g and 6h.

図６に示した変形例の作用効果を、図８を用いて説明し、図７に示した変形例の作用効果を、図９を用いて説明する。図８、図９は、これらの変形例の場合に、ケース６の上面６ｃに封止材１０が乗り上げた場合の状況を示す平面的な模式図である。   The operational effects of the modification shown in FIG. 6 will be described with reference to FIG. 8, and the operational effects of the modification shown in FIG. 7 will be described with reference to FIG. FIG. 8 and FIG. 9 are schematic plan views showing the situation when the sealing material 10 rides on the upper surface 6c of the case 6 in the case of these modified examples.

図８、図９から分かるように、突起部６ｇ、６ｈの厚さがケース６の上面６ｃの厚さを分割した厚さに相当し、薄いので、封止材１０の注入時、又は封止材１０が注入された後であって固化前の搬送時に、ケース６の上面６ｃに封止材１０が乗り上げた場合であっても、封止材１０は、突起部６ｇ、６ｈの側面に回り込み上面には乗り上げない。したがって、本実施形態のパワー半導体モジュール１は、外観不良にならない。また、封止材１０を注入するときの作業性を向上させることができる。   As can be seen from FIGS. 8 and 9, the thickness of the protrusions 6 g and 6 h corresponds to the thickness obtained by dividing the thickness of the upper surface 6 c of the case 6 and is thin. Even when the sealing material 10 rides on the upper surface 6c of the case 6 after the injection of the material 10 and before the solidification, the sealing material 10 wraps around the side surfaces of the protrusions 6g and 6h. Do not ride on top. Therefore, the power semiconductor module 1 of the present embodiment does not have a poor appearance. Moreover, workability | operativity when inject | pouring the sealing material 10 can be improved.

更に、ケース６の上面６ｃに封止材１０が乗り上げた場合であっても、封止材１０は、突起部６ｇ、６ｈには乗り上げないことから、蓋１１を接着固定するときの接着性の低下を招くことはない。   Further, even when the sealing material 10 rides on the upper surface 6c of the case 6, the sealing material 10 does not run on the protrusions 6g and 6h. There will be no decline.

ケース６の突起部の参考例について、図１０の平面図を用いて説明する。
図１０に示す参考例のパワー半導体モジュール１１１は、図６に示した変形例と近似の突起部１０６ｇを有している。突起部１０６ｇは、ケース６の上面６ｃが厚さ方向に二分され、外面６ｅ側が内面６ｄ側よりも高さが高い、突起部１０６ｇとなっている。この突起部１０６ｇが、ケース６の上面６ｃ上において、全周にわたって形成されている点で、図６に示した突起部６ｇと相違している。図１０に示す参考例の突起部１０６ｇは、上述したように反りが生じているケース６に対して。蓋１１を平坦に支持することが、図６に示した変形例に比べると難しくなり、接着性の向上が少ない。 A reference example of the protrusion of the case 6 will be described with reference to the plan view of FIG.
The power semiconductor module 111 of the reference example shown in FIG. 10 has a protrusion 106g that is similar to the modification shown in FIG. The protrusion 106g is a protrusion 106g in which the upper surface 6c of the case 6 is divided into two in the thickness direction, and the outer surface 6e side is higher than the inner surface 6d side. The protruding portion 106g is different from the protruding portion 6g shown in FIG. 6 in that the protruding portion 106g is formed over the entire circumference on the upper surface 6c of the case 6. The protrusion 106g of the reference example shown in FIG. 10 is for the case 6 in which the warp occurs as described above. It is difficult to support the lid 11 flat compared to the modification shown in FIG. 6, and the improvement in adhesion is small.

比較例として図１１に示した断面図を用いて従来のパワー半導体モジュール１０１を説明する。なお図１１において、図１に示したパワー半導体モジュール１と同一の部材については同一の符号を付しており、以下では重複する説明を省略する。   As a comparative example, a conventional power semiconductor module 101 will be described using the cross-sectional view shown in FIG. In FIG. 11, the same members as those in the power semiconductor module 1 shown in FIG.

図１１に示した従来のパワー半導体モジュール１０１が、図１に示した本考案の実施形態のパワー半導体モジュール１と相違する点は、半導体チップ３が搭載された絶縁基板２の周縁にケース１０６が取り付けられている点である。このケース１０６は、図１に示した本考案の実施形態のパワー半導体モジュール１のケース６に形成された突起部６ｆを有しない点でケース６とは相違し、他の構成は同一である。   The conventional power semiconductor module 101 shown in FIG. 11 is different from the power semiconductor module 1 of the embodiment of the present invention shown in FIG. 1 in that a case 106 is provided on the periphery of the insulating substrate 2 on which the semiconductor chip 3 is mounted. It is a point attached. The case 106 is different from the case 6 in that the case 106 does not have the protrusion 6f formed in the case 6 of the power semiconductor module 1 of the embodiment of the present invention shown in FIG. 1, and the other configurations are the same.

かかる従来の半導体モジュール１０１のケース１０６の内部空間に封止材１０を注入し、ケース１０６の上面に封止材１０が乗り上げた状況を断面図で図１２に示し、平面的な部分模式図で図１３に示す。図１２、１３に示すように、ケース１０６の上面に封止材１０６が乗り上げると、蓋１１を乗せた場合にその蓋１１が平坦になるように支持されず、接着固定するときの接着性が劣り、また、外観不良であった。   FIG. 12 is a sectional view showing a state in which the sealing material 10 is injected into the internal space of the case 106 of the conventional semiconductor module 101 and the sealing material 10 rides on the upper surface of the case 106. As shown in FIG. As shown in FIGS. 12 and 13, when the sealing material 106 rides on the upper surface of the case 106, when the lid 11 is placed, the lid 11 is not supported so as to be flat, and the adhesiveness when bonding and fixing is improved. It was inferior and the appearance was poor.

１ パワー半導体モジュール
２ 絶縁基板
３ 半導体チップ
４ はんだ
５ コンデンサチップ
６ ケース
６ｃ 上面
６ｆ 突起部
６ｇ 突起部
６ｈ 突起部
７ 絶縁性接着剤
８ リード
９ ボンディングワイヤ
１０ 封止材
１１ 蓋 DESCRIPTION OF SYMBOLS 1 Power semiconductor module 2 Insulation board | substrate 3 Semiconductor chip 4 Solder 5 Capacitor chip 6 Case 6c Upper surface 6f Projection part 6g Projection part 6h Projection part 7 Insulating adhesive 8 Lead 9 Bonding wire 10 Sealing material 11 Cover

Claims (11)

絶縁基板と、
該絶縁基板上に搭載された半導体素子と、
該絶縁基板の周縁を囲い、該半導体素子を収容する中空のケースと、
該ケース内に充填され、該ケース内を封止する封止材と
を備え、かつ
該ケースが、該ケースの上面から部分的に突出する突起部を有することを特徴とする半導体装置。 An insulating substrate;
A semiconductor element mounted on the insulating substrate;
A hollow case surrounding the periphery of the insulating substrate and containing the semiconductor element;
A semiconductor device comprising: a sealing material which is filled in the case and seals the inside of the case; and the case has a protrusion partly protruding from an upper surface of the case. 前記ケースが箱型形状を有し、前記突起部が、該ケースの上面の角部近傍に形成されている請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the case has a box shape, and the protrusion is formed in the vicinity of a corner of the upper surface of the case. 前記突起部が、前記ケースの上面の厚さを分割した厚さを有する請求項１又は２記載の半導体装置。   The semiconductor device according to claim 1, wherein the protrusion has a thickness obtained by dividing a thickness of an upper surface of the case. 前記ケースの長手方向端部近傍に形成された前記突起部は、前記ケースの長手方向中央部近傍に形成された前記突起部よりも、前記上面からの高さが高い請求項１〜３のいずれか1項に記載の半導体装置。   The height of the protrusion formed in the vicinity of the longitudinal end portion of the case from the upper surface is higher than that of the protrusion formed in the vicinity of the central portion of the case in the longitudinal direction. 2. The semiconductor device according to claim 1. 前記ケース内面に、該ケースの厚さが大きい段差部を備え、該段差部にケース内から外方に延出する導電部材の一端部が設けられている請求項１〜４記載のいずれか１項に記載の半導体装置。   5. The method according to claim 1, further comprising: a step portion having a large thickness of the case on the inner surface of the case, wherein the step portion is provided with one end portion of a conductive member extending outward from the case. The semiconductor device according to item. 前記導電部材が銅板よりなるリードであり、該リードに接続するボンディングワイヤを更に備える請求項５記載の半導体装置。   The semiconductor device according to claim 5, wherein the conductive member is a lead made of a copper plate, and further includes a bonding wire connected to the lead. 前記ケースを覆う蓋を更に備える請求項１〜６のいずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, further comprising a lid that covers the case. 前記ケース上に載置される平板を更に備える請求項１〜６のいずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, further comprising a flat plate placed on the case. 絶縁基板の周縁を囲い、半導体素子を収容し、封止材が充填される中空のケースであって、
該ケースの上面から部分的に突出する突起部を有することを特徴とする半導体装置用ケース。 A hollow case that surrounds the periphery of the insulating substrate, accommodates semiconductor elements, and is filled with a sealing material,
A semiconductor device case having a protrusion partly protruding from an upper surface of the case. 箱型形状を有し、前記突起部が、前記ケースの上面の角部近傍に形成されている請求項９記載の半導体装置用ケース。   The semiconductor device case according to claim 9, wherein the case has a box shape, and the protrusion is formed in the vicinity of a corner of the upper surface of the case. 前記突起部が、前記ケースの上面の厚さを分割した厚さを有する請求項９又は１０記載の半導体装置用ケース。   11. The semiconductor device case according to claim 9, wherein the protrusion has a thickness obtained by dividing a thickness of an upper surface of the case.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016096188A (en) * 2014-11-12 2016-05-26 富士電機株式会社 Semiconductor device
JP2016100475A (en) * 2014-11-21 2016-05-30 富士電機株式会社 Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016096188A (en) * 2014-11-12 2016-05-26 富士電機株式会社 Semiconductor device
JP2016100475A (en) * 2014-11-21 2016-05-30 富士電機株式会社 Semiconductor device
US9502320B2 (en) 2014-11-21 2016-11-22 Fuji Electric Co., Ltd. Semiconductor device

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