JP3190846B2 - Asynchronous readout circuit of binary counter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asynchronous readout circuit for a binary counter, and more particularly to a circuit for reading out the count data of a binary counter at a timing asynchronous with the count increment.

[0002]

2. Description of the Related Art When performing a counting process in a logic circuit,
Often a binary counter is used. In many cases, the timing of reading the count value (count data) of the binary counter is asynchronous with the timing for counting up the count value. The prior art of this asynchronous read will be described with reference to FIGS. FIG. 6 is a configuration diagram of a conventional circuit for asynchronously reading a count value from a binary counter. In a conventional asynchronous reading circuit for reading the count value of a binary counter of this type, a binary counter unit 1 performs a counting process by a counting clock Sa and outputs binary count data Sc. A data sampling unit 32 that samples the binary count data Sc with a count value read signal Sb that is asynchronous with the count clock Sa,
The binary read data Sg was output.

Here, a case of a 4-bit binary counter will be described as an example. Table 1 below (in the embodiment section)
Shows the Hamming distance when the 4-bit counter counts up from "0000" to "1111". For example, when the value of the counter is counted up from “7” to “8”, the bit string (binary code) is “011”.
The number of changes is “1” to “1000” and the number of changes is “4.” As described above, since the output of the n-bit binary counter advances with the hamming distance of “1” to “n” (n is an integer), There is a timing at which a value different from the counting process is read.

This will be described in detail with reference to a timing chart of FIG. The data Sc (b0 to b3) output from the binary counter unit 1 is sampled at the rising point of the count value read signal Sb (points P1 and P2). When sampling at point P1, the binary counter is counting up from "3" to "4" at the moment. That is, b0 and b1 change from "1" to "0", and b2 changes from "0" to "1". There are three bits that change, and each bit changes at different timings (time and time width) due to variations in the elements that constitute the circuit.
, The sampling is performed at different midpoints of change for each bit, and thus the sampled data is one of eight data of “0”, “1”,. May be one of the following values: Point P
When sampling at 2, the binary counter is counting up from "7" to "8" at the moment. That is, b
Since 0, b1, and b2 change from “0” to “1” and b3 changes from “1” to “0”, and there are four changing bits, the sampled data is “0”, “1”, “ 2 ",
“3”,..., “C (12)”, “D (13)”,
There is a possibility that any one of the 16 values of “E (14)” and “F (15)” will be obtained.

[0005]

In the above-mentioned conventional asynchronous readout circuit of the count value from the binary counter, the output of the binary counter which progresses at a hamming distance of 1 to n is sampled and read as it is. In some cases, a value significantly different from the counting process in the counter is read (in the worst case, there is an error of half of the maximum countable value), and the reliability of the read count value decreases.

[0006]

An asynchronous readout circuit for a binary counter according to the present invention is a circuit for reading out the count data of a binary counter at a timing asynchronous with the count increment. Encoding means for converting the data into codes;
Invert method to invert the logical value of the most significant bit data
And the highest order of the conversion output data of the encoding means at the read designation timing of the binary counter.
Read the remaining bit data excluding the bit data of
Together with the inverted bit data as the most significant bit data.
Sampling means for reading the output data of the unit, the data to which the sampling means is read from the gray code is inversely converted into a binary code, the binary counter
Decoding means for outputting as count data read from the binary counter corresponding to the case where the count stepping direction is reversed .

[0007]

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a bag used in the present invention will be described.
By converting between Inari code and Gray code,
Incorrect count value in asynchronous reading of the nally counter
The principle by which the difference can be made ± 1 or less will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the principle of the present invention. The readout circuit of this example performs a counting process (counting increment) by a counting clock Sa and outputs binary count (count) data Sc. The binary counter data Sc output by the binary counter unit 1 is grayed out. An encoding unit 2 that outputs coded gray code count data Sd; and a data sampling unit that samples the gray code count data Sd output from the encode unit 2 at the timing of the count value read signal Sb and outputs gray code read data Se. And a decoding unit 4 that converts the gray code read data Se output from the data sampling unit 3 into binary data and outputs binary read data Sf. Table 1 shows the hamming distance when the binary counter counts up and the hamming distance of the gray-coded binary count data as an example of 4-bit data.

[0010]

[Table 1]

FIGS. 2 and 3 show a detailed configuration example of the encoding unit 2 and the decoding unit 4 for converting between a binary code and a Gray code as shown in Table 1.
Each of the logic circuit elements used in FIGS. 2 and 3 performs an exclusive OR operation. The data sampling unit 3 has a flip-flop corresponding to a bit, and latches input data at the rise of the count value read signal Sb.

Next, the operation will be described. Counting clock Sa
Accordingly, the binary counter unit 1 performs a counting process (binary counting) and outputs binary count data Sc.
In response to the input of the binary count data Sc output from the binary counter unit 1, the encoding unit 2 performs gray code conversion and outputs gray code count data Sd. The data sampling unit 3 receives the timing (the counting clock S) of the count value read signal Sb at an arbitrary timing from outside.
a), the gray code count data Sd is sampled, and a gray code read signal Se is output.

At this time, even if the timing of the count value read signal Sb coincides with the rewrite timing of the value of the encoding unit 2 corresponding to the change in the count value of the binary counter unit 1, the gray code count data before the rewrite and the gray code count data after the rewrite The Hamming distance between the gray code count data is
It is always 1 regardless of the value of the binary counter unit 1. A Hamming distance of one means that only one bit changes. For this reason, even if there is a variation in the level change time among the elements constituting the circuit, the value read by the data sampling unit 3 as the gray code count data is either the value before rewriting or the value after rewriting. Yes, no other values.
That is, the reading error is ± 1 or less. For example, when the count value of the binary counter is counted up from 7 to 8, that is, when the binary data is counted up from “0111” to “1000”, according to Table 1, the output of the binary counter indicates that the hamming distance is 4 , Gray coding, the Hamming distance is always 1, and the data of the binary counter can be sampled with an error of ± 1. This will be described in detail below with reference to the timing chart of FIG.

For example, when sampling at the point P1, when the output Sc of the counting counter unit 1 changes from "3" to "4", the value Sd output from the encoding unit 2 changes from "2" to "6". Changes to The change at this time is only the third bit. Therefore, when the output data from the encoding unit 2 is sampled at the point P1, the sampled data Se is either “2” or “6”. The sampling unit 4 decodes the sampled data Se.
, The output data Sf becomes “3” and “4” for the input data “2” and “6”. That is, the reading error of the binary counter is ± 1.

Subsequently, the decoding unit 4 converts the gray code read data Se output from the data sampling unit 3 into binary data, and outputs binary read data Sf of the count value (Sc) ± 1 of the binary counter unit 1.

Next, an embodiment of the present invention will be described with reference to FIG. The circuit of FIG. 4 uses the principle of reading error reduction.
In the circuit of FIG. 1 used to explain the above, an inverting unit 5 for inverting the logical level is provided between the encoding unit 2 and the data sampling unit 3, and the most significant bit of the gray code count data output from the encoding unit 2 is provided. Sd2 is input to the inverting unit 5, and inverted data Sd3 of the most significant bit Sd2 output from the inverting unit 5 and data Sd4 other than the most significant bit of the gray code count data output from the encoding unit 2 are sent to the data sampling unit 3. Is input. Other circuits and functions are common to the circuit of FIG.

Next, the operation will be described. Counting clock Sa
Accordingly, the binary counter unit 1 performs a counting process and outputs binary count data Sc. Binary counter unit 1
Input of binary count data Sc output from
The encoding unit 2 performs Gray coding, and outputs the most significant bit Sd2 of the gray code count data and all data Sd4 excluding the most significant bit of the gray code count data. The inverting unit 5 inverts the most significant data Sd2 of the gray code count data and outputs the gray code counted most inverted data Sd3. Data sampling unit 3
Is a count reading signal S at an arbitrary timing from outside
At timing b, the gray code counting uppermost inverted data Sd3 and all data Sd4 excluding the uppermost bit of the gray code counting data are sampled, and a gray code read signal Se2 is output.

Here, in the data sampling unit 3, even if the sampling timing coincides with the rewriting timing of the value of the encoding unit 2 corresponding to the change in the count value of the binary counter unit 1, the gray code count data before rewriting and the gray code count data after rewriting. The Hamming distance from the gray code count data is always 1 irrespective of the value of the binary counter 1, and the error of the gray code read signal Se2 is ±
1 or less. Furthermore, since the most significant bit of the gray code count data is inverted, the binary data in Table 1 and the gray code conversion table indicate that the binary data is from “0000” to “0111” and from “1000” to “1111”.
Up to this point is vertically symmetric. That is, the binary up counter is changed to the binary down counter only by inverting the gray code counting top data.

For example, if the binary counter 1 is "000"
The case of counting up from “0” to “0001” is described below: First, the data of the binary counter is set to “000”.
When it is "0", the gray code counting uppermost data Sd2 output from the encoder 2 is "0", and the gray code counting data Sd4 excluding the uppermost is "000" to "001".
Changes to

Here, the gray code counting uppermost inverted data Sd3 input to the data sampling section 3 is inverted from “0” to “1”. That is, the data of the gray-coded binary counter is "1000". In the data sampling unit 3, the gray code read data Se2 sampled by the count value read signal Sb becomes “1000”. The decoding unit 4 changes the gray code into binary data.
Gray code read data S
When e2 is "1000" , binary read data
Sf2 becomes “1111”. Similarly, when the binary counter data counts up to “0001”,
The gray code read data Se2 becomes “1001” and the binary read data Sf2 becomes “1110” from the binary code-Gray code conversion of Table 1. This means that the initial value changes from “1111” to “1110”,
Indicates that it is counting down.

[0021]

The present invention described above, according to the present invention includes encoding means for grayed ray encode binary count data of the binary counter, the sampled gray code read at the timing of the signal output reads gray code count data Sampling that outputs data
It has a grayed means and decoding means for outputting the gray code read data as the inverse transformation to binary read data into binary code data. The Hamming distance between two codes before and after sampling of Gray code data is
It is always 1 irrespective of the value of the count data of the binary counter, and the gray code data is ± 1 error regardless of the time relationship between the timing of the read signal and the count increment timing of the binary counter. Since sampling can be performed, binary code data obtained by inversely converting gray code data after sampling, that is, count data of a binary counter can be output with an error of ± 1. Further, in addition to the above configuration, the present invention
Logic of the most significant bit data of the output data of
Invert hand to invert and then input to sampling means
It has a step. This allows the output from the decoding means to be
The binary count of the count data
Of the count data in the counter
With the direction, the prior art is the problem, the Hamming distance in the binary counter is 1 to n (n is the number of counter bits) different value from the count value of the binary counter by proceeding in (error ± 2 or more, In the worst case, there is an effect of eliminating the timing at which (± half the maximum count value) is read.

[Brief description of the drawings]

FIG. 1 illustrates the principle of reading error reduction according to the present invention.
It is a block diagram for performing.

FIG. 2 is a block diagram illustrating a detailed configuration of an encoding unit in FIG. 1;

FIG. 3 is a block diagram illustrating a detailed configuration of a decoding unit in FIG. 1;

FIG. 4 is a block diagram showing an embodiment of the present invention.

FIG. 5 is a diagram illustrating signal operation timings of respective units in FIG . 1 ;

FIG. 6 is a block diagram showing a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Binary counter part 2 Encoding part 3 Data sampling part 4 Decoding part 5 Invert part

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-8-149117 (JP, A) JP-A-4-217118 (JP, A) JP-A-62-179221 (JP, A) JP-A-1- 251822 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03M 7/16 H03K 23/58

Claims (1)

(57) [Claims] 1. A circuit for reading count data of a binary counter at a timing asynchronous with a count increment, wherein said encoding means converts output data of said binary counter from a binary code to a gray code, and conversion output data of said encoding means. The top
And inverting means for inverting the logic value of Ttodeta, the read designated timing of the binary counter, before
Of the conversion output data of the encoding means.
Read the remaining bit data except for the
Then, as the most significant bit data,
Sampling means for reading the output data, and inversely converted into a binary code data said sampling means is read from the gray code, the binary counter
Decoding means for outputting as the read count data from the binary counter corresponding to the case where the count increment direction of the data counter is reversed .