JP3189896B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor and a semiconductor device manufactured by the method.

[0002]

2. Description of the Related Art When forming HSG-Si (hemispherical silicon grains), the state of the back surface of a wafer has not been considered so far. When HSG-Si is formed on a wafer having an oxide film formed on the back surface of the wafer, the HSG-Si
Moisture is released from the oxide film by the heat treatment at the time of forming the -Si, an oxide film is formed on the surface of the amorphous silicon on which the HSG-Si is to be formed, and a phenomenon that the HSG-Si is not formed partially occurs.

A portion where HSG-Si is not formed has a small surface area and a small capacitance. This phenomenon becomes apparent when the HSG-Si formation area occupying the wafer surface is small, for example, in a semiconductor device such as a logic-embedded DRAM. In addition, when HSG-Si is formed by batch processing, it occurs remarkably when the number of processed wafers is large. FIG. 1 shows the difference in capacitance when the number of processed wafers is changed in batch processing. That is, when the number of processed wafers increases, the amount of water released from the back surface of the wafer increases, and a portion where HSG-Si is not formed partially increases, so that the capacity decreases. If a DRAM or the like is formed in a state where HSG-Si is not formed partially, a bit (A) having a short hold time is generated as shown in FIG. 2 and a hold failure occurs. (B) shows a normal state in which a bit having a short hold time does not occur.

[0004]

SUMMARY OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device capable of obtaining a highly reliable semiconductor device free of occurrence of bits having a short hold time and no occurrence of hold failure, and a method of manufacturing the same. It is an object to provide a semiconductor device.

[0005]

The above object is achieved by the following means. That is, the present invention proposes a method of manufacturing a semiconductor device, characterized in that hemispherical silicon is formed after silicon is formed on the back surface of the wafer. That the method of forming the silicon on the back surface of the wafer is by etching; that the method of forming the silicon on the back surface of the wafer is by polishing; the method of forming the hemispherical silicon is a first heat treatment at a predetermined atmosphere and temperature; Performing a second heat treatment in a predetermined atmosphere and temperature, performing a third heat treatment in a predetermined atmosphere and temperature, setting the first heat treatment atmosphere to a vacuum, and setting the second heat treatment atmosphere to S
iH _4, and the third heat treatment atmosphere is evacuated. The present invention also proposes a semiconductor device manufactured by the above method.

According to the present invention, since the back surface of the wafer is made of silicon, moisture is not released from the back surface of the wafer, dense HSG-Si is formed on the entire surface, and a highly reliable capacitor free of hold failure can be formed. .

It is considered that the function of the present invention is to reduce the amount of water released from the back surface by making the back surface of the wafer a silicon surface having high hydrophobicity to the oxide film.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described more specifically with reference to examples.

[0009]

(Embodiment 1) An N well 102 and a P well 103 are formed in a P type silicon substrate 101. Next, an element isolation insulating film region 104 is formed, and a gate insulating film 105 is formed. Subsequently, after the gate electrode 106 is formed, the p-type high-concentration impurity diffusion region 1 is formed by ion implantation.
07 and an n-type impurity diffusion region 108 are formed. Next, after a digit line contact hole 110 is formed in the interlayer insulating film 109, a digit line 111 is formed. Next, after an interlayer insulating film 112 is formed, a hole 113 communicating with the stack electrode is formed.
To form

Next, a P-doped amorphous silicon film 114 serving as a stack electrode is deposited by a CVD method. Next, the silicon oxide film, the silicon film, and the like formed and deposited on the back surface of the wafer are removed using an HF aqueous solution or a mixed solution of hydrofluoric acid and nitric acid. By this processing, the silicon substrate is exposed on the back surface of the wafer. Next, the P-doped amorphous silicon film 1
14 is processed into a stack electrode, and the process proceeds to an HSG-Si forming step. First, after removing the natural oxide film on the surface with an HF aqueous solution, the temperature is raised from room temperature to 580 ° C. in a vacuum, and is maintained for several minutes to several tens of minutes until the temperature is stabilized. Next, the temperature is 58
Heat treatment is performed at 0 ° C. for 15 minutes in an atmosphere of SiH ₄ at a partial pressure of 1 × 10 ⁻⁴ Torr. Subsequently, when the temperature is maintained at 580 ° C. in a vacuum for 20 minutes, hemispherical silicon grains (HSG-Si) are formed on the amorphous silicon surface, and FIG. 3 is obtained. Subsequently, the capacitance insulating film 115 and the capacitance electrode 116
To form Next, the interlayer insulating film 117 and the aluminum wiring 11
When 8 and the like are formed, FIG. 4 is obtained, and the semiconductor device is completed.

(Embodiment 2) P-type silicon substrate 101 is coated with N
A well 102 and a P well 103 are formed.

Next, an element isolation insulating film region 104 is formed,
A gate insulating film 105 is formed. Subsequently, the gate electrode 1
After the formation of the semiconductor layer 06, the p-type high concentration impurity diffusion region 107 and the n-type impurity diffusion region
To form Next, after a digit line contact hole 110 is formed in the interlayer insulating film 109, a digit line 111 is formed. Next, after forming an interlayer insulating film 112, a hole 113 communicating with the stack electrode is formed. Next, a P-doped amorphous silicon film 114 serving as a stack electrode is deposited by a CVD method. At this time, the outermost surface of the back surface of the wafer becomes amorphous silicon. Next, the P-doped amorphous silicon film 114 is processed into a stack electrode, and the process proceeds to an HSG-Si forming step.
First, after removing the natural oxide film on the surface with an HF aqueous solution, the temperature is raised from room temperature to 580 ° C. in a vacuum, and is maintained for several minutes to several tens of minutes until the temperature is stabilized. Next, heat treatment is performed for 15 minutes in an atmosphere of SiH ₄ partial pressure of 1 × 10 ⁻⁴ Torr at a temperature of 580 ° C. Subsequently, the temperature is kept at 580 ° C. in a vacuum for 2 hours.
When held for 0 minutes, hemispherical silicon grains (HSG-Si) are formed on the amorphous silicon surface, and FIG. 3 is obtained.
Subsequently, a capacitor insulating film 115 and a capacitor electrode 116 are formed. Next, when an interlayer insulating film 117, an aluminum wiring 118 and the like are formed, FIG. 4 is obtained, and the semiconductor device is completed.

(Embodiment 3) P-type silicon substrate 101 is coated with N
A well 102 and a P well 103 are formed.

Next, an element isolation insulating film region 104 is formed,
A gate insulating film 105 is formed. Subsequently, the gate electrode 1
After the formation of the semiconductor layer 06, the p-type high concentration impurity diffusion region 107 and the n-type impurity diffusion region
To form Next, after a digit line contact hole 110 is formed in the interlayer insulating film 109, a digit line 111 is formed. Next, after forming an interlayer insulating film 112, a hole 113 communicating with the stack electrode is formed. Next, a P-doped amorphous silicon film 114 serving as a stack electrode is deposited by a CVD method. Next, a silicon oxide film, a silicon film, and the like formed and deposited on the back surface of the wafer are removed by using a chemical mechanical polishing technique. At this time, the back surface of the wafer is exposed from the silicon substrate. Next, the P-doped amorphous silicon film 114 is processed into a stack electrode, and the process proceeds to an HSG-Si forming step. First, after removing the natural oxide film on the surface with an HF aqueous solution, the temperature is raised from room temperature to 580 ° C. in a vacuum, and is maintained for several minutes to several tens of minutes until the temperature is stabilized. Next, the temperature is 580 ° C
15 in an atmosphere of SiH ₄ partial pressure of 1 × 10 ^-4 Torr
Heat treatment for minutes. Subsequently, when the temperature is maintained at 580 ° C. in a vacuum for 20 minutes, hemispherical silicon grains (HSG-Si) are formed on the amorphous silicon surface, and FIG. 3 is obtained. Subsequently, a capacitor insulating film 115 and a capacitor electrode 116 are formed. Next, when an interlayer insulating film 117, an aluminum wiring 118 and the like are formed, FIG. 4 is obtained, and the semiconductor device is completed.

[0015]

According to the present invention, since the back surface of the wafer is made of silicon, the release of moisture from the back surface of the wafer is eliminated, dense HSG-Si is formed on the entire surface, and a highly reliable capacitor free from hold failure is provided. Can be formed.

[Brief description of the drawings]

FIG. 1 is a graph showing the relationship between the number of processed wafers and the capacity in batch processing.

FIG. 2 is a graph showing a relationship between a hold time and a bit generation state.

FIG. 3 is a cross-sectional view of the semiconductor device at an intermediate stage of the manufacturing process of the semiconductor device according to the invention;

FIG. 4 is a cross-sectional view of the semiconductor device of the present invention.

[Explanation of symbols]

 Reference Signs List 101 P-type silicon substrate 102 N-well 103 P-well 104 element isolation insulating region 105 gate insulating film 106 gate electrode 107 P-type high concentration impurity diffusion region 108 n-type impurity diffusion region 109 interlayer insulating film 110 digit line contact hole 111 digit line 112 Interlayer insulating film 113 hole 114P doped amorphous silicon film 115 capacitor insulating film 116 capacitor electrode 117 interlayer insulating film 118 aluminum wiring

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/108 H01L 21/205 H01L 21/822 H01L 21/8242 H01L 27/04

Claims (5)

(57) [Claims] 1. A method of manufacturing a semiconductor device using hemispherical silicon grains, wherein the hemispherical silicon grains are subjected to a heat treatment on amorphous silicon formed on a wafer surface.
In the step of forming hemispherical silicon on the surface of the amorphous silicon, in the step of forming hemispherical silicon, the back surface of the wafer is made of amorphous silicon deposited by vapor phase epitaxy as its outermost surface And performing a heat treatment for forming hemispherical silicon. 2. A method of manufacturing a semiconductor device utilizing hemispherical silicon grains, wherein the hemispherical silicon grains are subjected to a heat treatment on amorphous silicon formed on a wafer surface.
In the step of forming hemispherical silicon on the surface of the amorphous silicon, in the step of forming hemispherical silicon, the hemispherical silicon is formed in a state where silicon is exposed on the outermost surface by etching the back surface of the wafer. A method for manufacturing a semiconductor device, comprising performing a heat treatment. 3. A method of manufacturing a semiconductor device using hemispherical silicon grains, wherein the hemispherical silicon grains are subjected to heat treatment on amorphous silicon formed on a wafer surface.
In the step of forming hemispherical silicon on the surface of the amorphous silicon, in the step of forming hemispherical silicon, the backside of the wafer is polished to form hemispherical silicon with silicon exposed on the outermost surface. A method of manufacturing a semiconductor device, comprising: performing a heat treatment. 4. The heat treatment in the step of forming the hemispherical silicon includes: performing a first heat treatment at a predetermined atmosphere and temperature; performing a second heat treatment at a predetermined atmosphere and temperature; The method of manufacturing a semiconductor device according to claim 1, wherein the method is performed by performing a third heat treatment. 5. The heat treatment according to claim 4, wherein the first heat treatment atmosphere is vacuum, the second heat treatment atmosphere is SiH _4, and the third heat treatment atmosphere is vacuum. A method for manufacturing a semiconductor device.