JP3189696B2 - Semiconductor integrated circuit, semiconductor device and test method therefor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device, and more particularly to a semiconductor device suitable for a multi-chip module (hereinafter, referred to as MCM).

[0002]

2. Description of the Related Art In recent years, high integration and high speed of semiconductor integrated circuits have been realized, and semiconductor integrated circuits of systems have been accelerated, which has greatly contributed to miniaturization and cost reduction of systems. However, the capital investment required for high-speed and high-integration of semiconductor integrated circuits in the quarter-micron era is increasing, and due to the increase in circuit scale and the decrease in yield due to high integration, chipsets manufactured by the old-generation process are being used. It is becoming very difficult to secure price benefits.
Therefore, as a means for satisfying the cost reduction and the reduction of the mounting area of the semiconductor integrated circuit, a method of applying the MCM mounting instead of making a plurality of LSIs into one LSI has been devised. According to this method, an object which has been sealed in two packages on the board is mounted, but the mounting area and the speed advantage by eliminating the wiring on the board can be obtained.

[0003] In addition, the cost required for circuit testing has increased due to the high integration. This test cost is mainly due to the time required for testing (depreciation of expensive testers) and the occurrence of market defects due to insufficient test coverage. With conventional test vectors, it is difficult to confirm the functions of all transistors in highly integrated circuits.Today, test circuits dedicated to test functional modules such as scan circuits and memories have been created as dedicated circuits for testing, reducing test time, Improves test coverage.

[0004]

However, most of the conventional LSI tests use a frequency that is considerably slower than the actual operating frequency of the LSI. For example, an image LSI or the like used in a VCR or the like is actually used at 20 to 30 MHz, but is operated at about 1 MHz during a function test. Although the scan circuit and the test circuit dedicated to the function module test described above are used only for the function test and are not necessary for the actual operation, an expensive process similar to other circuits requiring high-speed operation is required. And has a problem due to an increase in the area (= cost) of these circuits.

Accordingly, it is an object of the present invention to provide a semiconductor integrated circuit, a semiconductor device, and a test method therefor, which suppress an increase in manufacturing cost by an LSI test circuit.

[0006]

According to a first aspect of the present invention, there is provided a semiconductor device including a plurality of circuit units including a first circuit unit and a second circuit unit having different block parameters. Is formed on a first LSI, and the second circuit is divided from the first LSI.
The first LSI is a semiconductor device that is electrically connected to the second LSI externally, and is formed on a second LSI that is an integrated LIS. One of the second circuit units has an input terminal, a test input terminal, a test control terminal, an output terminal, a test output terminal, a logic circuit unit for realizing a specific function, and a signal from the test control terminal. A selection circuit for inputting either the input terminal or the signal from the test input terminal to the logic circuit, wherein an output signal of the logic circuit is output to an output terminal and a test output terminal, The input terminal and the output terminal have bonding pads that can be electrically connected to the outside, thereby achieving the above object.

According to still another aspect of the present invention, there is provided a semiconductor device, wherein a plurality of logic circuit units, a connection unit for making an electrical connection with the outside, and at least one of the plurality of logic circuits pass through the connection unit. without a first LSI having an external electrical connection can be bonding pads, and the test circuit portion, wherein
A test LSI having a connection part , which is an LIS divided from the first LSI and electrically connected to the outside, and a bonding pad corresponding to the bonding pad of the first LSI on a one-to-one basis; The bonding pads of the first LSI and the bonding pads of the test LSI are electrically connected externally, and a connection portion of the first LSI and a test pattern provided from the connection portion of the test LSI are used. Thus, a test is performed on the logic circuit portion of the first LSI, thereby achieving the above object.

The test circuit of the test LSI may be externally changeable by a program.

According to a semiconductor device test method of the present invention, a plurality of logic circuit units, a connection unit for making an electrical connection with the outside, and at least one of the plurality of logic circuits pass through the connection unit. And a first LSI having a bonding pad electrically connectable to the outside, and the first LSI
A test circuit unit having a test circuit unit , which is a divided LIS, a connection unit for making an electrical connection to the outside, and a bonding pad corresponding to the bonding pad of the first LSI on a one-to-one basis. Electrically connecting a bonding pad of the first LSI and a bonding pad of the test LSI externally, a connecting portion of the first LSI, and a connecting portion of the test LSI. Performing a test of the logic circuit portion of the first LSI using the test pattern given by the above, thereby achieving the above object.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 2 is a circuit diagram of an LSI separated into two by block parameters. In the present embodiment, as shown in FIG. 1, the "logic circuit" and the "memory and memory test circuit" are divided as parameters, and the first LSI and the second LSI are mounted on the MCM.

In FIG. 2, a first LSI 7 and a second LSI
The SI 8 is characterized by parameters of “logic circuit” and “memory and memory test circuit” and is divided into two LSIs. Each of the bonding pads 9 is electrically connected one-to-one externally. This functions as the semiconductor device according to the third aspect .

1 is a logic circuit unit, 2 is a test control circuit for testing the logic circuit unit 1, 3 is a connection unit (I / O) for making an electrical connection with the outside, and 4 is a selection circuit unit (mux). Reference numeral 5 denotes a D flip-flop with a scan function (SCAN-DFF), and reference numeral 6 denotes a selection circuit.

Next, the semiconductor device of the present invention will be described with reference to FIG.
This will be described with reference to FIG. 67 of the second LSI 8 is a circuit of a memory having a selection function (corresponding to claim 1);
FIG. 6 shows the details. Switching between the normal mode and the test mode is performed by the control from the test control terminal 65. In the normal mode, the selection circuit section 66 inputs the memory control signal, address and data input from the input terminal 61 to the memory 60. , The memory 60 reads / writes data according to the input memory control signal and address, and outputs the read result to the test output terminal 63 and the output terminal 6.
4 is output. On the other hand, in the test mode, the selection circuit section 66 (functioning as a part of the memory test circuit) inputs a memory control signal, an address and data input from the test input terminal 62 to the memory 60, and the memory 60 3. A semiconductor integrated circuit according to claim 2, wherein data is read / written in accordance with a memory control signal and an address to be read, and a read result is output to a test output terminal 63 and an output terminal 64. Is what you do.

By dividing the "logic circuit" and the "memory and memory test circuit" as described above, there are the following advantages.

(1) By dividing into two types of LSIs, the area of each LSI is reduced and the manufacturing yield is improved as compared with the case where the LSIs are formed without division.

(2) Also, due to the layout inside the LSI,
The more the number of objects with fixed shapes, the more difficult it is to optimize the area. However, since the memory with the fixed shape does not exist in the first LSI, the area optimization becomes very easy and the area is further reduced. it can.

The manufacturing cost is reduced from the above (1) and (2). (3) The memory and the logic circuit in a connection relationship are mounted by MCM as shown in FIG. It becomes unnecessary, and higher speed operation becomes possible.

Although the present embodiment has been described with respect to an example in which the parameters are configured by a memory, the present invention can be similarly applied to an arithmetic unit such as an FPU or a DSP.

(Embodiment 2) FIG. 3 is a circuit diagram of an LSI separated into two by other block parameters.
In the present embodiment, the division is made using “logic circuit and memory” and “memory test circuit” as parameters.

In FIG. 3, a first LSI 57 and a second LSI 58 are characterized by parameters of “logic circuit and memory” and “memory test circuit”, and have two LSIs.
I, and each bonding pad 9
Are electrically connected one-to-one externally, and function as the semiconductor device according to the third aspect .

Reference numeral 1 denotes a logic circuit unit, and 2 denotes a logic circuit unit.
A test control circuit for testing a circuit, 3 a connection unit for making an electrical connection to the outside, 4 a selection circuit unit, 5 a D flip-flop with scan function (SCAN-DFF), 41 an input pattern generator and an output pattern BIST (Build In Self Tes
t) circuit.

Next, the semiconductor device of the present invention will be described with reference to FIG.
This will be described with reference to FIG. 77 of the first LSI 57 is a circuit of a memory having a selection function (corresponding to claim 2), the details of which are shown in FIG. Switching between the normal mode / test mode is performed by control from the test control terminal 75,
In the normal mode, the selection circuit section 76 inputs a memory control signal, address and data input from the input terminal 71 to the memory 70, and the memory 70 reads / writes data according to the input memory control signal and address. And outputs the read result to the test output terminal 73 and the output terminal 74. On the other hand, in the test mode, the selection circuit section 76 inputs a memory control signal, an address, and data input from the test input terminal 72 to the memory 70, and the memory 70 outputs the data according to the input memory control signal and address. It is configured to perform read / write and output the read result to a test output terminal 73 and an output terminal 74.

In the normal mode, the first LSI 57 reads / writes data according to the normal address regardless of the second LSI 58, and in the test mode, the BIST circuit 41 of the second LSI 58 After writing the data generated by the BIST circuit 41 in accordance with the generated address, the data is read from the same address, and it is compared whether the correct data was read or written. The comparison result is passed through the connection unit 3 of the second LSI 58. Output.

In general, a test circuit is a circuit which is added separately from specifications required for an LSI in order to make it easy to determine a non-defective product in a manufacturing process, and is unnecessary for a user. Therefore, how to make the unnecessary “test circuit” cheaply contributes greatly to the total cost.

As described above, dividing the "logic circuit and memory" and the "memory test circuit" has the following advantages.

(1) In particular, a circuit ("logic circuit and memory") necessary for actual operation is formed in the first LSI, and a circuit ("memory test circuit") unnecessary for actual operation is formed in the second LSI. By separating, only the first LSI can be manufactured using an expensive high-speed and high-integration process, and the second LSI can use an inexpensive process corresponding to the test frequency. It is valid.

(2) If the second LSI is composed of an FPGA, a PLA, or the like, whose logic can be rearranged programmatically, the manufacture of the second LSI becomes unnecessary, so that the cost can be further reduced significantly. It is.

(Embodiment 3) FIG. 3 is a diagram showing division of a first LSI and a second LSI (= test LSI), and FIGS. 4 and 9 are a first LSI and a test LSI at the time of test.
FIG. 8 is a diagram showing electrical connection of SI, and FIG. 8 is a diagram showing a configuration of a semiconductor test apparatus.

In FIG. 8, 101 is a CPU, 102 is a data storage unit for storing test input data 114 and its expected value 115, 103 is a ROM for storing various programs executed by the CPU, and 104 is a display. Display, 105 is an input keyboard, 106 is a CPU
A waveform generation unit for generating a waveform to be applied to the LSI under test based on the digital signal from the LSI, a waveform detection unit 107 for detecting a response signal from the LSI under test, an IO unit 108, 83
Is a test board, 111 is a waveform generation program, 11
Reference numeral 2 denotes a waveform detection program, and reference numeral 113 denotes a coincidence determination program for determining whether the response signal from the LSI under test coincides with the expected value data 115.

4 and 9, reference numeral 57 denotes a logic circuit section, a connection section 3, and a bonding pad 9, and a first LSI to be a test LSI, and 58, a test circuit section 50, a connection section 3 And a second LSI which is a test LSI composed of the bonding pads 9 and 57, 58
Are characterized by parameters of "logic circuit and memory" and "memory test circuit", are divided into two LSIs, and each bonding pad 9 is electrically connected one-to-one externally.

A test board 83 has a test L
The SI 58 is surface-mounted in advance by solder bumps 85, and makes electrical connection with the first LSI 57 through the probe 84. That is, the test board 83 is configured as shown in FIG.
As shown in FIG. 8, a function of connecting the corresponding bonding pads (BP parts) 9 of the first LSI and the second LSI and connecting the connection parts 3 of the first and second LSIs to the I / O 108 shown in FIG. have.

Next, a method for testing a semiconductor device according to the present invention will be described with reference to FIGS. 3, 4, 8, and 9. FIG.

(First Step) The probe 84 of the test board 83 comes into contact with all the bonding pads 9 and all the connection portions 3 of the first LSI (state 2 in FIG. 4), and the first LSI 57 Each of the bonding pads 9 of the test LSI 58 and the bonding pads 9 of the test LSI 58 are in a conductive state, and the connection 3 of the first LSI 57 and the connection 3 of the test LSI 58
Through the / O section 108, the waveform generation section 106 and the waveform detection section 107 are brought into conduction.

(Second Step) Next, the CPU 101 issues a command for generating a test input signal to the waveform generating unit 106 from the waveform generating program 111 and the input data 114, and the waveform generating unit 106 outputs the test input signal in accordance with the command. The test board 83 is provided.

(I) When the test input signal is in the normal mode, the first LSI 57 operates independently irrespective of the operation of the test LSI 58, and outputs the result to the test board 83.
To the waveform detection unit 107 through The CPU 101 includes a waveform detection program 112 and a coincidence determination program 113
Is used to determine the match / mismatch between the signal transmitted to the waveform detection unit 107 and the value of the expected value data 115, and the result is displayed on the display unit 104.

(Ii) When the test input signal is in the test mode (SCAN mode), the first LSI 7 operates independently of SCAN irrespective of the operation of the test LSI 8, and outputs the result through the test board 83 to the waveform detector. 107
Tell The CPU 101 uses the waveform detection program 112 and the coincidence determination program 113 to
7 and the value of the expected value data 115 are determined, and the result is displayed on the display unit 104.

(Iii) When the test input signal is in the test mode (memory test mode), the memory 70 writes the data generated by the BIST circuit 41 in accordance with the address generated by the BIST circuit 41 of the second LSI 58. After that, data is read from the same address and BI
The ST circuit 41 compares the read data with the expected value generated by the BIST circuit 41 itself, and compares the result with the test L
The signal is output from the connection unit 3 of the SI 58 and transmitted to the waveform detection unit 107 through the test board 83. The CPU 101 uses the waveform detection program 112 and the coincidence determination program 113 to determine whether the signal transmitted to the waveform detection unit 107 matches the value of the expected value data 115, and displays the result on the display unit 104.

In the above embodiment, a probe is used to connect the first LSI to the test board. Instead of the probe, a low-hardness protruding electrode made of resin and metal is used as shown in FIG. An example using 91 may be adopted.

[0040]

As described above, according to the present invention, the circuits necessary for the actual operation are formed in the first LSI, and the memory test circuit is separated into the second LSI. L
Only the SI is manufactured using an expensive high-speed and high-integration process, and the second LSI can use an inexpensive process corresponding to the test frequency, which is effective in reducing the cost of the LSI. Further, if the second LSI is constituted by an FPGA or the like which can rearrange the logic in a program manner, the second LSI
Since the production of the PDP is not required, the cost can be further significantly reduced.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of division and mounting of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of one LSI divided by parameters “logic circuit” and “memory and memory test circuit”;

FIG. 3 is a configuration diagram of one LSI divided by parameters “logic circuit and memory” and “memory test circuit”;

FIG. 4 is a diagram illustrating an example of an electrical connection between a first LSI and a test LSI;

FIG. 5 is a diagram showing another example of the electrical connection between the first LSI and the test LSI;

FIG. 6 is a circuit diagram of a memory having a selection function.

FIG. 7 is a circuit diagram of a memory having a selection function.

FIG. 8 is a configuration diagram of a semiconductor test apparatus.

FIG. 9 is a diagram showing an electrical connection between a first LSI and a test LSI;

[Explanation of symbols]

 Reference Signs List 1 logic circuit unit 2 test control circuit 3 connection unit 4 selection circuit unit 5 D flip-flop with scan function 6 selection circuit 7, 57 first LSI 8, 58 second LSI 9 bond pad 41 BIST circuit 50 test circuit unit 60, 70 memory 61, 71 input terminal 62, 72 test input terminal 63, 73 test output terminal 64, 74 output terminal 65, 75 test control terminal 66, 76 selection circuit section 67, 77 memory circuit having selection function 83, 90 Test Board 84 Probe 85 Solder Bump 91 Low Hardness Protruding Electrode 101 CPU 102 Data Storage Unit 103 ROM for Storing Various Programs 104 Display Display 105 Input Keyboard 106 Waveform Generator 107 Waveform Detector 108 IO Unit 111 Waveform Generator 112 waves Detection program 113 match determination program 114 input data 115 expected value for the test

Claims (7)

(57) [Claims] A plurality of circuit sections including a first circuit section and a second circuit section having different block parameters, wherein the first circuit section is formed on a first LSI; 2 is divided into the first LSI and the divided L.
The first LSI is a semiconductor device electrically connected to the second LSI externally, and is formed on a second LSI which is an SI . One of the circuit portions of the input terminal, a test input terminal, a test control terminal, an output terminal, a test output terminal, a logic circuit portion that implements a specific function, according to the signal of the test control terminal, A selection circuit for inputting one of an input terminal and a signal from the test input terminal to the logic circuit, wherein an output signal of the logic circuit is output to the output terminal and the test output terminal, A semiconductor device, wherein the input terminal and the output terminal include a semiconductor integrated circuit having a bonding pad electrically connectable to the outside. 2. A semiconductor device comprising: a plurality of circuit units including a first circuit unit and a second circuit unit having different block parameters, wherein the first circuit unit is formed on a first LSI; 2 is divided into the first LSI and the divided L.
The first LSI is a semiconductor device electrically connected to the second LSI externally, and is formed on a second LSI which is an SI . One of the circuit portions of the input terminal, a test input terminal, a test control terminal, an output terminal, a test output terminal, a logic circuit portion that implements a specific function, according to the signal of the test control terminal, A selection circuit that inputs one of an input terminal and a signal from the test input terminal to the logic circuit unit, and an output signal of the logic circuit unit is output to the output terminal and the test output terminal. A semiconductor device including a semiconductor integrated circuit having a bonding pad electrically connectable to the outside, wherein the test input terminal, the test output terminal, and the test control terminal. 3. The semiconductor integrated circuit according to claim 1, wherein the specific function is a function of at least one of a memory and a computing unit. 4. The first LSI and the second LSI
3. The semiconductor device according to claim 1, wherein the semiconductor devices are mounted with the surfaces of the respective LSIs superposed on each other. 5. A plurality of logic circuit units, a connection unit for making an electrical connection with the outside, and at least one of the plurality of logic circuits can be electrically connected to the outside without passing through the connection unit. LSI having simple bonding pad
When a test circuit portion, and a connecting portion for performing outside the electrical connection, have a bonding pad which correspond one-to-one to the bonding pad of the first LSI, to the first LSI min
A semiconductor device comprising a split test LSI, a step of electrically connecting a bonding pad of the first LSI and a bonding pad of the test LSI externally, and a connection portion of the first LSI And a step of testing a logic circuit section of the first LSI using a test pattern given from a connection section of the test LSI. 6. A plurality of logic circuit units, a connection unit for making an electrical connection with the outside, and at least one of the plurality of logic circuits can be electrically connected to the outside without passing through the connection unit. a first LSI having a bonding pad such, possess a test circuit portion, and a connecting portion for performing outside the electrical connection, the bonding pads a one-to-one correspondence with the bonding pad of the first LSI, wherein First LSI and minutes
A cracked test LSI, electrically connecting the bonding pads of the first LSI and the bonding pads of the test LSI externally, a connection portion of the first LSI, and the test LSI A test of a logic circuit portion of the first LSI using a test pattern provided by a connection portion of the semiconductor device. 7. The test circuit section of the test LSI,
7. The semiconductor device according to claim 6, which can be externally changed by a program.