JP3186137B2 - Information processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing system suitable for application to various processing circuits such as a servo system, a digital filter and a timer.

[0002]

2. Description of the Related Art Conventionally, in various processing circuits such as a servo system, a digital filter, a timer, and the like, processing is mostly performed by a program using a microcomputer.

FIG. 6 shows a motor servo system as an example.

In FIG. 6, reference numeral 1 denotes a motor. The rotation frequency of the motor 1 is detected by a frequency generation circuit 2 and output as a frequency signal.

The frequency signal is supplied to a comparator 3, which compares the frequency signal with a reference signal. The error signal as a result of the comparison is output from an input / output port 9 and a bus (address, control and data buses) of the microcomputer 4. Is supplied to the CPU 5.

The CPU 5 obtains a control signal based on an error signal from the comparator 3 using the RAM 7 as a work area in accordance with various programs stored in the ROM 8,
This control signal is supplied to the motor 1 via the amplifier circuit 10.

Thus, the motor 1 is driven stably by the servo.

As shown in FIG. 4, a processing section as a program stored in the ROM 8 generally includes a main processing section p1 as a main program and a main processing section p1 as a main program.
The sub-processing units p2 and p as sub-programs that perform processing by interrupting at various timings in the processing process 1
3,... Pn.

FIG. 5 shows the main processing unit p1 and the sub-processing unit p.
The processing timing of 2, p3,... Pn is shown.

In FIG. 5, the processing time of each of the processing units p1 to pn is indicated by a high level “1”.

As shown in FIG. 5, each sub-processing unit p2,
The time other than the time during which p3,... pn is performing processing is the time during which the main processing unit p1 is performing processing.

If the interrupt timing and the processing time are different as described above, an overlap portion ob occurs where the processing timings of the respective sub-processing units overlap as shown by hatching in FIG.

When this overlap occurs, that is,
For example, when the sub-processing units p2 and p3 overlap, the processing of the sub-processing unit p2 is prioritized, and when the sub-processing units p3 and pn overlap, the processing of the sub-processing unit p3 is prioritized.

[0014]

In the processing as a program configured as described above, for example, the sub-processing unit p2,
p3,... pn program length (processing length)
Or the timing of these interrupts has changed,
It affects the processing timing of other processing units including the main processing unit p1.

For example, in the servo system of the motor shown in FIG. 6, due to this effect, a time loss occurs, which affects the servo transfer function, and the servo becomes unstable. .

The present invention has been made in view of the above points, and enables easy-to-understand programming that is easy to debug, and prevents time overlap between the sub-processing units so that the inter-sub-processing unit The present invention aims to propose an information processing method that can perform high-accuracy servo without time loss when applied to a servo system, for example, by not affecting the transfer function of the servo system. .

[0017]

According to the information processing system of the present invention, for example, as shown in FIGS.
And a reference signal generating unit c3 for generating a reference signal , and counting the n-bit value based on the reference signal, and adding 2 ¹ , 2 ² , 2 ³ , 2 ^{4 to} the time information T0 of one cycle of the reference signal. ,
..A plurality of time information T0 × 2 ¹ , T0 × 2 multiplied by 2 ^{n
2, T0 × 2 3, T0} × 2 4, a counting section c1 obtaining ··· T0 × 2 ^n, a plurality of counter c1 is counted time information T
^{0 × 2 1, T0 × 2} 2, T0 × 2 3, T0 × 2 4, ··
A plurality of sub-processing units q2, q3, q4, q5,... Qn to which T0 × 2 ⁿ is assigned as weights, and weighted time information T0 × 2 ¹ , T0 from the counting unit c1.
× 2 ² , T0 × 2 ³ , T0 × 2 ⁴ ,..., T0 × 2 ⁿ Sub-processing units q2, q3, q4, q5,.
n corresponds to the lower bit of the n-bit count value.
And a determining unit c2 for sequentially selecting the sub processing unit q
The processing time of 2, q3, q4, q5,..., Qn is shorter than at least one period T0 of the reference signal.

[0018]

According to the present invention described above, a plurality of sub-processing units q each having a processing time shorter than at least one cycle T0 of the reference signal are provided.
2, q3, q4, q5, 2 1 in the time information T0 of one period of the reference signal to ^{···· qn, 2 2, 2 3} , 2 4, ·
..A plurality of time information T0 × 2 ¹ , T0 × 2 multiplied by 2 ^n
2 , T0 × 2 ³ , T0 × 2 ⁴ ,... Weighted by T0 × 2 ⁿ
And weighted by the counting unit c1.
Time information ^{T0 × 2 1, T0 × 2} 2, T0 × 2 3, T0
× 2 ⁴ ,... Sub-processing units q2, q corresponding to T0 × 2 ⁿ
.., Qn are n-bit count values
Since the processing is performed by sequentially selecting from the ones corresponding to the lower bits, programming that is easy to understand and easy to debug is possible, so that there is no time overlap between the sub-processing units, The transfer function between the sub-processing units can be prevented from being affected.
For example, when applied to a servo system, a highly accurate servo can be performed without time loss, and when applied to, for example, a digital filter or a timer, these algorithms can be easily configured. .

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the information processing system of the present invention will be described below in detail with reference to FIG.

In FIG. 1, q1 is a main processing section as a main program, c1 is a counter as a calculation program for counting reference signals shown in FIG. 3A, for example, and c2 is one of the reference signals calculated by the counter c1. A judgment unit as a judgment program for selecting a sub-processing unit q2, q3, q4, q5,... Qn based on the time information of the cycle multiplied by 2 ^n, that is, c3 is, for example, 1
This is a reference signal generator that generates a reference signal having a cycle of 1 msec.

For example, a program having such a configuration is used for processing of the servo system as shown in FIG.

Next, the operation of the entire program will be described with reference to FIG.

First, at step 100, the main processing is executed by the main processing section q1. Then, the process proceeds to step 110.

In step 110, the counter c1 counts the count value MC = MC + 1, that is, counts the reference signal from the reference signal generator c3. And step 1
Move to 20.

That is, 2 ⁿ is multiplied by the time information of one cycle of the reference signal as shown in FIG. 3A.

In step 120, the judgment unit c2 determines
It is determined whether or not the count value MC is 2 ¹ × T0 (for example, one cycle of the reference signal). If “YES”, the process proceeds to step 130, and if “NO”, the process proceeds to step 140.

In step 130, the sub-processing unit q2 executes sub-processing. Then, the process returns to step 100 again.

In step 140, the judgment unit c2 determines
It is determined whether or not the count value MC is 2 ² × T0. If “YES”, the process proceeds to a step 150, and if “NO”, the process proceeds to a step 160.

At step 150, the sub-processing unit q3 executes sub-processing. Then, the process returns to step 100 again.

In step 160, the judgment unit c2 determines
It is determined whether or not the count value MC is 2 ³ × T0. If “YES”, the process proceeds to a step 170, and if “NO”, the process proceeds to a step 180.

In step 170, the sub-processing unit q4 executes sub-processing. Then, the process returns to step 100 again.

At step 180, the judgment unit c2 determines
It is determined whether or not the count value MC is 2 ⁴ × T0. If “YES”, the process proceeds to a step 190, and if “NO”, the process proceeds to the next step.

At step 190, a sub-process by the sub-processor q5 is executed. Then, the process returns to step 100 again.

In step n, the judgment section c2 judges whether or not the count value MC is 2 ⁿ × T0. If “YES”, the flow proceeds to step n + 1. If “NO”, the flow proceeds to step 100 again. I do.

As described above, in this embodiment, the counter c
1 counts the reference signal from the reference signal generation unit c3, for example, and the determination unit c2 determines the count value, that is, the time information, and the sub-processing unit q to which the time information is assigned in advance.
2, q3, q4, q5,..., Qn are selected.

The judgment by the judging section c2 is made to give priority to, for example, the lower bit of the value counted by the counter c3.

For example, if the count value of the counter c1 is "0100
In the case of "0000", the sub-processing unit q3 weighted by "1", that is, the time information of one cycle of the reference signal × 2 ² is executed.

On the other hand, for example, if the count value of the counter c1 is "1"
In the case of "1100000", there are three bits where "1" is set, but when "1" is set for a plurality of bits, the bit with the lowest "1" is given priority.

That is, in this case, the sub-processing unit q2 weighted by time information of one cycle of the reference signal × 2 ¹ is executed.

[0040] Here, the time information representing the 2 ⁿ is generally different from the 2 ⁿ defined for bits known counter.

That is, in the present embodiment, this 2 ^{n is taken} to mean ^{n n} of the period of the reference signal.

That is, the ratio of “1” (the period during which the process is active) to the first bit, which is the least significant bit at which the process of the sub-processing unit q2 is selected, is once every two periods with respect to the reference signal. The rate at which “1” (the period during which the processing is active) is set to the second bit at which the processing of the sub-processing unit q3 is selected is once every four cycles with respect to the reference signal. The rate at which "1" (a period during which the processing is active) is set to the third bit at which the processing of (1) is selected is once in eight cycles with respect to the reference signal, and the processing of the sub-processing unit q5 is selected. The ratio of “1” (the period during which the process is active) at the bit is once in 16 cycles with respect to the reference signal,
The ratio of “1” at the n-th bit (most significant bit) at which the processing of the sub-processing unit qn is selected is once every 2 ⁿ cycles with respect to the reference signal.

Therefore, as described above, each sub-processing unit q2
Temporal weighting of ~qn, vice processor q2 time T0 × 2 ¹ of 1 cycle of the reference signal, the sub-processor q3 is 1 period of the reference signal time T0 × 2 ^2, sub-processing unit q4 reference signal one cycle time T0 × 2 ^3, sub-processing unit q5 is one period of a reference signal time T0 × 2 ^4, ···· sub-processing unit qn is time T0 × 2 ⁿ of one period of the reference signal.

FIG. 3 shows a timing chart when such processing is performed.

In FIG. 3, the high-level "1" portion of the timing chart of the processing by the processing units q1 to q5 is processed by the respective processing units q1 to q5 (the sub-processing unit qn is not shown). Running time.

As shown in FIG. 3, each sub-processing unit q
The processing time from 2 to q5, that is, the time when the output of the counter c1 is "1" is set shorter than the time T0 of one cycle of the reference signal.

Therefore, as shown in FIG. 5, the processing times of the sub-processing units q2, q3, q4 and q5 do not overlap.

As described above, the counter C1 causes each of the sub-processing units q2 to qn to output the time T0 of one cycle of the reference signal.
Is multiplied by 2 ⁿ to select and execute the sub-processing units q2 to qn. Since the access time of each of the sub-processing units q2 to qn is temporally weighted, debugging is performed. Is easy to understand, and the sub-processing units q2 to qn are not overlapped with each other in time.
To qn so as not to affect the transfer function between them, whereby, for example, when applied to a servo system, it is possible to perform high-precision servo without time loss,
When applied to, for example, a digital filter or a timer, these algorithms can be easily configured.

It should be noted that the present invention is not limited to the above-described embodiments, but may take various other configurations without departing from the gist of the present invention.

[0050]

Effects of the Invention According to the present invention to above, a plurality of time information T0 to 2 ¹ of 1 cycle of the reference signal to the sub-processing unit in which a shorter processing time than at least one cycle T0 of the reference signal,
Multiple time information multiplied by 2 ² , 2 ³ , 2 ⁴ ,... 2 ^{n
T0 × 2 1, T0 × 2} 2, T0 × 2 3, T0 × 2 4, ·
· · T0 × 2 with weights at ^n, counted by the counting unit weighting time information ^{T0 × 2 1, T0 × 2} 2,
The sub-processor corresponding to T0 × 2 ³ , T0 × 2 ⁴ ,... T0 × 2 ⁿ corresponds to the lower bits of the n-bit count value.
Processing is performed by sequentially selecting from the
Since the access time of each sub-processing unit is time-weighted, easy-to-understand and easy-to-understand programming can be performed. It is possible not to affect the transfer function between the two, so that, for example, when applied to a servo system, time loss can be eliminated and highly accurate servo can be performed. When applied, there is an advantage that these algorithms can be easily configured.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an information processing method according to the present invention.

FIG. 2 is a flowchart for explaining one embodiment of the information processing system of the present invention.

FIG. 3 is a timing chart for explaining one embodiment of the information processing system of the present invention.

FIG. 4 is a block diagram showing an example of a conventional information processing method.

FIG. 5 is a timing chart for explaining an example of a conventional information processing method.

FIG. 6 is a configuration diagram illustrating an example of a servo system of a motor.

[Explanation of symbols]

 q1 main processing unit q2, q3, q4, q5,... qn sub-processing unit c1 counter c2 determination unit c3 reference signal generation unit

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 9/46 H02P 1/00-19/00 F02D 45/00 G11B 1/00-33/00 G05B 19 / 05 G05B 15/02 JICST file (JOIS) CSDB (Japan Patent Office)

Claims (1)

(57) [Claims] 1. A main processing section for performing main processing, a reference signal generating section for generating a reference signal , counting an n-bit value based on the reference signal, and obtaining time information T0 of one cycle of the reference signal 2 ¹ , 2 ² , 2 ³ ,
2 ^4, a plurality of time information T0 × 2 ¹ multiplied by · · · 2 ^{n,
T0 × 2 2, T0 × 2} 3, T0 × 2 4, ··· T0 × 2
a counting unit to obtain a ^n, the counting unit plurality of time information T0 × 2 ¹ counted is, T0
^{× 2 2, T0 × 2 3} , T0 × 2 4, are ··· T0 × 2 ⁿ
A plurality of sub-processing units to be assigned as a weighted, weighted time information from the counting part T0 × 2 ^{1,
T0 × 2 2, T0 × 2} 3, T0 × 2 4, ··· T0 × 2
The sub-processing unit corresponding to ⁿ is set to the lower value of the n-bit count value.
And a determination unit for sequentially selecting from the bit corresponding to the order bit, wherein the processing time of the sub-processing unit is shorter than at least one cycle T0 of the reference signal.