JP3185716B2 - Demodulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulator for performing synchronous detection using a unique word, and more particularly to a carrier recovery apparatus for demodulating a phase modulated (PSK) or frequency modulated (FSK) signal by inserting a unique word. And a clock recovery method.

[0001]

2. Description of the Related Art A conventional demodulator will be described with reference to the drawings.

2. Description of the Related Art A technique for detecting a received signal in which a unique word is inserted, performing frame synchronization and signal detection, and demodulating the signal is known. For example, Japanese Patent Application Laid-Open No. 5-167630
The "unique word detector" described in Japanese Unexamined Patent Publication (Kokai) No. 2000-216, provides a circuit capable of detecting a unique word with a relatively small circuit even when an input signal has a frequency error.

FIG. 9 shows the configuration of the unique word detector described in the above publication.

Here, as shown in FIG. 8, a preamble and a unique word (fixed word) are placed at the head of the data part.
However, a signal having a frame structure inserted periodically is defined as an input signal R (t). Usually, the preamble length is about 8
There are 0 symbols, and about 20 unique words are used. First, the input signal R (t) is subjected to delay detection by the first delay detector 25 to obtain a detection output D (t).

[0005]

Here, τ is a delay time of the delay detector 25, and R * (t) is a complex conjugate of R (t).

Next, the cross-correlation C (t) of the unique word pattern U (t) from the unique word generator 21 with the pattern W (t) differentially detected by the second delay detector 26 is calculated by the following equation. Calculated by the unit 22.

[0008]

The level detector 23 detects that the square of the absolute value | C (t) | 2 exceeds the threshold value, and detects a unique word. Since the input signal is differentially detected by this configuration, the frequency offset included in the input signal is removed.

Next, as a prior art of a carrier wave component extraction circuit, a configuration shown in FIG. 10 is known.

That is, the fixed word (unique word) portion in the input signal (Ri) is inversely modulated by a multiplier 36 with a signal Rs obtained by complexly conjugating the output Ru of the fixed word table 32, and modulated. After removing the components, the adaptive bright line enhancer 31
To enter. The adaptive bright line enhancer 31 adapts to the bright line component in the inversely modulated signal and extracts the carrier component.
An input signal is demodulated to obtain an output Ro by the reproduced carrier wave. Thereafter, when the unique word portion of the input signal ends and the data becomes random data, the changeover switch 34 is switched to the hard decision unit 33. Since the hard decision unit 33 estimates an integer (fixed word) from the demodulated signal Ro, by applying inverse modulation with the estimated value, it is possible to remove a modulation component from the input signal Ri and continue demodulation. The details of the above operation are described in JP-A-5-63743.

Conventionally, when a demodulation device is configured, a unique word position in an input signal is detected by the technique described in Japanese Patent Application Laid-Open No. Hei 5-167630, and according to the information, a unique word position is disclosed in Japanese Patent Application Laid-Open No. Hei 5-63743. Based on the technology described, demodulation processing is performed by applying inverse modulation to a unique word portion using a unique word table, and performing inverse modulation by the demodulator output in other portions.

That is, the changeover switch 34 shown in FIG. 10 is driven by the output of the level detector 23 shown in FIG. 9 to control the inverse modulation based on the unique word table 32 or the inverse modulation based on the demodulated output signal Ro.

[0014]

In the structure of the demodulator described above, according to the technique disclosed in Japanese Patent Laid-Open No. 5-167630, when a unique word is detected, a detection pulse is output when the correlator output exceeds a threshold. Therefore, it is not possible to accurately estimate the clock phase of the input signal.
There has been a problem that the pull-in characteristics of the demodulator thereafter deteriorate. Specifically, the accuracy of estimating the clock phase depends on how to determine the threshold, but is within a range of about ± 1/2 clock, and has a large variation.

In the prior art described in Japanese Patent Application Laid-Open No. Hei 5-63743, the pull-in frequency range (the range where the pull-in can be performed with a high probability of 95% or more) is only about ± 1/8 of the symbol frequency. There has been a problem that an input signal having an input frequency offset exceeding that cannot be demodulated.

In view of the above-mentioned problems of the prior arts, it is an object of the demodulation device of the present invention to use a unique word included in an input signal to more accurately estimate a clock phase, and The purpose is not to deteriorate the pull-in characteristic of the demodulator. It is another object of the present invention to provide a demodulation device that can estimate a frequency offset at the same time and expand a pull-in frequency range.

Another object of the demodulator of the present invention is to improve the frequency estimation accuracy even for a received signal having a large amount of noise components, and to provide a PLL having a narrow pull-in range for a demodulator.
An object of the present invention is to provide a demodulation device which can use a demodulator.

[0018]

A demodulator according to the present invention delay-detects an input signal in which a unique word is inserted, and performs correlation between the differential detection output and a data table obtained by delay-detecting the unique word. Detecting the maximum time when the power of the correlation value exceeds the threshold, reading from the head of the unique word by the buffer storing the input signal based on the time, and calculating the phase of the maximum correlation value. Estimating the frequency error of the input signal, obtaining a signal from which the frequency error has been removed from the read signal, and inversely modulating a unique word portion in the signal from which the frequency error has been removed according to data in a unique word table. After that, carrier recovery is performed.

Further, the demodulation device of the present invention comprises a delay detection circuit for delay-detecting an input signal in which a unique word is inserted, and a correlator for correlating an output of the delay circuit with a pattern obtained by delay-detecting the unique word. And when the power of the correlator output exceeds a predetermined threshold, a peak detector that detects a time at which the power becomes maximum before and after the correlator output, and an output value of the correlator at the detection time of the peak detector output. A phase error estimating circuit for estimating a frequency, estimating a frequency error of the input signal by dividing the phase by a delay time of the delay detection circuit, and accumulating the input signal, and inputting the input signal based on a time of the peak detector output. A buffer that outputs the unique word from the beginning of the unique word, a frequency shifter that performs frequency conversion of the buffer output according to the output of the frequency error estimating circuit, A first inverse modulator for performing inverse modulation on a unique word portion of an output using a previously stored unique word pattern, and a carrier recovery circuit for performing carrier recovery of the output of the inverse modulator and outputting a demodulated signal And characterized in that:

[0020] In the carrier recovery, a second inverse modulator that inversely modulates the output of the first inverse modulator based on the demodulated signal while the unique word portion is being input, except for the unique word portion. A changeover switch for selecting the output of the inverse modulator, an output of the changeover switch, an adaptive line enhancer adapted to adapt to the bright line component and extract the carrier wave, and converting the output of the adaptive bright line enhancer to a complex conjugate value. It is characterized by comprising a complex conjugate and a multiplier for multiplying an output of the complex conjugate with an output of the first inverse modulator to output the demodulated signal.

Next, the principle of the present invention will be described.

The unique word (fixed word) portion included in the input signal r (t) is expressed by the following equation, where U (t) is the fixed word portion and fd is the frequency error. Here time to
（(To + tu) represents the time of the unique word part.

[0023]

When a signal obtained by performing delay detection on this at time τ is d (t),

[0025]

## EQU1 ## Here, U * (t) is a conjugate complex number of U (t).

If the correlation reference signal is w (t),

[0028]

## EQU1 ##

The signal c (t) is obtained by cross-correlating the signal d (t) with the signal w (t).

[0031]

The correlation value in this case is expressed by the following equation (7).

[0033]

Here, A is a real number, and the phase θ is 2πΔfτ. Therefore, when the phase θ is obtained,

[0035]

## EQU1 ## Here, if the estimated frequency is fe,

[0037]

Therefore,

[0039]

Since τ is known, the value of fe can be obtained.

If the frequency error of the input signal is removed using the estimated value fe, the frequency error of the input signal can be reduced.
The demodulation can be performed even if it exceeds the pull-in range, which cannot be demodulated in the prior art of -63743.

Since the peak after the correlator output exceeds the threshold is detected, the clock phase can be estimated with high accuracy.

[0043]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a demodulation device 100 according to the present invention. Demodulation device 100 of the present invention
Is largely the frequency error elimination circuit 20 and the carrier recovery circuit 40
Divided into

First, the frequency error removing circuit 20 will be described. The input signal r (t) is, as shown in FIG.
A unique word part and a data signal part are arranged before and after a frame, and a preamble is excluded. Compared with the input signal having the preamble shown in FIG. 8, the unique word length is slightly longer at about 24 to 40 symbols, but if the entire frame length is the same because the preamble is unnecessary, the data length should be increased. Can be.

This input signal is first supplied to the delay unit 1 for a time width t.
The complex conjugate is taken by the complex conjugator 2 after being delayed by c. Thereafter, the multiplier 3 multiplies the input signal that does not pass through the delay unit 1 and the complex conjugate unit 2 by complex to obtain an output d (t). d
(T) shows the delay unique word table 5 in the correlator 4.
Is cross-correlated with the unique word pattern that has been differentially detected and stored in the memory. The output c (t) of the correlator 4 is first converted into power by the power converter 6, and when it is detected by the comparator 7 that the output exceeds the threshold value, the peak detector 8 detects the output before and after that.
The maximum time TMAX between clocks is detected.
After the output of the correlation 4 at this time TMAX is latched by the latch circuit 9, it is converted into the phase θ by the phase detector 10, and divided by the time tc by the divider 11 to obtain the frequency error fe.

On the other hand, the input signal r (t) is accumulated in the buffer 12 for the length of the unique word, and is sequentially read from the head of the unique word in accordance with the output of the peak detector 8. The frequency error fe is removed using the output frequency error fe. The input signal from which the frequency error has been removed is a signal whose modulation component has been removed by the inverse modulator 15 using the unique word value of the output of the unique word table 14 according to the timing of the output of the peak detector 8 during the unique word section. In other than the unique word section, the signal is directly input to the carrier recovery circuit 40 and output as a demodulated signal.

Next, the operation of the embodiment of the frequency error elimination circuit 20 of the present invention will be described in detail with reference to FIGS.

The input signal r (t) includes a unique word u (t) which is a fixed pattern and has a frequency error f (t).
It has d and is represented by a complex number as two series of signals that are orthogonally detected asynchronously.

[0050]

Here, to represents the head time of the unique word, tu represents the unique word length, and P (t) represents random data other than the unique word part.

When this r (t) is input to the differential detection circuit composed of the delay unit 1, the complex conjugate unit 2, and the multiplier 3 in FIG. 1, the output d (t) becomes the following in the unique word section. Become like

[0053]

Here, * represents a complex conjugate. Also

[0055]

Is as follows. Correlation value c between d (t) and waveform u '(t) obtained by delay detection of the unique word pattern
(T) is output by the correlator 4. FIG. 3A shows the output c (t) of the correlator 4.

[0057]

From the equation (15), at time t = to + tu, that is, at the end of the unique word, the correlation completely matches, so the power of c (t) obtained at the output of the power converter 6 | c
(T) | 2 becomes a maximum (peak). The output | c (t) | 2 of the power converter 6 is shown in FIG. Therefore, after the output of the power converter 6 exceeds the threshold value in the comparator 7,
The output of the peak detector 8 that detects a peak at about one clock before and after that time is, as shown in FIG.
It will be output at to + tu.

Therefore, the latch circuit 9 latches the value of c (t) at t = to + tu.

[0060]

This value is converted to its phase θ by the phase detector 10 and divided by 2πtc by the divider 11 to obtain a frequency error fd as in the following equation.

[0062]

Actually, the relationship of fe = fd is obtained by the equation (19).
The phase θ is 2 due to the influence of noise and the like.
Since it does not completely coincide with πfd tc, the output of the divider 11 is represented by fe.

Next, since one of the input signals is sequentially stored in the buffer 12, it is read from the head of the unique word. Time to the end of the unique word by the peak detector to
Since + tu has been detected, the time to in the buffer data can be known therefrom, so that it is sequentially read from there. When the frequency shifter 13 shifts the frequency using the frequency error estimated value fe output from the divider 11, the output S (t) becomes as follows.

[0065]

Here, Δf = fd−fe, where fe is the estimation error and tb is the delay time due to the data buffer. This S (t) is stored in the content u (t) of the unique word table 14.
When the inverse modulation is performed by the inverse modulator 15 using

[0067]

The unique word part in the signal is a signal in which the frequency error is compressed to Δf with no modulation signal. Therefore, this signal can be easily demodulated by 16 carrier recovery circuits.

Next, FIG. 4 shows a specific configuration of the carrier recovery circuit 40 shown in FIG.

In FIG. 4, the output from the inverse modulator 14 in the frequency error elimination circuit 20 is first switched by the switch 41, and the input signal is selected as it is in the unique word section, and the output of the inverse modulator 42 is selected otherwise. Then, it is input to the next adaptive bright line enhancer 43. Since the output of 43 becomes a carrier component of the input signal, it is converted to a conjugate value by a complex conjugate unit 44 and then multiplied by the input signal by a multiplier 45 to obtain a demodulated signal. Used to inverse modulate the input signal.

Next, the operation of the carrier recovery circuit 40 will be described with reference to the drawings.

In FIG. 4, the switch 41 selects the unique word section so that the input signal from the frequency error removing circuit 20 is input to the adaptive bright line enhancer 43. This signal is a signal shown in Expression (21). The adaptive line enhancer 43 is an adaptive filter that adapts to the line component in the input signal and grows into a narrow-band bandpass filter (BPF) centered on its frequency. The signal, that is, the signal a (t) in which the carrier component is emphasized.

[0073]

The complex conjugate unit 44 outputs a conjugate value b (t) of this a (t).

[0075]

Therefore, the input signal w
Multiplying by (t) gives the output y (t)

[0077]

Thus, a demodulated signal is obtained.

When the input from the frequency error elimination circuit 20 is divided by the inverse modulator using the demodulated signal P (t) in a period other than the unique word section, the output g (t) becomes

[0080]

The signal is also a signal in which the modulation component has been removed from the input signal, and is input to the adaptive bright line enhancer 43 via the switch 41 to extract the carrier component.

In the above-described embodiment of the present invention, the configuration in which delay unit 1 delays one symbol is described.

However, the present invention is not limited to this delay time.

Hereinafter, as another embodiment, a demodulation device having another delay time will be described.

FIG. 5 is a block diagram showing another embodiment of the demodulator 100 of the present invention.

Here, the demodulation device 100 is mainly divided into a frequency error removal circuit 70 and a carrier recovery circuit 50.

The frequency error removing circuit 70 has the same configuration as that of the frequency error removing circuit 20 except for the delay circuit 60 and the divider 61.

Therefore, the delay circuit 60 and the divider 61 will be mainly described, and the description of the other components will be omitted.

As described above, the correlation value given by the equation (7) shows an ideal case where there is no noise component.

However, the actual received signal includes the noise signal θ.
Since n is included, the correlation value in this case is expressed as follows.

[0091]

Thus, the estimated frequency fe is

[0093]

In equation (28), the frequency error of the estimated frequency fe is

[0095]

## EQU10 ## This value can be reduced by increasing the delay time τ. However, τ
Becomes too large, the value of 2πfd τ exceeds π. In this case, correct frequency estimation cannot be performed.

As described above, τ has an upper limit as shown by the following equation.

[0098]

The delay time τ of the delay circuit 60 is set to such a value that the frequency error of the equation (29) can be ignored within a range satisfying the condition of the equation (30).

As described above, since the frequency error of the equation (29) becomes a small value,

[0101]

Can be obtained.

Various circuits can be applied as a specific configuration of the delay circuit 60. For example, as shown in FIG. 6, N delay units 1 of FIG. May be done.

In this case, N is selected so as to satisfy Expression (30).

Next, the divider 61 corresponds to the delay time τ of the delay circuit 60.

[0106]

Is divided by

On the other hand, the carrier recovery circuit 50 shown in FIG. 1 can be applied to the carrier recovery circuit 50 as it is. However, the carrier recovery circuit 40 has a disadvantage that the circuit configuration is complicated, though the allowable frequency error range of the input signal is wide.

Therefore, if the accuracy of frequency error estimation is increased by increasing the delay time τ of the delay circuit 60, a phase-locked loop (PLL) having a relatively simple configuration can be used without using the carrier recovery circuit 40. ) Type demodulator can be used in the carrier recovery circuit 50.

FIG. 7 is a block diagram of the carrier recovery circuit 50 when an appropriate delay time τ is set as described above, and shows a PLL type demodulator.

In the figure, the input signal w (t) is VC
The output of O52 is multiplied by a multiplier 51 to obtain a demodulated output y
(T) is obtained. The demodulated output y (t) is output from the phase error detector 54.
After the phase comparison with the reference signal, the loop filter 5
3, the VCO 52 is controlled.

[0112]

According to the result of simulation using the configuration of the present invention, the estimation accuracy of the clock phase is approximately ± 1/1 compared to the conventional demodulator described with reference to FIGS.
It has been found that the effect is improved from 2 clocks to ± 1/8 clocks, and the pull-in characteristics of the demodulator are hardly degraded thereafter.

Furthermore, according to the present invention, the frequency range that can be pulled in with a sufficiently high probability (95% or more) is about ± １ ／ to ± １ ／ of the symbol frequency compared to the conventional demodulator.
It has also been found that it has an effect that can be greatly expanded up to the present.

As a result, in the conventional satellite communication, a preamble is usually provided at the head of a signal. However, by using the technique of the present invention to abolish the preamble and lengthen the unique word, a sufficiently high speed and wide area are provided. This has the effect that a preambleless demodulator having a frequency range characteristic can be provided.

When the frequency offset of the input signal is not so large, the accuracy of frequency estimation can be improved by increasing the delay amount of the delay detector. Thus, a PLL type demodulator can be used, so that the circuit scale can be reduced, and the size and power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a demodulation device of the present invention.

FIG. 2 is a diagram illustrating an input signal r (t) of FIG.

FIG. 3 is a diagram showing a correlator output and a power converter output of FIG. 1;

FIG. 4 is a block diagram showing a carrier recovery circuit 40 of FIG. 1;

FIG. 5 is a block diagram showing another embodiment of the demodulation device of the present invention.

FIG. 6 is a block diagram of a delay circuit 60 of FIG. 5;

FIG. 7 is a block diagram showing a carrier recovery circuit 50 of FIG. 5;

FIG. 8 is a diagram illustrating a conventional input signal r (t).

FIG. 9 is a block diagram of a conventional unique word detector.

FIG. 10 is a block diagram of a conventional carrier recovery circuit.

[Explanation of symbols]

 Reference Signs List 1 delay device 2,44 complex conjugate device 3,45 complex multiplier 4 correlator 5 delay unique word table 6 power 7 comparator 8 peak detector 9 latch 10 phase detector 11 divider 12 buffer 13 frequency shifter 14,42 Inverse modulator 15 Unique word table 20 Frequency error elimination circuit 40 Carrier recovery circuit 41 Changeover switch 43 Adaptive bright line enhancer 100 Demodulator

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 27/227 H04J 3/06 H04L 7/08 H04L 27/14

Claims (7)

(57) [Claims] An input signal in which a unique word is inserted is delay-detected, and a correlation between the differential detection output and a data table obtained by delay-detecting the unique word is obtained. When the output power of the correlation exceeds a threshold, Detecting the maximum time, reading from the head of the unique word by the buffer storing the input signal based on the time, estimating the frequency error of the input signal based on the phase of the maximum correlation output, Obtaining a signal from which the frequency error has been removed from the read signal, performing inverse modulation on a unique word portion in the signal from which the frequency error has been removed according to data in a unique word table, and then performing carrier wave reproduction. Demodulator. 2. A delay detection circuit for delay-detecting an input signal in which a unique word is inserted, a correlator for correlating an output of the delay circuit with a pattern of the unique word being delayed-detected, and an output of the correlator. When the power exceeds a predetermined threshold, a peak detector that detects a time at which the power becomes maximum before and after that, and a phase of an output value of the correlator at a detection time of the peak detector output is obtained. A frequency error estimating circuit for estimating a frequency error of the input signal by dividing by a delay time of the delay detection circuit, and accumulating the input signal, and outputting the input signal from a unique word head based on the time of the peak detector output A frequency shifter for performing a frequency conversion of the buffer output according to the output of the frequency error estimating circuit; A first inverse modulator that performs inverse modulation using a unique word pattern stored in advance, and a carrier recovery circuit that outputs a demodulated signal by performing carrier recovery on the output of the inverse modulator. Characteristic demodulator. 3. The carrier recovery device according to claim 1, wherein the output of the first inverse modulator is output while the unique word portion is input.
Except for the unique word portion, a changeover switch for selecting an output of a second inverse modulator that performs inverse modulation based on a demodulated signal; and an adaptive bright line enhancement that receives the output of the changeover switch, adapts to the bright line component, and extracts a carrier. A complex conjugate for converting an output of the adaptive bright line enhancer to a complex conjugate value; a multiplication for multiplying an output of the complex conjugate and an output of the first inverse modulator to output the demodulated signal. 3. The demodulation device according to claim 1, wherein the demodulation device comprises a demodulator. 4. The demodulation device according to claim 1, wherein the input signal has the unique word part and the received data part arranged before and after, and has no preamble. 5. The delay time τ in the differential detection is increased in the range of τ <fd / 2, where fd is the frequency error, thereby increasing the estimation accuracy of the frequency error. 2. The demodulation device according to 2. 6. The demodulator according to claim 5, wherein when the delay time is increased to increase the estimation accuracy of the frequency error, a PLL demodulator is used for the carrier recovery. 7. The PLL type demodulator according to claim 1, wherein the input signal and the VC
A multiplier that multiplies and demodulates the O output, a phase error detector that compares the multiplier output with a demodulation reference phase, and a loop filter that filters the output of the phase error detector.
7. The demodulator according to claim 6, further comprising a VCO that outputs a reproduced carrier having a frequency corresponding to the output of the loop filter.