JP3181178B2 - Optical PNPN switch - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical PNPN switch. More specifically, the present invention relates to an optical PNPN switch having improved commutation characteristics when operating as a switch of an AC circuit.

[0002]

2. Description of the Related Art Some conventional optical PNPN switches have a chip structure as shown in FIGS. 5 shows a schematic pattern layout of the chip, and FIG. 6 shows a cross section taken along line CC of FIG. As shown in FIG. 5, this optical PNPN switch has an anode diffusion region (P type) on the surface side of an N type silicon substrate 101.
102, and a P gate diffusion region (P type) 103 facing the anode diffusion region 102 are provided on the upper side and the lower side in the figure, respectively, in left and right opposite states. In each P gate diffusion region 103, a cathode diffusion region (N type) 107 is provided.
Is provided. Thereby, the anode diffusion region 10
A PNPN portion is formed from 2 to the cathode diffusion region 107. For convenience, a path through which current flows from the upper right anode 102 to the upper left cathode 107 in FIG. 5 is ch (channel) 1, and a path through which current flows from the lower left anode 102 to the lower right cathode 107 is ch (channel). Call it 2. Between the P-gate diffusion region 103 of ch1 and the anode diffusion region 102 of ch2, the gate resistance (P-type) 106 on the ch1 side, and the P-gate diffusion region 1 of ch2
03 and the anode diffusion region 102 of ch1
Side gate resistance (P-type) 106 is formed. The cathode diffusion region 107 of ch1 and the anode diffusion region 102 of ch2, and the cathode diffusion region 107 of ch2 and the anode diffusion region 102 of ch1 are connected by Al pattern wiring (not shown). A bonding pad (shown by a broken line) 1
10 and 111 are provided, and these bonding pads 110 and 111 are connected to the lead frames T ₁ and T ₂ by Au wires 112 and 113. Reference numeral 109 denotes an N-type diffusion region provided around the chip as a channel stopper.

In this example, phototransistors Q ₃ and Q ₃ for improving the photosensitivity of ch1 and ch2 are provided along the periphery of the left side and the periphery of the right side of the chip, respectively. Each phototransistor Q ₃ includes a base diffusion region (P type) 104, an emitter diffusion region (N type) 108 formed in the base diffusion region 104, and an N type silicon substrate 101 functioning as a collector. I have.
Between the base diffusion region 104 and the emitter diffusion region 108 of the photo-transistor Q _3, as shown in FIG. 6, the base resistor 105 is present.

The equivalent circuit of the whole chip is ch1, ch1.
When the PNPN section of ch2 is represented by _two transistors Q ₁ and Q ₂ , for example, it is represented as shown in FIG.
When operating as a switch of an AC circuit, an AC voltage is applied to terminals T ₁ and T ₂ . For example than T ₁ side is T ₂ side and a positive potential (approximately 1.5V or higher). In this state,
When light in the chip surface (infrared light usually has a GaAs-based light-emitting diode emits) is incident, first phototransistor Q ₃ of ch1 side by contribution of photocurrent base region 104 occurs is turned on. Then, the PNP on the ch1 side
It will be to draw the base current of the transistor Q _1,
The PNP transistor Q ₁ is turned on. Then, by the collector current of the PNP transistor Q ₁ ch1
The base current of the side of the NPN transistor Q ₂ is supplied,
The NPN transistor Q ₂ is turned on. Then PN
P is supplied base current of the transistor Q _1, PNPN portion of ch1 side by the positive feedback is turned on, the on current corresponding to the load of the AC circuit from the terminal T ₁ to the terminal T _2. At this time, on the ch2 side, since the direction of the bias application is opposite, positive feedback of the PNPN section does not occur, and only the primary photocurrent flows. On the other hand, if than T ₂ side is T ₁ side in the positive potential,
Similarly, the PNPN section on the ch2 side performs positive feedback operation and turns on, and only the primary photocurrent flows on the ch1 side.

The impurity concentration of the N-type silicon substrate is usually 10 ¹³ to 10 ¹⁵ cm ⁻³ , the impurity concentration of each P-type diffusion region (boron or the like) is 10 ¹⁵ to 10 ¹⁹ cm ⁻³ , and the N-type diffusion region is Is set to 10 ²⁰ cm ⁻³ or more.

[0006]

By the way, as described above, bidirectional channels ch1 and ch2 are provided in one chip.
The element used as a switch of the AC circuit has
Commutation characteristics are an important evaluation criterion. In other words, in the normal operation, when the light is not incident during the half cycle of the alternating current in which ch1 is on, the on state continues due to the current holding characteristic of the PNPN section during this half cycle, but in the next half cycle, When entering, ch2 does not turn on unless there is light incidence. However, when an L load is present in the switching AC circuit, the phase of the ON current lags behind the phase of the AC voltage, so that a voltage showing a steep rise is applied to the ch2 side when the ch1 is turned off. Therefore, N
The holes remaining in the silicon substrate 101 move to the P gate diffusion region 103 and the base diffusion region 104 (see FIG. 5) on the ch2 side to promote the positive feedback action on the ch2 side,
2 may turn on (commutation failure).

In order to solve this problem, ch1 and ch
There has been known a device in which a two-chip is configured as a separate chip and a two-chip optical bi-directional PNPN switch is configured. However, in the case of a two-chip configuration, various problems occur. That is, in the step of arranging two chips on the same frame and die-bonding, both chips come into contact with each other, causing defects such as chipping and cracking. Further, if the distance between both chips is unnecessarily widened, the distance between both chips and the light emitting diode chip on the input side is widened, and the distance is varied. For this reason, there arises a problem that the minimum trigger current increases or variation occurs. In the case of a two-chip configuration, the peripheral area of each chip needs to be secured, so that the total chip size is larger than that of a one-chip configuration. In addition, the time and labor required for assembly are also increased. Therefore, there is a problem that the cost is high.

For example, regarding the separation of chips, “Oki Electric R & D” No. 131, Vol. 53, No. 3 (Showa 6)
On page 25 (July 1 July), a Si substrate on which elements have been formed in advance and a holding plate are heat-pressed with a resin, and then a cutting groove is formed from the Si substrate surface side to the resin portion using a dicing saw. Method to separate elements by using a canal separation method
Is disclosed. However, this method has the disadvantage that, as described above, extra work such as heating and press bonding between the Si substrate and the holding plate is required, and the cost is increased. Further, the cut groove separates a bidirectional element including ch1 and ch2 from a bidirectional element including ch1 and ch2 having the same configuration, and separates ch1 and ch2. It does not do. That is, it is not intended to improve the commutation characteristics of an element that performs AC switching.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an optical PNPN switch capable of performing AC switching with one chip and improving commutation characteristics.

[0010]

In order to achieve the above object, an optical PNPN switch according to the first aspect of the present invention includes an N-type or P-type silicon substrate having a conductivity type of one of N-type and P-type. An anode diffusion region having the other conductivity type of the P type, a gate diffusion region having the other conductivity type opposed to the anode diffusion region, and a cathode formed in the gate diffusion region and having the one conductivity type In an optical PNPN switch including a pair of PNPN sections each having a diffusion region, the pair of PNPN sections are provided on both sides in one direction of the substrate surface and are separated from each other, and the pair of PNPN sections are provided.
Between the PN portions, cut grooves having a depth that stops from the substrate surface into the substrate are formed, and the cut grooves have a depth of 3.
It is characterized in that it is set within the range of μm to 200 μm.

The optical PNPN switch according to the second aspect is the optical PNPN switch according to the first aspect,
Each of the above PNPNs is provided on the surface of the substrate on both sides of the cut groove.
A phototransistor for increasing the photosensitivity of the unit is provided.

[0012]

[0013]

In the optical PNPN switch according to the first aspect, since a pair of PNPN portions is provided on the front surface side of the silicon substrate, the pair of PNPN portions are connected in anti-parallel by wires or the like, so that one-chip AC switching is performed. Can be performed. In addition, the pair of PNPN portions are separated from each other, and a cut groove having a depth that stops from the surface of the substrate into the substrate is formed therebetween, so that the movement of the minority carrier in the silicon substrate is restricted by the cut groove. Is done. In addition, the side surface of the cut groove also has an effect of trapping and eliminating minority carriers. Therefore, for example, when ch1 is turned off, the minority carriers remaining in the silicon substrate on the ch1 side are less likely to move to the ch2 side. Accordingly, the positive feedback action on the ch2 side
Is turned on (commutation failure), and the commutation characteristics are improved.

In this optical PNPN switch, the depth of the cut groove is set in a range of 3 μm to 200 μm.

The reason why the depth of the cut groove is set to 3 μm or more is as follows. That is, channel stoppers are provided along both sides of the cut grooves in order to prevent a reduction in breakdown voltage due to surface inversion of the silicon substrate. Here, if the depth of the cut groove does not reach the depth of the channel stopper (usually set to 3 μm or more), the effect of restricting the movement of minority carriers in the silicon substrate is not exhibited. Therefore, the depth of the cut groove is preferably set to 3 μm or more so as to exceed the depth of the channel stopper.

The depth of the cut groove is set to 200 μm.
The reason for the following is as follows. That is, from the viewpoint of improving the commutation characteristics, it is necessary to consider the diffusion distance of minority carriers in the silicon substrate for the depth of the cut groove.
The diffusion distance of the minority carrier is determined depending on the impurity concentration and the crystallinity of the silicon substrate. In this type of optical PNPN switch, the impurity concentration of the silicon substrate is in the range of 10 ¹³ to 10 ¹⁵ cm ⁻³ , typically, in order to secure the junction breakdown voltage between the silicon substrate and the anode diffusion region and the gate diffusion region. It is set to about 10 ¹⁴ cm ^-3 . The crystallinity of a silicon substrate depends on heat treatment in a manufacturing process. As a result, the diffusion distance of minority carriers is about 200 μm. On the other hand, if a notch groove is present on the chip surface, when an external force is applied to the chip in the assembly process, the chip may be broken along the notch groove. Therefore, from the viewpoint of assembly, it is preferable that the depth of the cut groove is small. Therefore, the depth of the cut groove is preferably set to 200 μm or less.

In the optical PNPN switch according to the second aspect, the phototransistors for increasing the light sensitivity of each of the PNPN portions are provided on the substrate surfaces on both sides of the cut groove, so that the light sensitivity is increased. The minimum trigger current when combined with a light emitting diode can be reduced.

[0018]

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The optical PNPN switch according to the present invention will be described below in detail with reference to embodiments.

FIG. 1 shows a schematic pattern layout of an optical PNPN switch of one embodiment, and FIG.
FIG. 3 shows a cross section taken along line A-A of FIG. 1, and FIG. 3 shows a cross section taken along line BB of FIG.

As shown in FIG. 1, this optical PNPN switch includes an anode diffusion region (P-type) 2 on a surface side of an N-type silicon substrate 1 and a P-type region opposing the anode diffusion region 2.
A gate diffusion region (P-type) 3 is provided on the upper side 1a and the lower side 1b in the figure in left and right opposite states, respectively. Each P
In the gate diffusion region 3, a cathode diffusion region (N type) 7 is provided. Thereby, the upper part 1a of the chip,
In the lower part 1b, PNPN portions are formed from the anode diffusion region 2 to the cathode diffusion region 7, respectively.

The upper portion 1a and the lower portion 1b of the chip are formed with a notch groove 1 having a depth D which stops in the substrate from the substrate surface.
5 (see FIG. 3). For convenience, FIG.
In the upper part 1a, a path through which current flows from the right anode 2 to the cathode 7 in the upper part 1a is referred to as ch (channel) 1, and a path through which current flows from the left anode 2 to the cathode 7 in the lower part 1b is referred to as ch (channel) 2.

In this example, phototransistors Q ₃ and Q ₃ for improving the light sensitivity of ch1 and ch2 are provided in the upper part 1a and the lower part 1b of the chip, respectively. Each phototransistor Q ₃ has a P gate diffusion distance of 3
A base diffusion region (P-type) 4 provided on the side opposite to the anode diffusion region 2, an emitter diffusion region (N-type) 8 formed in the base diffusion region 4, and an N-type silicon substrate serving as a collector. 1 and 1. Between the base diffusion region 4 and the emitter diffusion region 8 of each phototransistor Q _3, as shown in FIG. 2, the base resistor 105
Exists.

As shown in FIG. 1, the upper part 1a and the lower part 1b of the chip each have a P
A gate diffusion region 3, a gate resistor (P-type) 6 is formed between the base diffusion region 4 of the phototransistor Q _3.

In the upper part 1a and the lower part 1b of the chip, as shown in FIG.
And the emitter diffusion region 8 are connected by an Al pattern wiring. Bonding pads (shown by broken lines in FIG. 1) 11a and 11b are provided on a part of the Al pattern wirings. In addition, each anode diffusion region 2 has Al
Pattern wiring is provided, and bonding pads 10a and 10b are provided in a part thereof. These bonding pads 10a and 11b are connected to Au wires 12a and 12b.
While connected to the lead frame T ₁ by the bonding pads 11a, 10b is Au wires 13a, 13
It is connected to the lead frame T ₂ by b.

In this example, the upper part 1 of the chip
a, N-type diffusion regions 9a and 9b are provided along the periphery of the lower portion 1b as channel stoppers. The N-type diffusion region 9a includes a portion 9ai along the upper side of the cut groove 15 and a portion 9ao along the periphery of the chip, and the N-type diffusion region 9b includes a portion 9bi along the lower side of the cut groove 15, And a portion 9bo along the periphery of the chip.

This optical PNPN switch is manufactured by a known method as follows.

First, as shown in FIG. 1, boron is diffused as a P-type impurity in the surface of an N-type silicon substrate 1 to form each anode diffusion region 2 and each P gate diffusion region 3 at the same time. The impurity concentration of the silicon substrate 1 is 10 ¹⁴ cm
It is about ^-3 .

Next, boron is diffused again as a P-type impurity in the surface of the N-type silicon substrate 1 to form each base diffusion region 4 and each gate resistor 6 at the same time.

Next, phosphorus is diffused as an N-type impurity into the surface of each P gate diffusion region 3 and the surface of each base diffusion region 4, and the cathode is diffused into each P gate diffusion region 3 and each base diffusion region 4. A region 7 and an emitter diffusion region 8 are formed. At the same time, an N-type diffusion region as a channel stopper is formed at the periphery and the center of the chip, that is, in a pattern of a substantially “sun” shape. At this stage, at the center of the chip, the N-type diffusion regions 9ai and 9bi are not vertically separated but continuous. The N-type diffusion regions 9a, 9
The depth of b is 3 μm as usual.

After heat treatment (at 800 ° C. for 30 minutes), an Al pattern wiring (not shown) is formed. Further, a protection film (not shown) is provided on the chip surface, and bonding pads 11a, 11b, 12a, 1
The portion corresponding to 2b and the portion on the N-type diffusion region as a channel stopper are removed.

After performing the wafer test, the center of the N-type diffusion region located at the boundary between the upper part 1a and the lower part 1b of the chip is half-diced, and the cut groove having a depth stopping in the substrate from the surface of the substrate. 15 are formed. The N-type diffusion regions 9ai and 9bi are vertically separated by the cut grooves 15.

Subsequently, full dicing is performed around the chips to separate the chips.

[0034] After the die bonding, while connecting the bonding pads 10a, 11b and the lead frame T ₁ Au wires 12a, by 12b, connecting the bonding pads 11a, 10b and the lead frame T ₂ Au wires 13a, by 13b I do.

As described above, by connecting the PNPN sections provided on the upper portion 1a and the lower portion 1b of the chip in anti-parallel, AC switching can be performed by one chip.

Further, since the cut groove 15 is formed between the PNPN portion of the upper portion 1a and the PNPN portion of the lower portion 1b, the cut groove 15 allows the positive carrier, which is a minority carrier in the N-type silicon substrate 1, to be formed. Hole movement is restricted. In addition, the side surface of the cut groove 15 also has an effect of trapping and eliminating holes. Therefore, for example, when ch1 is turned off, the holes remaining in the silicon substrate 1 on the ch1 side are less likely to move to the ch2 side. Therefore, c
A malfunction (commutation failure) in which ch2 is turned on by the positive feedback action on the h2 side can be suppressed, and the commutation characteristics can be improved.

FIG. 4 shows correlation data with commutation characteristics when the depth D of the cut groove 15 is actually changed. As can be seen from this figure, in the pattern layout shown in FIG. 1 (indicated by “〇” in the figure), the depth D of the cut groove 15 is 0 μm (no cut groove), 50
When the current was increased to μm or 100 μm, the current value at which commutation failed when the load was L (the optical PNPN switch normally operates if the current value is less than this value) could be increased. In addition,
As a matter of course, in the case where the cut grooves were deepened and separated into two chips (indicated by the mark “◎” in the figure), commutation failure did not occur. In addition, the pattern layout shown in FIG. 1 has improved commutation characteristics even without the cut groove 15 as compared with the pattern layout shown in FIG. 5 (indicated by a “●” mark in the figure). I have. This is presumably because the distance between the PNPN section of ch1 and the PNPN section of ch2 in FIG. 1 is longer than that in FIG.

The depth D of the cut groove 15 is preferably set to 3 μm or more which exceeds at least the depth of the channel stoppers 9ai and 9bi so as to exert the effect of restricting the movement of holes in the silicon substrate 1. preferable.

On the other hand, if the cut groove 15 exists on the chip surface, the chip may be broken along the cut groove 15 when an external force is applied to the chip in the assembly process. Therefore, from the viewpoint of assembly, it is preferable that the depth of the cut groove is small. Here, mainly as a result of the impurity concentration of the silicon substrate 1 of about 10 ¹⁴ cm ⁻³ and the heat treatment (at a temperature of 800 ° C. for 30 minutes), the hole diffusion distance becomes about 200 μm. Therefore, the silicon substrate 1
In consideration of the diffusion distance of the holes inside, the depth of the cut groove is 2
It is preferable to set the thickness to 00 μm or less.

In this embodiment, the conductivity type of the silicon substrate 1 is N-type, but is not limited to this. The conductivity type of the silicon substrate 1 may be P-type, and accordingly, the conductivity types of the other diffusion regions may be opposite to those of the above embodiment.

[0041]

As is apparent from the above description, the optical PNPN switch according to the first aspect is characterized in that the PNPN switch is provided on the surface side of the silicon substrate.
Since a pair of units is provided, by connecting the pair of PNPN units in anti-parallel with a wire or the like, AC switching can be performed with one chip. In addition, the pair of PNPN portions are separated from each other, and a cut groove having a depth that stops from the surface of the substrate into the substrate is formed therebetween, so that the movement of the minority carrier in the silicon substrate is restricted by the cut groove. Is done. In addition, the side surface of the cut groove also has an effect of trapping and eliminating minority carriers. Therefore, for example, when ch1 is turned off, c
Minority carriers remaining in the silicon substrate on the h1 side are less likely to move to the ch2 side. Therefore, a malfunction (commutation failure) in which ch2 is turned on by the positive feedback action on the ch2 side can be suppressed, and the commutation characteristics can be improved.

In this optical PNPN switch, since the depth of the cut groove is set in the range of 3 μm to 200 μm, the commutation characteristics can be effectively improved, and an external force is applied to the chip in the assembly process. At this time, chipping or chipping can be suppressed to a negligible level.

In the optical PNPN switch according to the second aspect, the phototransistors for increasing the light sensitivity of each of the PNPN portions are provided on the substrate surface side on both sides of the notch groove. Thus, the minimum trigger current when combined with a light emitting diode can be reduced.

[0044]

[Brief description of the drawings]

FIG. 1 is a plan view showing an optical PNPN switch according to an embodiment of the present invention.

FIG. 2 is a sectional view taken along line AA in FIG.

FIG. 3 is a sectional view taken along line BB in FIG. 2;

FIG. 4 is a diagram showing a relationship between a depth of a cut groove of the optical PNPN switch and a commutation characteristic.

FIG. 5 is a plan view showing a conventional optical PNPN switch.

FIG. 6 is a sectional view taken along line CC in FIG. 5;

7 is a diagram showing an equivalent circuit of the optical PNPN switch shown in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 N-type silicon substrate 2 Anode diffusion region 3 P gate diffusion region 4 Base diffusion region 7 Cathode diffusion region 8 Emitter diffusion region 15 Cut groove 9a, 9b
Channel stopper

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-2-125666 (JP, A) JP-A-51-7866 (JP, A) JP-A-58-31571 (JP, A) JP-A-5-131571 315603 (JP, A) JP-A-63-202969 (JP, A) JP-A-56-83083 (JP, A) JP-A-55-154765 (JP, A) (58) Fields investigated (Int. ⁷ , DB name) H01L 29/74 H01L 29/747 H01L 31/111

Claims (2)

(57) [Claims] 1. An anode diffusion region having the other conductivity type of N-type or P-type on a surface side of a silicon substrate having one conductivity type of N-type or P-type, and facing the anode diffusion region. An optical PNPN switch including a pair of PNPN portions each having a gate diffusion region having the other conductivity type and a cathode diffusion region formed in the gate diffusion region and having the one conductivity type. A notch groove having a depth stopping in the substrate from the substrate surface is formed between the pair of PNPN portions, and a depth of the notch groove is formed between the pair of PNPN portions. The optical PNPN switch is set within a range of 3 μm to 200 μm. 2. The optical PNPN switch according to claim 1, wherein each of the PNPNs is provided on the substrate surface on both sides of the cut groove.
An optical PNPN switch, characterized in that a phototransistor for increasing the light sensitivity of the unit is provided.