JP3179792B2 - マルチ・ポート・ランダム・アクセス・メモリ - Google Patents

マルチ・ポート・ランダム・アクセス・メモリ

Info

Publication number
JP3179792B2
JP3179792B2 JP06495291A JP6495291A JP3179792B2 JP 3179792 B2 JP3179792 B2 JP 3179792B2 JP 06495291 A JP06495291 A JP 06495291A JP 6495291 A JP6495291 A JP 6495291A JP 3179792 B2 JP3179792 B2 JP 3179792B2
Authority
JP
Japan
Prior art keywords
signal
data
port
flip
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP06495291A
Other languages
English (en)
Japanese (ja)
Other versions
JPH04212778A (ja
Inventor
尚徳 浜野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP06495291A priority Critical patent/JP3179792B2/ja
Priority to DE4122060A priority patent/DE4122060A1/de
Publication of JPH04212778A publication Critical patent/JPH04212778A/ja
Application granted granted Critical
Publication of JP3179792B2 publication Critical patent/JP3179792B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Dram (AREA)
JP06495291A 1990-07-04 1991-03-28 マルチ・ポート・ランダム・アクセス・メモリ Expired - Fee Related JP3179792B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP06495291A JP3179792B2 (ja) 1990-07-04 1991-03-28 マルチ・ポート・ランダム・アクセス・メモリ
DE4122060A DE4122060A1 (de) 1990-07-04 1991-07-03 Multi-port-speicher mit wahlfreiem zugriff fuer hochgeschwindigkeitsdatenverarbeitung und zugriffsverfahren auf einen solchen

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP17829090 1990-07-04
JP2-178290 1990-07-04
JP06495291A JP3179792B2 (ja) 1990-07-04 1991-03-28 マルチ・ポート・ランダム・アクセス・メモリ

Publications (2)

Publication Number Publication Date
JPH04212778A JPH04212778A (ja) 1992-08-04
JP3179792B2 true JP3179792B2 (ja) 2001-06-25

Family

ID=26406100

Family Applications (1)

Application Number Title Priority Date Filing Date
JP06495291A Expired - Fee Related JP3179792B2 (ja) 1990-07-04 1991-03-28 マルチ・ポート・ランダム・アクセス・メモリ

Country Status (2)

Country Link
JP (1) JP3179792B2 (enExample)
DE (1) DE4122060A1 (enExample)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6072020A (ja) * 1983-09-29 1985-04-24 Nec Corp デュアルポ−トメモリ回路

Also Published As

Publication number Publication date
JPH04212778A (ja) 1992-08-04
DE4122060A1 (de) 1992-01-16
DE4122060C2 (enExample) 1993-08-05

Similar Documents

Publication Publication Date Title
US4807189A (en) Read/write memory having a multiple column select mode
US5590083A (en) Process of writing data from a data processor to a memory device register that is separate from the array
US5001672A (en) Video ram with external select of active serial access register
US4961171A (en) Read/write memory having an on-chip input data register
US5726947A (en) Synchronous semiconductor memory device suitable for graphic data processing
JP3046075B2 (ja) デュアルバンクメモリおよび同メモリを用いたシステム
US4646270A (en) Video graphic dynamic RAM
US5808958A (en) Random access memory with latency arranged for operating synchronously with a micro processor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock
US5282177A (en) Multiple register block write method and circuit for video DRAMs
US4106109A (en) Random access memory system providing high-speed digital data output
JP2645529B2 (ja) フラッシュライト機能を備えた半導体記憶装置
US5148524A (en) Dynamic video RAM incorporating on chip vector/image mode line modification
JPH059872B2 (enExample)
US5065368A (en) Video ram double buffer select control
KR940006362B1 (ko) 반도체 기억장치와 그 동작방법
JPH04243085A (ja) 半導体記憶装置
US5146430A (en) Self-refresh system for use in a field memory device
US4811305A (en) Semiconductor memory having high-speed serial access scheme
JPH04228172A (ja) 半導体メモリ
JP2593060B2 (ja) ダイナミックランダムアクセスメモリ、ダイナミックランダムアクセスメモリのアクセス方法及びシステム
US4891795A (en) Dual-port memory having pipelined serial output
JPS61288240A (ja) 半導体記憶装置
JP3179792B2 (ja) マルチ・ポート・ランダム・アクセス・メモリ
KR950004743B1 (ko) 멀티 포트 랜덤 액세스 메모리 및 액세스방법
JPS6151792B2 (enExample)

Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20010403

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees