JP3173390B2 - LSI tester - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an LSI tester, and more particularly, to a pin electronics such as a driver and a comparator mounted on the LSI tester.

[0002]

2. Description of the Related Art Conventionally, in an LSI tester, a pin element LSI in which one driver and one comparator are incorporated is provided in a test head in the test head by the number of pins of a memory to be measured (hereinafter, referred to as DUTM). A test for the DUTM is performed by mounting it on a board and connecting the pins of the pin element LSI and the DUTM.

Hereinafter, a conventional LSI tester will be described in detail with reference to the drawings.

FIG. 5 is a block diagram showing a configuration example of a conventional LSI tester.

[0005] In this conventional example, as shown in FIG.
9-1 to DUTM59-n, a memory tester main body 51 for controlling a test, and DUTM59-1 to DUTM5
9-n, and the DUTM59-1 to DUTM59-
test data that exchanges test data with
A head 52 is provided with an ALPG 54 for generating a test pattern.
A fail memory 55 for storing data of defective bits in the DUTM 59-1 to DUTM 59-n;
The operation of the memory tester main body 51 is controlled and the DU is controlled.
A CPU 56 to which test results in the TM 59-1 to DUTM 59-n are input is provided. The test head 52 includes a driver and a comparator, one for each pin. A plurality of pin elements LSI 53-1 to 53-3 provided in
-N, a timing generator 57 for generating a timing signal for a test, and a pattern output from the ALPG 54 and a timing signal output from the timing generator 57, and combined with each other. N
Formatter / pin matrix 58 for output to
Are provided.

The operation of the LSI tester configured as described above will be described below.

First, when the test pattern is output from the ALPG 54 and the timing signal for the test is output from the timing generator 57, the formatter / pin matrix 58 outputs the pattern output from the ALPG 54 and the timing generation. DUTM 59-1 to DUTM based on the timing signal output from the unit 57.
An address, a clock and input data applied to each of the pins 59-n are generated, and the pin elements LSI 53-1 to 53-n are generated.
Output to 53-N.

Then, the pin electronics LSI 53-1 to 53
In the driver provided in each of -DUM 59-1 to DUTM 59-n, a signal output from the formatter / pin matrix 58 is set to an arbitrary "H" level / "L" level potential. Applied to each pin.

After 10 to 20 ns, DUTM5
Data output from 9-1 to DUTM59-n is determined by a comparator in the pin element LSI 53,
The determination result is transferred to the CPU 56, and the DUTM 59-1 to DUTM 59-1 are transmitted.
The quality of the DUTM59-n is determined.

[0010]

However, the above-described conventional LSI tester has the following problems.

(1) Since the number of pin elements LSI is required as many as the number of DUTM pins, for example, when testing 32 40-pin DUTMs in parallel with one test head,
1280 pin element LSIs are required,
The head becomes large.

(2) Since the number of the pin elements LSI is required as many as the number of pins of the DUTM, if the number of pins of the DUTM increases, the distance between the pin elements LSI and the DUTM increases, and the number of the pin elements LSI and the DUTM increases. And the signal transmission efficiency between the
Input / output switching time in SI increases, and 2
High-frequency measurement of 50 MHz or more cannot be performed.

FIG. 6 is a diagram showing a measurement frequency limit with respect to a distance between a pin / ele LSI and a device under test in an LSI tester.

As shown in FIG. 6, when the distance between the pin element LSI and the device under test increases, the measurement frequency limit decreases, and high-frequency measurement becomes impossible.

(3) Pin element L for each pin of DUTM
Since a single SI is provided, when a different waveform is input for each pin, the junction temperature differs for each pin and the LSI, resulting in a difference in the current capability of the transistor, and a skew accuracy between the pins of the DUTM. Will decrease.

The present invention has been made in view of the above-mentioned problems of the prior art, and does not increase the size of the test head even when the number of pins of the DUTM to be tested is large. Also, Pin-Ele LSI and DU
Provided is an LSI tester capable of improving signal transmission efficiency between a TM and a DUTM and supplying a waveform having almost no skew time at each pin even when a different waveform is required for each pin of the DUTM. With the goal.

[0017]

In order to achieve the above object, according to the present invention, a driver and a comparator mounted on a test head of an LSI tester are incorporated in one package for each pin of a device under test. Rather, it is built into one package for each device under test.

More specifically, a driver for supplying a signal for a test to the device under test and a comparator for judging an output signal from the device under test are respectively provided with the same number of pins as the number of pins of the device under test. In the LSI tester, the driver and the comparator have one
It is characterized by being incorporated in one package.

Also, the tester has a memory tester main body for controlling a test on the device under test, and a test head for exchanging test data with the device under test. Pattern generating means for generating a test pattern for the measurement object, storage means for storing data of defective bits in the object to be measured,
A driver for controlling the operation of the memory tester main body and receiving a test result on the device under test, wherein the test head supplies a signal for testing to the device under test And driver / comparators each having the same number of built-in comparators as the number of pins of the device under test, and a timing generator for generating a timing signal for testing the device under test And a formatter / pin matrix for synthesizing a pattern output from the pattern generator and a timing signal output from the timing generator and outputting the synthesized signal to the driver / comparator. ,
The driver / comparator, the timing generator, and the formatter / pin matrix are included in one package for each device under test.

Further, the apparatus has a logic tester main body for controlling a test on the device under test, and a test head for exchanging test data with the device under test. A driver that is provided as many as the number of pins of the object and supplies a signal for a test to the device under test, and a driver that is provided as many as the number of pins of the device under test,
A comparator that determines an output signal from the device under test, a pattern generating unit that is provided in the same number as the number of pins of the device under test, and generates a test pattern for the device under test; The same number of timing generators that generate timing signals for testing the device under test, and the same number of pins as the number of pins of the device under test, and the number of pins output from the pattern generation unit and the timing generator In an LSI tester comprising a formatter for synthesizing the output timing signal and outputting the synthesized signal to the driver, the driver and the comparator are incorporated in one package for each device under test. It is characterized by.

Also, the apparatus has a logic tester main body for controlling a test on the device under test, and a test head for exchanging test data with the device under test. A driver / comparator in which a driver for supplying a signal for a test to the object and a comparator for judging an output signal from the object to be measured have the same number of pins as the number of pins of the object to be measured; Pattern generating means for generating a test pattern for the device under test, and a pattern generating means for providing a number of pins for the device under test and generating a timing signal for testing the device under test A timing generator, a number of pins equal to the number of pins of the device under test, and a pattern output from the pattern generator and the timing generator; An LSI tester comprising a formatter for synthesizing the timing signal output from the controller and outputting the synthesized signal to the driver / comparator, wherein the driver / comparator, the pattern generation means, the timing generator, and the formatter include: The device is built in one package for each device under test, and is used for testing the device under test.
A timing generator for generating a timing signal;
A pattern that generates a test pattern for the DUT
Generating means; and a pattern output from the pattern generating means.
And the timing output from the timing generator
The signal is combined with the signal and sent to the driver and the comparator.
Output formatter / pin matrix
And the driver, the comparator, and the timing
The generator and the formatter / pin matrix are
One package for each DUT
It is characterized by.

(Operation) In the present invention configured as described above, the driver and the comparator mounted on the test head of the LSI tester are not built in one package for each pin of the device under test. Since each device under test is contained in a single package, ICs such as pin electronics LSIs, etc., can be packaged in the test head.
, The test head is smaller, and the floor area is smaller. At the same time, Pin Ele LS
The distance between I and the device under test is reduced, the signal transmission efficiency is improved, and the input /
Output switching time is shortened, and high-frequency measurement can be performed.

Further, since a driver and comparator for all pins of one device under test are built in one pin element LSI, a different waveform is applied to each pin of one device under test. In this case, a waveform having almost no skew time is supplied to each pin.

[0024]

Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1A and 1B are block diagrams showing an embodiment of an LSI tester according to the present invention. FIG. 1A is a diagram showing the entire configuration, and FIG. 1B is a block diagram of the driver / comparator 11 shown in FIG. FIG. 3 is a circuit diagram showing an internal configuration.

In this embodiment, as shown in FIG. 1, a memory tester main body 1 for controlling a test on a DUT 9-1 to DUTM 9-n, which is a device under test, and a DUTM 9-1 to DUT 9-1.
M9-n, and a test head 2 for exchanging test data with DUTM9-1 to DUTM9-n, and a memory tester. The main body 1 includes an ALPG 4 which is a pattern generating means for generating a test pattern,
Fail memory 5 which is storage means for storing data of defective bits in DUTM 9-1 to DUTM 9-n
To control the operation of the memory tester body 1 and D
A CPU 6 to which test results in the UTM9-1 to DUTM9-n are input;
Drivers / comparators 11-1 to 11-n in which the number of pins of the DUTM 9-1 to DUTM 9-n is built in each of 3-1 to 3-n, Generators 7-1 to 7-n for generating timing signals for
Pattern output from PG4 and timing generator 7-
Combining the timing signals output from 1 to 7-n,
Formatter / pin matrix 8-1 for outputting to drivers / comparators 11-1 to 11-n, respectively
To 8-n.

The operation of the LSI tester configured as described above will be described below.

FIG. 2 is a timing chart for explaining the operation of the LSI tester shown in FIG.

First, when the address, clock and input data patterns are output from the ALPG 4 and timing signals for testing are output from the timing generators 7-1 to 7-n, the formatter / pin matrix 8
-1 to 8-n, based on the pattern output from the ALPG 4 and the timing signal output from the timing generators 7-1 to 7-n, the DUTM 9-1 to the DUT 9-1.
Timing waveforms applied to each pin of M9-n are respectively generated, and the driver / comparators 11-1 to 11-11 are generated.
/ N.

Then, the driver / comparator 11-1
11-n, the formatter / pin matrices 8-1 to 8-
n is set to an arbitrary “H” level / “L” level potential, and DUTM9-1 to DUTM9-
n is applied to each pin.

As shown in FIG. 2, in the first cycle, "H" level input data is applied to DUTM 9-1.
"L" level input data is written into UTM9-n, respectively.
-1 and "H" level input data are written into the DUTM9-n, respectively.
In the cycle, “L” level output data is read from the DUTM 9-1 and “H” level output data is read from the DUTM 9-n. The comparator 13 makes a determination, and the determination result is transferred to the CPU 6. DUT
The pass / fail judgment of M9-1 to DUTM-n is performed. In addition,
At the time of reading in the third cycle, the driver 12 has the “H” impedance.

In this way, the DUTM 9-1 to DUTM 9-1
The test for each of M9-n is performed in parallel.

(Other Embodiments) FIG. 3 shows an LS of the present invention.
FIG. 10 is a block diagram showing another embodiment of the I tester,
FIG. 3A is a diagram illustrating the entire configuration, and FIG. 3B is a diagram illustrating the internal configuration of the pin element LSI 33 illustrated in FIG.

As shown in FIG. 3, the present embodiment is different from the one shown in FIG. 1 in that only the driver 3C and the comparator 3D are built in the pin element LSI 33. Degrees are easier to implement.

FIG. 3 shows a logic tester, which includes a pattern generator 34 and a timing generator 37.
The formatter 38 is of a per-pin type.

FIG. 4 is a block diagram showing another embodiment of the LSI tester of the present invention.

In the one shown in FIG.
Pin electronics LSI4 provided for each of -1 to 49-n
In 3-1 to 43-n, a pattern generator 44, a timing generator 47, a formatter 48, and a driver / comparator 4B have a DUTM 49- as a per-pin configuration.
1 to 49-n pins are mounted.

[0038]

Since the present invention is constructed as described above, it has the following effects.

(1) The driver and comparator mounted on the test head of the LSI tester are not built in one package for each pin of the device under test, but are built in one package for each device under test.・ ICs such as pin / ele LSI which become packages to be mounted on the head
Can be reduced, the test head can be miniaturized, and the floor area can be reduced. At the same time, the distance between the pin element LSI and the device under test can be reduced, signal transmission efficiency can be improved, and the input / output switching time in a test on the device under test can be reduced, enabling high-frequency measurement. .

(2) Since drivers and comparators for all pins of one device under test are built in one pin element LSI, different waveforms are generated for each pin of one device under test. Even when the voltage is applied, the junction temperature of the driver and the comparator connected to one device under test becomes the same, and the skew time between the pins can be greatly reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an LSI tester according to the present invention, in which FIG.
FIG. 3 is a circuit diagram showing an internal configuration of the driver / comparator shown in FIG.

FIG. 2 is a timing chart for explaining the operation of the LSI tester shown in FIG.

FIG. 3 is a block diagram showing another embodiment of the LSI tester according to the present invention, wherein FIG.
FIG. 2B is a diagram showing an internal configuration of the pin element LSI shown in FIG.

FIG. 4 is a block diagram showing another embodiment of the LSI tester of the present invention.

FIG. 5 is a block diagram illustrating a configuration example of a conventional LSI tester.

FIG. 6 is a diagram showing a measurement frequency limit with respect to a distance between a pin / ele LSI and a device under test in an LSI tester.

[Explanation of symbols]

1 Memory tester main body 2, 32, 42 Test head 3-1 to 3-n, 33-1 to 33-n, 43-1 to 43
-N pin-ele LSI 9-1 to 9-n, 39-1 to 39-n, 49-1 to 49
−n DUTM 3C, 12 Driver 3D, 13 Comparator 4 ALPG 4B, 11-1 to 11-n Driver / Comparator 5 Fail memory 6, 36, 46 CPU 7-1 to 7-n, 37, 47 Timing generator 8 -1 to 8-n formatter / pin matrix 31, 41 Logic tester body 38, 48 formatter

Claims (4)

(57) [Claims] A memory tester main body for controlling a test on the device under test; and a test head for exchanging test data with the device under test. Pattern generating means for generating a test pattern for the test object; storage means for storing data of defective bits in the test object; and controlling the operation of the memory tester main body and the test result in the test object. The test head comprises a driver for supplying a signal for a test to the device under test, and a comparator for determining an output signal from the device under test. A driver / comparator built in the same number as the number of pins of the device, and a timing signal for testing the device under test An imming generator, and a formatter / pin matrix for synthesizing the pattern output from the pattern generator and the timing signal output from the timing generator and outputting the synthesized signal to the driver / comparator. In the LSI tester, the driver / comparator, the timing generator, and the formatter / pin matrix are included in one package for each device under test. 2. A logic tester main body for controlling a test on a device under test, and a test head for exchanging test data with the device under test, wherein the test head comprises: A driver that is provided as many as the number of pins of an object and supplies a signal for a test to the device under test; and a driver that is provided as many as the number of pins of the device under test and determines an output signal from the device under test. A comparator; a pattern generation unit that is provided in the same number as the number of pins of the device under test and generates a test pattern for the device under test; A timing signal generator for generating a timing signal for generating a timing signal, the number of pins being equal to the number of pins of the device under test, a pattern output from the pattern generating means, and the timing generator It combines the output timing signals from, formed by and a formatter configured to output to the driver LS
In the I tester, the driver and the comparator are incorporated in one package for each device under test. 3. A tester for controlling a test on a device under test, comprising: a main body of a logic tester; and a test head for exchanging test data with the device under test. A driver / comparator in which a driver for supplying a signal for a test to the object and a comparator for judging an output signal from the object to be measured are provided in the same number as the number of pins of the object to be measured; Pattern generating means for generating a test pattern for the device under test, the same number as the number of pins of the device to be measured, and a timing signal for testing the device to be measured provided with the same number of pins as the device to be measured A timing generator, the same number of pins as the number of pins of the device under test, a pattern output from the pattern generator, and the timing generator An LSI tester comprising a formatter for synthesizing the timing signal output from the controller and outputting the synthesized signal to the driver / comparator.
An LSI tester wherein the timing generator and the formatter are incorporated in one package for each of the devices under test. 4. An LSI tester having a driver for supplying a signal for a test to a device under test and a comparator for determining an output signal from the device under test, each of which has the same number of pins as the device under test. The driver and the comparator are included in one package for each of the device under test, a timing generator that generates a timing signal for testing the device under test, and a test pattern for the device under test. Pattern generating means for generating, and a formatter / pin matrix for synthesizing a pattern output from the pattern generating means and a timing signal output from the timing generator and outputting the synthesized signal to the driver and the comparator. The driver, the comparator, the timing generator, and the formater. Data / pin matrix, LSI tester, characterized in that said built into a single package for each object to be measured.