JP3173026B2 - Deflection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a deflection device used for a monitor receiver or the like.

[0002]

2. Description of the Related Art In a vertical synchronization processing circuit of a deflecting device used in a monitor receiver or the like, an apparatus has been proposed which counts horizontal synchronization signals and generates a vertical synchronization timing signal or the like from the counted value (countdown processing). ing. Further, in a deflection correction waveform generation circuit used for a monitor receiver or the like, an apparatus has been proposed which generates a sawtooth wave, a parabolic wave, or the like as a correction waveform using a count value of a horizontal synchronization signal.

However, in the conventional apparatus, the count value of the horizontal synchronizing signal used in the deflection correction waveform generation circuit is counted independently from the original horizontal synchronizing signal using a counter IC or the like. There are many structural wastes, such as an increase in scale, and various problems have occurred.

[0004]

The problem to be solved is that, in the conventional apparatus, a counter is provided in each of the vertical synchronization processing circuit and the deflection correction waveform generation circuit to increase the circuit scale. There is much waste.

[0005]

According to the present invention, when a vertical synchronizing signal included in a supplied video signal is detected,
Generates a timing pulse for vertical deflection synchronized with the vertical synchronization signal.
Is added to the interpolated vertical sync signal from the missing vertical sync signal.
In deflection apparatus order to generate a timing pulse synchronized with a vertical deflection, the deflection device, the video signal
It is determined that the period of the vertical synchronization signal of
In the standard mode or when the period of the vertical sync signal
Non-standard mode or non-standard mode
Is one of the no-signal modes that are determined to be no-signal
In order to operate in the operation mode of
The deflection mode is reset to the initial value and
After the de is with the non-standard mode, the a software repeatedly activated at a period of an integer multiple of the frequency of the horizontal frequency, it is determined whether or not the vertical synchronization signal of at least the video signal has been detected 1 and of the procedure, the first of
The vertical sync signal of the video signal was not detected in the procedure
If the by have you, the operation mode of the deflection device, the standard
Mode, the above non-standard mode, or
Is a second procedure for determining whether the mode is the no-signal mode, and the operation mode of the deflecting device is standard in the second procedure.
If it is determined that the mode is the mode,
It corresponds to the number of times the software is started within one vertical cycle.
The count value is compared with the predetermined setting value.
If the value is above the set value, reset the above count value ,
If not, the operation mode of the deflecting device is changed by the third procedure for increasing the count value by a constant value and the second procedure.
If it is determined that the mode is the non-standard mode,
Numerical value of the window showing the period for detecting the vertical sync signal
Compared to the upper limit, the count value is the upper limit of the window
If the value is greater than or equal to the value, reset the above count value.
If not, a fourth step to increase the above count value by a fixed value
And the operation mode of the deflection device in the second procedure
If it is determined that the mode is the signal mode,
The value is compared with the predetermined set value, and the count value
Reset the above count value if it is more than the set value
Otherwise, increase the above count value by a fixed value.
A fifth procedure, and a vertical procedure of the video signal in the first procedure.
Synchronization signal is have you when it is detected, movement of the deflector
Operation mode is the standard mode or the non-standard mode
Mode or the no-signal mode described above.
A sixth procedure to separate the deflecting device in the sixth procedure.
If the operation mode is determined to be the standard mode,
And the counted value is compared with the predetermined set value.
If it is equal to the set value, reset the above count value,
Otherwise, increase the count value by a fixed value.
Step 7 and the operation mode of the deflecting device in the sixth step.
If the mode is determined to be in non-standard mode,
Compare the count value with the lower limit of the window and
If the numerical value is smaller than the lower limit of the above window,
Increase the count by a fixed value, otherwise
Update the window and reset the above count
The operation mode of the deflecting device is described in the eighth procedure and the sixth procedure.
If the mode is determined to be in the no-signal mode,
A ninth operation mode for setting the operation mode of the deflection device to a non-standard mode
In the procedure and the third procedure, the count value is equal to or less than the predetermined value.
If it is determined that the position is above the predetermined number of times,
A tenth procedure for setting the operation mode of the device to the standard mode;
In the fourth procedure, the count value is equal to or less than the upper limit of the window.
If it is determined that the position is above the predetermined number of times,
A storage unit storing software including an eleventh procedure for setting the operation mode of the device to the no-signal mode, and generating the timing pulse for vertical deflection by executing the software stored in the memory. A vertical synchronization processing circuit 100 having an arithmetic unit, memories storing data and coefficients (ROM 23 and RAM 24), and multiplying the data and coefficients stored in the memory at every timing of multiplying the horizontal synchronization signal. A multiplier (27);
An adder (30) for adding a multiplication result from the multiplier or a coefficient stored in the memory and a previously calculated operation result or a reset value, and controls operations of the multiplier, the adder, and the memory; Control means (ROM and R
AM22), a count value (X) obtained by counting the horizontal synchronizing signal is supplied, and a deflection correction waveform generation circuit 2 that repeatedly performs a calculation from the count value using the multiplier and the adder.
And supplies the count value obtained by the vertical synchronization processing circuit to the deflection correction waveform generation circuit (register 30).
0) yields the desired higher order equation [Y _SAW = (CX ³ +
DX ² + X) B + A: Y _PARA = (GX ⁴ + X ² + HX)
FB ² + E].

[0006]

According to this, by supplying the count value obtained by the vertical synchronization processing circuit to the deflection correction waveform generation circuit and performing the calculation, a correction waveform having a desired higher-order equation can be obtained with a simple configuration. A deflection device can be formed.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In FIG. 1, reference numeral 100 denotes a vertical synchronization processing circuit. In the vertical synchronization processing circuit 100, a timing signal of twice the horizontal frequency (2f _H ) and a clock signal of 4 MHz are supplied to the instruction address generator 1. The address generated by the generator 1 is supplied to an instruction (I) ROM and a RAM 2, and a signal generated by the ROM and the RAM 2 is used to generate an R signal for data.
OM3 and RAM4, instruction decoder 5
Supplied to

The output of the ROM 3 is supplied to a bus line 6 and to an adder 8 via a selector 7. The output of the RAM 4 is supplied to the adder 8. The output of the adder 8 is supplied to an accumulator (ACC) 9, and the output of the accumulator 9 is supplied to the RAM 4 via the bus line 6 and to the adder 8 via the selector 7.

The operation of the selector 7, adder 8, and accumulator 9 is controlled by a signal from the instruction decoder 5. The signal from the accumulator 9 and the vertical synchronizing signal are supplied to a jump command generator 10, and the jump command from the generator 10 is supplied to the instruction address generator 1. Then, in this circuit, a software operation shown in a flowchart described later is performed, and the operation result is taken out to the registers 11 and 12.

Reference numeral 200 denotes a deflection correction waveform generation circuit. In the deflection correction waveform generating circuit 200, a timing signal of twice the horizontal frequency (2f _H ) and a clock signal of 4 MHz are applied to the instruction address generator 21.
Supplied to The value generated by the generator 1 is supplied to an instruction (I) ROM and a RAM 22, and the output of the ROM and the RAM 22 is converted to a ROM 2 for data.
3 and an address input to the RAM 24 and supplied to the instruction decoder 25.

The output of the ROM 23 is supplied to a multiplier 27 and a register 28 via a bus line 26. The output of the RAM 24 is supplied to the multiplier 27. The outputs of the multiplier 27 and the register 28 are selected by the selector 29 and supplied to the adder 30. Furthermore, this adder 3
0 is output to the first and second accumulators (ACC) 3
1, 32. The output of the accumulator 32 is supplied to the adder 30 and the accumulator 31
Is output from the RAM 24 and the multiplier 2 via the bus line 26.
7 and the register 28.

The multiplier 27 and the register 2
8, selector 29, adder 30, accumulator 31,
The operation of 32 is controlled by a signal from the instruction decoder 25. Then, in this circuit, a software operation shown in a program list described later is performed, and the operation result is taken out to the registers 33 and 34.

In this device, a count value (X) obtained by counting a timing signal of twice the horizontal frequency (2f _H ) counted by the vertical synchronization processing circuit 100 is supplied to the register 300 via the bus line 6, This register 300
Is supplied to the RAM 24 via the bus line 26 of the deflection correction waveform generation circuit 200.

FIG. 2 shows a flowchart of an example of the software stored in the instruction (I) ROM and the RAM 2. In this figure, this software is started (started) at a cycle of twice the horizontal frequency (2f _H ). When the process is started, first, in step [1], it is determined whether or not the period is the period of the vertical synchronizing signal. If it is not the period of the vertical synchronizing signal (NO), the standard / non-standard / no signal mode is determined in step [2]. This step [2] is determined by a flag described later.

In the standard mode in step [2], the count value (X) is set to a predetermined value (Tstm) in step [3].
It is determined whether or not X ≧ Tstm. If X ≧ Tstm is not satisfied (NO), the count value (X) is incremented by 1 in step [4], and X ≧ Tstm is satisfied (YE
At S), the count value (X) is reset to 0 in step [5]. Thereafter, the flowchart is stopped.

If the mode is the non-standard mode in step [2], it is determined in step [6] whether the count value (X) satisfies X ≧ Wmax with respect to an upper limit value (Wmax) of a window to be described later. Is done. If X ≧ Wmax is not satisfied (NO), the count value (X) is incremented by 1 in step [7], and X ≧
If it is Wmax (YES), the count value (X) is reset to 0 in step [8]. Thereafter, the flowchart is stopped.

Further, if no signal mode is selected in step [2], step

In [9], the count value (X) becomes a predetermined value (Tstm
), It is determined whether or not X ≧ Tstm.
If X ≧ Tstm is not satisfied (NO), step [1]
In [0], the count value (X) is incremented by 1. If X ≧ Tstm is satisfied (YES), the count value (X) is reset to 0 in step [11]. Thereafter, the flowchart is stopped.

On the other hand, if it is the period of the vertical synchronizing signal in step [1] (YES), the standard / non-standard / no signal mode is determined in step [12] in the same manner as in step [2] described above. You. When the mode is the standard mode in step [12], it is determined in step [13] whether or not X = Tstm between the count value (X) and the predetermined value (Tstm). When X = Tstm is not satisfied (NO), the count value (X) is incremented by 1 in step [14], and when X = Tstm (YES), the count value (X) is determined in step [15].
Is reset to 0. Thereafter, the flowchart is stopped.

If the mode is the non-standard mode in step [12], it is determined in step [16] whether the count value (X) satisfies X <Wmin with respect to a window lower limit value (Wmin) described later. Is done. And X <Wmin (YE
In the case of S), the count value (X) is incremented by 1 in step [17]. On the other hand, if X <Wmin is not satisfied in step [16] (NO), a system having a vertical frequency of 50/60 Hz is determined in step [18] from the count value (X) at that time, and in step [19]. The window is updated, and the count value (X) is reset to 0 in step [20]. After that, this flowchart stops.
Is done.

Further, when the mode is the non-signal mode in step [12], the mode flag is set to the non-standard mode in step [21], and in step [22], the count value (X) is X> 1.
It is determined whether it is 00 or not. If X> 100 is not satisfied (NO), the count value (X) is incremented by 1 in step [23], and if X> 100 (YES), the count value (X) is reduced to 0 in step [24]. Reset. Thereafter, the flowchart is stopped.
The above software is, for example, twice the horizontal frequency (2
repeated in a cycle of f _H) is activated (start).

In the initial state, the count value (X) is set to an initial value of 0, and the mode flag is set to the non-standard mode. This allows the above flow chart to:
In the initial state, steps [1] → [2] → [6] → [7]
Or driven through [8] and twice the horizontal frequency (2
count in a cycle of f _H) (X) is incremented by 1. Thus, for example, the period of the vertical synchronizing signal is not determined in step [1], and when this count value (X) exceeds the upper limit value (Wmax) of the window, the count value (X) is reset to zero. If this reset is performed, for example, three times in succession, the mode flag is set to the no-signal mode. Thus, the flowchart is changed from step [1] → [2] →

[9]
Driven through [10] or [11], the count value (X) is added one by one at a cycle of twice the horizontal frequency (2f _H ), and the value of 0 → Tstm is repeated.

On the other hand, when the period of the vertical synchronizing signal is determined in the step [1] in the non-standard mode, the flow chart shows the steps [1] → [12] → [16] → [1]
7] or [18] → [19] → [20]. Here, in the initial state, step [16] is X <W
Step [1] while the value is still min (YES)
In step [1] → [2] →

The drive is returned to the drive through [9] → [10] or [11], and while these are repeated, the drive is pulled in step [16] so that X <Wmin is not satisfied (NO).

In this state, in step [18], a system discrimination of 50/60 Hz of the vertical frequency is performed. The determination is performed when this state is repeated, for example, four times. When the average value of the count value (X) during this period is approximately 625, 50H is determined.
When z is approximately 525, it is determined to be 60 Hz. Thus, for example, the value of Tstm is set to 625 at 50 Hz and 525 at 60 Hz, respectively.

In this state, the window is updated in step [19]. This update also has this state, for example, 4
It is performed when the number of repetitions is repeated, and the maximum and minimum values of the count value (X) during this time are added with a predetermined margin to be the upper limit value (Wmax) and the lower limit value (Wmin) of the window. . That is, when the maximum value of the count value (X) during this period is Tmax and the minimum value is Tmin, the margins are α and β, respectively, and Wmax = Tmax + αWmin = Tmin−β. The initial values of the upper limit value (Wmax) and the lower limit value (Wmin) of the window have a sufficiently large width including 625 and 525, and the initial values are set when the mode flag is changed to the non-standard mode. Is reset to Further, when the maximum value Tmax and the minimum value Tmin are both substantially Tstm and the difference is equal to or smaller than a predetermined value, the mode flag is set to the standard mode.

In the standard mode, the steps [1] → [2] → [3] → [4] are usually performed. During the period of the vertical synchronizing signal, the steps [1] → [12] → [13] → [14] or It is driven through [15]. As a result, the count value (X) is added one by one at a cycle of twice the horizontal frequency (2f _H ), and is reset to 0 when X = Tstm, and the value of 0 → Tstm is repeated. On the other hand, if the vertical synchronizing signal cannot be obtained, X =
When it reaches Tstm, the count value (X) is obtained in step [5].
Is reset to 0, and the value of 0 → Tstm is repeated. Therefore, in the standard mode, the count value (X) is always added one by one at a cycle of twice the horizontal frequency (2f _H ), and X = T
It is reset to 0 at the time of stm, and the value of 0 → Tstm is repeated. Further, in this step [5], the count value (X)
Is reset to 0, for example, if the state is repeated eight times in succession, the mode flag is set to the non-standard mode.

Therefore, in this flowchart, in the standard mode, the count value (X) is equal to X in the period of the vertical synchronizing signal.
= Tstm, and is reset to 0 at the time of X = Tstm, even if the vertical synchronizing signal is lost for eight or more times even if the vertical synchronizing signal is lost. As a result, the missing vertical synchronizing signal is interpolated.

That is, in the standard mode, the count value (X) is changed as shown in FIG. 3B with respect to the input vertical synchronizing signal as shown in FIG. Therefore, this count value (X)
When a timing pulse for vertical deflection is formed in a period where is equal to or larger than a predetermined value a and equal to or smaller than a value b, the timing pulse becomes as shown in C of FIG. On the other hand, if the input vertical synchronizing signal is missing as shown in D of the figure, the count value (X) is changed as shown in E of the figure. Here, the count value (X) has the same change regardless of the lack of the input vertical synchronization signal.

Therefore, a timing pulse for vertical deflection is formed during a period in which the count value (X) is equal to or more than a predetermined value a and equal to or less than a value b.
As shown in (1), the missing vertical synchronizing signal is interpolated. Further, since the interpolated vertical synchronization signal has the same change regardless of the lack of the input vertical synchronization signal, the count value (X) is formed at exactly the same timing as the original position, thereby eliminating jitter and the like. The vertical synchronization signal is interpolated.

In the non-standard mode, as shown in FIG. 4A, the width of the window is increased at the initial value, and when a vertical synchronization signal as shown in B of FIG. According to the maximum value Tmax and the minimum value Tmin of the count value (X) at this time, the window is changed to a width obtained by adding predetermined margins α and β to this value as shown in FIG. As a result, the window width is large in the initial value, and the vertical synchronization signal can be determined (pulled in) quickly. After the vertical synchronization signal is pulled in, the window width is reduced, so that the vicinity of the vertical synchronization signal is reduced. Noise and the like can be removed.

Further, when the interval between the vertical synchronizing signals is gradually changing in the non-standard mode, the above-mentioned margin α,
If it is in the range of β, the window is changed accordingly, and the vertical synchronization signal can be discriminated in the non-standard mode satisfactorily. When the phase of the vertical synchronization signal changes significantly, the mode flag is temporarily set to the no-signal mode by, for example, not determining the vertical synchronization signal in the window, and then set to the non-standard mode by determining the vertical synchronization signal. As a result, the width of the window is reset to the initial value, and the determination (pull-in) of the vertical synchronization signal is quickly performed.

In this way, the above-described system determination result of, for example, 50/60 Hz of the vertical frequency and the timing pulse of the vertical deflection are formed. Then, the operation result is taken out to the registers 11 and 12.

Further, the count value (X) being calculated by the vertical synchronization processing circuit 100 is supplied to the register 300 via the bus line 6 for each horizontal synchronization signal, for example.
The count value (X) from 00 is the deflection correction waveform generation circuit 200
Is supplied to the RAM 24 through the bus line 26 of the. As a result, in the deflection correction waveform generation circuit 200, a correction waveform having a desired higher-order equation, for example, a sawtooth wave [Y _SAW =
(CX ³ + DX ² + X) B + A] and parabolic wave [Y _PARA
= (GX ⁴ + X ² + HX) FB ² + E]. However, in these equations, A is a vertical shift, B is a vertical size, C is an S-shaped correction, D is a linearity, E is a horizontal size, F is a pin amplifier, G is a pin phase, and H is a corner pin parameter.

That is, Table 1 below shows, for example, a sawtooth wave [Y
_SAW = (CX ³ + DX ² + X) B + A] is an instruction (I) for performing the operation of the above-described circuit, and is a program list stored in the ROM and the RAM 22.

[0034]

[Table 1]

In this Table 1, the calculation is as follows: Y _SAW =
(((CX + D) X + 1) X + 0) B + A. The calculation is performed with a precision of 16 bits. However, in the above-described circuit, the multiplier 27 has a capacity of 8.times.8 bits.

Therefore, in Table 1, the column a indicates the addresses of the instruction ROM and the RAM 2, and the operation is performed in the order of these addresses. Column b shows the type of instruction, M is a multiplication instruction, L is a load instruction, and J is a jump instruction. Column c shows the type of the load instruction, where K> Y is a memory and a register, and X> Y is a register and a register.
Column d shows the arithmetic expression of the adder 30. The column e shows the register of X, where A is the upper 8 bits of the accumulators 31 and 32 and B is the lower 8 bits. This column e shows a register to be multiplied by the multiplication instruction. The f column indicates the Y register, R is the register 28, 1 is the output register 33, and 2 is the output register 34. g column is ROM23 and RAM2
4 is shown. The g column indicates the address of the coefficient in the multiplication instruction. The h column is for selecting a memory (ROM, RA
M).

As a result, first, in the processing of the address 79, a value is loaded from the address 0D of the RAM 24 to the register 28. The address 0D stores the count value (X) supplied from the register 300 via the bus line 26.

Next, in the processing of the address 7a, a value is loaded from the address 14 of the RAM 24 to the register 28, and 0 is added to the value of the register 28. The addition result is supplied to the accumulator 31. The address 14 stores a linearity coefficient (D).

In the processing of the address 7b, the lower 8 bits of the accumulator 31 are multiplied by the contents of the address 12 of the RAM 24, and the addition of 0 and the value of the register 28 is performed in parallel. Addition result is accumulator 3
2 is supplied. The previous value of the accumulator 31 is retained. The address 12 stores a coefficient (C) for S-shaped correction. In the processing of the address 7b, a product-sum operation of CX (lower order) and 0 + D is performed.

In the processing of the address 7c, the upper 8 bits of the accumulator 31 are multiplied by the contents of the address 12 of the RAM 24, and the value (D) of the accumulator 32 and the processing of the address 7b from the multiplier 27 are obtained. The value of the obtained CX (lower order) + D is shifted by 8 bits to the lower order (selected by the selector 29), and the addition is performed in parallel. By processing the address 7c, CX (upper) and CX
The product-sum operation of (lower) + D is performed.

Then, in the processing of the address 7d, as preparation for the next operation, the address 28 of the ROM 23 and the register 28 are read.
And the value of the accumulator 32 (CX (lower order) + D) and the address 7 from the multiplier 27 are loaded.
The addition with the CX (high-order) value obtained in the processing of c is performed in parallel. In the processing of this address 7d, CX (upper) +
The product-sum operation of CX (lower order) + D is performed, and the value of CX + D is supplied to the accumulator 31.

Thereafter, these processes are sequentially repeated, (CX + D) X + 1 in the process of address 80, ((CX + D) X + 1) X in the process of address 84, and (((CX + D) X + 1) X + 0 in the process of address 89, respectively. ) B + A
= Y _SAW is supplied to the accumulator 31. Then, the value Y _SAW is supplied to the output register 33 in the processing of the address 8a.

Table 2 below shows a parabolic wave [Y _PARA =
(GX ⁴ + X ² + HX) FB ² + E] The instruction for performing the operation of the above-mentioned circuit by the above-mentioned circuit (I) ROM and R
It is a program list stored in AM22.

[0044]

[Table 2]

Accordingly, in Table 2, the processing is sequentially repeated in the same manner as described above, and GX + 0 in the processing of address 61, (GX) X + 1 in the processing of address 65, and ((GX) X + 1) X + H in the processing of address 69, respectively. , (((GX) X + 1) X + H) X + 0 in the processing of address 6d, and (((GX) X + 1) X + H) X in the processing of address 70
F, (((GX) X + 1) X +
H) In the processing of the XFB and the address 77, (((GX) X +
1) The value of (X + H) XFB ² + E = Y _PARA is supplied to the accumulator 31. Then, the value Y _PARA is supplied to the output register 34 in the processing of the address 78.

These processes are performed for each timing signal of twice the horizontal frequency (2f _H ) based on the count value (X) at that time. For the output of these correction waveforms, for example, the value (Y _SAW, Y _PARA ) at that time is taken out to output registers 33 and 34 for each horizontal synchronizing signal, and this output is passed through a D / A converter (not shown). It is supplied to an output amplifier of a horizontal deflection circuit.

According to the above-described apparatus, the count value (X) obtained by the vertical synchronization processing circuit 100 is supplied to the deflection correction waveform generation circuit 200 (register 300) to perform the calculation, thereby achieving a simple configuration. It is possible to form a deflecting device that can obtain a correction waveform (Y _SAW, Y _PARA ) composed of a desired higher-order equation.

That is, in the above-described apparatus, the count value (X) corresponds to the absolute position in the vertical direction on the screen of the monitor receiver. Therefore, the vertical deflection waveform and the horizontal deflection width correction waveform are formed by calculation. In this case, the calculation can be performed using the count value (X) as it is. In the determination of the count value (X)> 100 in step [22] of the above-described flowchart, the vertical synchronization signal is frequently determined due to erroneous detection of noise or the like, and the vertical deflection width is narrowed. It is to prevent from becoming.

In the above-described apparatus, by performing the countdown processing by software, complicated condition determination can be easily performed by a program. Therefore, for example, even if the synchronization signal is lost, it is possible to prevent the displacement of the screen position by interpolating from some past synchronization signals. In addition, by making the window width variable so that it becomes wider when the synchronization signal is pulled in and becomes narrower when the synchronization signal is stabilized, noise near the synchronization signal and the like can be removed and jitter can be prevented. Further, since the system determination is also performed by the same processor as that described above, no additional logic is required for this, and the LSI
In this case, the chip area does not increase.

Further, in the above-mentioned circuit, for example, consider a system in which the vertical frequency is 60 Hz and 50 Hz. In this case, the count value obtained by counting the timing signal of twice the horizontal frequency of the above (2f _H) (X) is the vertical frequency 60Hz
In this case, the waveform changes from 0 to 525, and in the case of 50 Hz, the waveform changes from 0 to 625, and the waveform is as shown in FIG. However, in this case, considering the screen displayed on the cathode ray tube,
The displayed screens of one field are equal to each other. On the other hand, the above-described correction waveforms of, for example, the sawtooth wave and the parabola wave correspond to the absolute positions on the screen.

Considering the count value (X) on the basis of the screen, the results are shown by a solid line and a broken line in FIG. 6 in a system having a vertical frequency of 60 Hz and 50 Hz, respectively. That is, as is clear from this figure, the respective count values (X) are in a proportional relationship at the absolute positions on the screen. Thus the count value used in the calculation as X ^*, X ^* = as previously calculate KX, for example, if the vertical frequency is 60 Hz K =
By setting K = 0.84 in the case of 1,50 Hz, the amount of image distortion with respect to the absolute position on the screen becomes constant irrespective of the system, and there is no need to change parameters and the like for each system. The calculation of X ^* = KX is performed by the multiplier 27.
Can be done with

[0052]

According to the present invention, the count value obtained by the vertical synchronization processing circuit is supplied to the deflection correction waveform generation circuit to perform an arithmetic operation, whereby a correction waveform having a desired higher-order equation can be obtained with a simple configuration. Can be formed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an example of a deflection device according to the present invention.

FIG. 2 is a flowchart illustrating an example of software.

FIG. 3 is a waveform diagram for explanation.

FIG. 4 is a waveform diagram for explanation.

FIG. 5 is a diagram for explanation.

FIG. 6 is a diagram for explanation.

[Explanation of symbols]

 1,21 instruction address generator 2,22 instruction ROM and RAM 3,23 data ROM 4,24 data RAM 5,25 instruction decoder 6,26 bus line 7,29 selector 8,30 adder 9,31 , 32 Accumulator 10 Jump instruction generator 11, 12, 33, 34 Output register 27 Multiplier 28, 300 Register 100 Vertical synchronization processing circuit 200 Deflection correction waveform generation circuit

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁷ Identification symbol FI H04N 5/06 H04N 5/06 Z (56) References JP-A-1-295297 (JP, A) JP-A-63-122365 ( JP, A) JP-A-63-31274 (JP, A) JP-A-63-286070 (JP, A) JP-A-58-17779 (JP, A) JP-A-60-111577 (JP, A) JP-A-2-92176 (JP, A) JP-A-2-202778 (JP, A) JP-A-1-212969 (JP, A) JP-A-62-43268 (JP, A) JP-A-62-234489 (JP) JP-A-1-315788 (JP, A) JP-A-64-12716 (JP, A) JP-A-63-665 (JP, A) JP-A-61-72964 (JP, U) 59-47513 (JP, B2) real public Akira 59-26437 (JP, Y2) PCT National Akira 62-502787 (JP, a) (58 ) investigated the field (Int.Cl. ⁷ DB name) H04N 3/16 G09G 1/04 G09G 1/16 H04N 3/23 H04N 3/27 H04N 5/06

Claims (1)

(57) [Claims] 1. A vertical synchronization included in a supplied video signal.
If the signal is detected, it generates a timing pulse for vertical deflection synchronized with a vertical synchronizing signal and a vertical same
If no sync signal is detected, the missing vertical sync signal
For the vertical deflection synchronized with the interpolated vertical sync signal
In deflection apparatus order to generate a timing pulse, the deflection device, the period of the vertical synchronizing signal of the video signal
The standard mode, which is determined to be the specified one, or the above image
It is determined that the period of the vertical sync signal of the signal is not the specified one.
Is determined to be non-standard mode or no signal.
Operating in one of the no-signal mode
Therefore, when the count value is reset to the initial value in the vertical cycle
In both cases, the operation mode of the deflection device is the non-standard mode.
And then repeat at a frequency cycle that is an integer multiple of the horizontal frequency.
A and software to be started, not least a first step the vertical synchronization signal of the video signal to determine whether it is detected, the vertical synchronization signal of the video signal in the first step the detection was to have you in the case, the operation mode of the deflection device
Is the standard mode or the non-standard mode
Or, alternatively, first to determine whether it is the non-signal mode
In the second procedure and the second procedure, the operation mode of the deflection device is changed to the standard mode.
If the count value is determined to be
A place corresponding to the number of times the software is started in a direct cycle
Compared to the fixed set value, the count value is
It resets the count value in the case is greater than or equal to, I so
In this case, the operation mode of the deflecting device is changed to a non-standard mode in the third procedure of increasing the count value by a constant value and in the second procedure.
If it is determined that the mode is
The upper limit of the window indicating the period for detecting the direct synchronization signal and
In comparison, if the above count value is equal to or greater than the upper limit of the window,
Reset the above count in some cases, otherwise
The fourth procedure for increasing the count value by a constant value, and the operation mode of the deflecting device is set to the non-signal mode in the second procedure.
When it is determined that the over-de, top the count value
The counted value is compared with the predetermined setting value.
If the value is above the set value, reset the above count value,
If not, increase the count value by a constant value.
A vertical synchronizing signal of the video signal is detected in the procedure and the first procedure.
The operating mode of the deflecting device is
Standard mode or non-standard mode above
Or, a sixth procedure for determining whether or not the mode is the no-signal mode.
In the sixth procedure, the operation mode of the deflecting device is changed to the standard mode.
If it is determined that the
If the count value is equal to the predetermined set value,
If not, reset the above count value.
In the seventh procedure for increasing the count value by a constant value, and in the sixth procedure, the operation mode of the deflection device is changed to a non-standard mode.
If it is determined that
Compared to the lower limit of the window, the counted value
If the value is smaller than the lower limit of the window, keep the above count value constant
Increment by value; otherwise, open window above
Eighth procedure for updating and resetting the count value
In the sixth procedure, the operation mode of the deflection device is set to the non-signal mode.
If the deflection device is determined to be
A ninth procedure for setting the operation mode to the non-standard mode, and the count value is equal to or more than the predetermined value in the third procedure.
Is determined a predetermined number of times.
In the tenth procedure for setting the mode to the standard mode, and in the fourth procedure, the count value is set to the upper limit value of the window.
If it is determined that the above is the predetermined number of times, the deflection
A storage unit storing software including an eleventh procedure for setting the operation mode of the apparatus to the no-signal mode; and executing the software stored in the memory to generate the timing pulse for vertical deflection. A vertical synchronization processing circuit including an arithmetic unit, a memory storing data and coefficients, and a multiplier for multiplying the data and coefficients stored in the memory at each timing of a cycle of an integral multiple of the horizontal frequency. An adder for adding a multiplication result from the multiplier or a coefficient stored in the memory and a previously calculated operation result or a reset value, and control means for controlling operations of the multiplier, the adder and the memory. And a count value obtained by counting the horizontal synchronizing signal is supplied. From this count value, a deflection correction wave for repeatedly performing calculations using the multiplier and the adder is provided. And a generating circuit, a count value obtained in the vertical synchronization processing circuit by supplying to the deflection correcting waveform generating circuit, a deflection device to obtain a correction waveform consisting of desired high order formulas.