JP3171240B2 - Resistance element, semiconductor device using the same, and method of manufacturing these - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a resistance element,
In particular, the present invention relates to a resistance element such as a high resistance load used together with a MOSFET or a thin film transistor in a static random access memory (hereinafter, referred to as an SRAM) using a flip-flop circuit, and a semiconductor device using the same.

[0002]

2. Description of the Related Art FIG. 1 shows a circuit diagram of an SRAM cell. The circuit of this SRAM cell includes transfer transistors Ta1, Ta2 and a driver transistor Td1,
Td2, load elements R1, R2 and bit lines BL1, B
A flip-flop circuit comprising L2, word lines WL1, WL1 ', power supply line Vcc and ground line Vss is formed.

In general, a plurality of SRAMs shown in FIG. 1 are arranged in a matrix, a cell in a row direction is selected by a word line WL, a cell in a column direction is selected by a bit line BL, and a cell located at an intersection thereof is selected. The stored information is read and written. Here, the same signals are supplied to the word lines WL1 and WL1 'by being connected to the same word line driver (not shown).

Next, the word line WL1 goes high,
The operation when the cell shown in FIG. 1 is selected and the information stored in this cell is read will be described. Now, it is assumed that the intersection D1 is at the H level and the intersection D2 is at the L level. When the intersection D1 is at the H level, the driver transistor Td2
Becomes ON, a current flows through the resistor R2, and the intersection D2 becomes L level. This is input to the gate of the driver transistor Td1, and the transistor Td1 is turned off, so that no current flows through the resistor R1 and the intersection D1 becomes H level. Thus, the flip-flop circuit is in the first stable state.

When the word line WL1 is at the H level, the transfer transistors Ta1 and Ta2 are turned on, and the levels of the intersections D1 and D2 are changed to the bit lines BL1 and BL2.
2 and output to the outside through a sense amplifier and a driver amplifier (not shown).

[0006] In recent years, the storage capacity has become larger and larger, and the bit lines BL tend to be longer. As the bit line BL becomes longer, not only does the signal propagation time increase, but also the wiring resistance and the parasitic capacitance increase, so that the time required for reading and writing further increases.

Although the load elements R1 and R2 shown in FIG. 1 are conventionally provided in a part of a straight line portion of the Vcc wiring, the purpose is to shorten the bit lines BL1 and BL2 to reduce the wiring resistance and to adjust the load resistance. For the purpose of expanding the range of possible load resistance values, it is required that the Vcc wiring be bent and a load element be provided at the bent portion.

FIG. 16 shows a Vcc wiring portion including a load element. As described above, the wiring from Vcc to the shared contacts SC1 and SC2 (connected to D2 and D1, respectively) is bent, and the load elements R1 and R2 are formed at the bent portions.

The load elements R1, R2 having such a pattern
Can be formed, for example, by applying a method described in JP-A-9-219494.

For example, after forming a Vcc wiring pattern shown in FIG. 17 with a semi-insulating polysilicon layer 11 having a high resistance,
As shown in FIG. 18, the portions that become the load elements R1 and R2 are masked with the photoresist 12 (12a and 12b), and ions are implanted into the unmasked portions to reduce the resistance. In this case, the masked portion remains as a high resistance, and thus functions as a load element, and the low resistance portion functions as a normal wiring.

However, if it is attempted to form a pattern in which the boundary between the low resistance portion and the high resistance portion as shown in FIG. However, there was a problem that an accurate resistance value could not be obtained due to a change in the length of the wire. In FIG. 18, 12a indicates a photoresist pattern at a regular position, and 12b indicates a photoresist pattern when misalignment occurs. As is clear from the comparison of the length of the semi-insulating polysilicon layer 11 covered by the photoresist patterns 12a and 12b, the photoresist pattern for forming the load element R2 is located on the lower right side, the right side, and the lower side. If it shifts, the resistance value of the load element R2 decreases, and if it shifts to the upper left, the left, and the upper side, the resistance increases.

Further, the resistance not only fluctuates, but also
When R1 and R2 are paired as in the flip-flop circuit, when misalignment occurs such that one of the resistances increases, the other resistance decreases. There was a problem that the balance became extremely poor. For this reason, the symmetry of the flip-flop circuit constituting the memory cell is deteriorated, and it is difficult to rewrite from the first stable state to the second stable state, or from the second stable state to the first stable state due to disturbance. There was a problem such as changing to.

In the flip-flop circuit, a current always flows through one of the load elements R1 and R2. This current value is determined by the resistance values of the load elements R1 and R2, and the smaller the resistance value, the larger the current flowing through the flip-flop circuit. Even if the variation in the amount of current per SRAM is small, if the storage capacity is large, S
The variation in current consumption of the entire RAM becomes large. Even if the resistance value varies, the resistance value must be set in advance in order to satisfy the product specification of the current consumption. However, if the load elements R1 and R2 are too large, there is a problem that the standby characteristics and the soft error rate with respect to α rays are deteriorated, the margin in the manufacturing process is reduced, and the yield and productivity are reduced.

As described above, it has become an important issue how to reduce the variation in the resistance value while reducing the length of the bit line.

[0015]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and a resistor capable of obtaining a stable resistance value even when some mask misalignment occurs in a manufacturing process. An object is to provide an element, a semiconductor device using the element, and a method for manufacturing the element.

[0016]

The present invention has a bent portion having a bent angle θ, and is formed by a wiring layer comprising a high resistance portion and a low resistance portion provided in a region including the bent portion. A boundary between the low resistance portion and the high resistance portion is a straight line substantially parallel to a bisector of the bending angle θ.

Further, the present invention provides a method of manufacturing a resistance element having a bent portion having a bent angle θ and a wiring layer including a high resistance portion provided in a region including the bent portion and a low resistance portion. In the method, a step of forming a low-resistance material film over the entire surface of the substrate and an opening in a region including a bent portion of a wiring layer to be formed later, and a line that traverses the wiring layer pattern has a bending angle θ Forming a mask that becomes a straight line substantially parallel to the bisector, etching the low-resistance material film exposed from the mask opening, and subsequently forming a high-resistance material film on the entire surface; Patterning the low-resistance material film and the high-resistance material film to form a wiring structure.

Further, the present invention provides a method of manufacturing a resistance element having a bent portion having a bent angle θ, and a wiring layer including a high resistance portion provided in a region including the bent portion and a low resistance portion. In the method, a step of forming a low-resistance material film on the entire surface of a substrate, a step of forming a shape of the low-resistance material film to form a wiring layer, and an opening in a region including a bent portion of the wiring layer are provided. Forming a mask in which a line crossing the wiring layer pattern is a straight line substantially parallel to the bisector of the bending angle θ;
Etching a wiring layer formed of the low-resistance material film exposed from the mask opening; and
Forming a wiring layer using a high-resistance material film so as to cover at least the removed wiring layer.

Further, the present invention has a bent portion having a bent angle θ, and a high resistance portion provided in a region including the bent portion;
In a method for manufacturing a resistance element formed of a wiring layer including a low-resistance portion, a step of forming a high-resistance material film over the entire surface of a substrate and covering a region including a bent portion of a wiring layer to be formed later, A step of forming a mask in which a line traversing the layer pattern is a straight line substantially parallel to a bisector of the bending angle θ, and a step of using the mask to reduce the resistance of the high-resistance material film And a method for manufacturing a resistance element.

Further, the present invention has a bent portion having a bent angle θ, and a high-resistance portion provided in a region including the bent portion;
In a method of manufacturing a resistance element formed of a wiring layer including a low-resistance portion, a step of forming a high-resistance material film over the entire surface of a substrate and forming a wiring layer by processing the shape of the high-resistance material film Covering the step and the area including the bent portion of the wiring layer,
Forming a mask in which the line traversing the wiring layer pattern is a straight line substantially parallel to the bisector of the bending angle θ, and lowering the high-resistance material film in a portion not covered by the mask using the mask; And a method of manufacturing a resistance element.

[0021]

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, as shown in FIG.
The high resistance portion 21 is provided on the wiring 20 in a region including the bent portion. In the present invention, the bent portion is not limited to the case where it is bent only once as shown in FIG.
As shown in FIGS. 2 (b) and 2 (c), it may be bent more than once. That is, in the region 21 where the high resistance portion 21 is formed,
2 (a) to 2 (c) as long as the bent portion is included in FIG.
This includes the case where the low-resistance portions 22a and 22b sandwiching the high-resistance portion 21 are bent to form a bending angle θ as shown in FIG. Further, the low resistance parts 22a and 22b
The wiring may be bent for convenience of wiring, but the bending angle θ in the present invention is different from the area 21 where the high-resistance portion is formed.
It refers to the angle formed by the low-resistance portion closest to a.

FIG. 4 is a diagram showing the positional relationship between the high resistance portion 21, the low resistance portions 22a and 22b, and the boundary 23 of the wiring shown in FIG. In the present invention, the boundary 23 is disposed so as to be substantially parallel to the bisector 25 of the bending angle θ formed by the low resistance portions 22a and 22b disposed on both sides of the high resistance portion 21.

The present invention is most effective when θ is 90 ° as shown in FIG.
Is an obtuse angle, and similarly, the bisector 2 of the bending angle θ formed by the low-resistance portions 22a and 22b can be similarly applied.
5, the boundary 23 is arranged so as to be substantially parallel. The same applies to the case where θ is an acute angle.

The boundary 23 and the bisector 25 are formed to be as parallel as possible. For example, if it is within ± 10 °, it is acceptable for ordinary purposes, but preferably it is within ± 5 °.

In the present invention, the substrate on which the resistive element is formed is appropriately selected depending on the application in which the resistive element is used. In the semiconductor substrate, FETs, transistors, other semiconductor elements, interlayer insulating films and the like may be formed. Also, the present invention
The present invention can also be applied to a resistor element formed by printing on a ceramic substrate or a printed wiring board.

According to the configuration of the present invention, even when misalignment of the mask pattern occurs, the fluctuation of the resistance value can be suppressed to the minimum. FIGS. 2 to 5 show a single resistive element. However, when two resistive elements form a pair, or when a plurality of resistive elements are used side by side, the variation in resistance between the resistive elements is minimized. Can be

The semiconductor device using the resistance element of the present invention is, for example, an SRAM, a differential amplifier, a D / A conversion element using an arrangement of resistors, etc., which are configured by flip-flop circuits using two resistance elements in pairs. Can be used widely.

[0029]

[Embodiment 1] An SRAM constituted by a flip-flop circuit using a resistance element according to the present invention as a load is shown in FIG.
This will be described with reference to a diagram in which a cross section along line 2 is developed.

First, as shown in FIG. 7A, a field oxide film 2 serving as an element isolation region is formed on a semiconductor substrate 1 by 20.
It is formed with a thickness of 0 to 500 nm.

Next, as shown in FIG. 7B, a silicon oxide film serving as the gate oxide film 3 is formed to a thickness of 3 to 10 nm, and then the gate electrode 4-1 of the transistor Td1 and the wiring 4 are formed.
For example, a film in which a polysilicon film and a high-melting-point silicide film are stacked is deposited to a thickness of 50 to 300 nm. continue,
A gate electrode 4-1 and a wiring 4-2 are formed using a film in which a polysilicon film and a high-melting-point silicide film are stacked by using a lithography technique and an etching technique. After that, impurity ions are implanted, and a diffusion layer D1, which becomes a source or drain region,
D2 and S1 are formed. D1, D2 and S1 are shown in FIG.
Correspond to the points shown in FIG.

Next, as shown in FIG. 7C, an interlayer insulating film 5 is formed, and a shared contact 6 is opened using lithography and etching. This corresponds to SC1 in FIG.

Next, as shown in FIG. 8D, in order to form a wiring serving as a power supply line, a P film is formed on the entire surface as a low-resistance material film.
Alternatively, the polysilicon film 7 doped with As is
Deposit 00 nm. The method of doping P or As is C
Either a method of doping simultaneously with the growth of the polysilicon film by the VD method or a method of doping by ion implantation after depositing a non-doped polysilicon film may be used. The impurity concentration of P or As in the polysilicon film 7 is 1 × 10 ¹⁹ to 1 × 10 ²² atm.
/ Cm ³ . Subsequently, a photoresist 8 having a mask opening 27 is formed as a mask for processing the polysilicon film 7.

FIG. 12 is a plan view of the photoresist 8, and more specifically, as shown in FIG. The mask is formed such that the line 26 at which the end of the opening 27 intersects is as parallel as possible to the bisector 25 of the wiring bending angle θ. Here, the shape of the mask opening is shown in FIG.
It is not necessary to have the rectangular shape shown by 13, but any polygon may be used as long as the line 26 satisfies a desired angle with respect to the bisector 25.

Next, the polysilicon film 7 exposed from the opening 27 is etched, and thereafter, the photoresist 8 is removed to obtain the structure shown in FIG.

Next, as shown in FIG. 9F, a polysilicon film or a SIPOS film 9 is formed on the entire surface as a high resistance material film.
Is deposited to a thickness of 20 to 150 nm. This SIPOS film (semi-insulating polysilicon film, Semi-Insulating Polycrystallin
e Silicon) can be formed by a CVD method using a mixed gas of SiH ₄ and N ₂ O. After that, using the photoresist 10, the polysilicon films 7, 7a, 7b,
The polysilicon film or SIPOS film 9 is processed into a final wiring shape. The plan view of the photoresist 10 at this time is as shown in FIG. 14. When the wiring has a bending angle of 90 ° and the wiring and the end of the opening intersect at 45 ° as shown in FIG. Even if the position of the photoresist 8 with respect to is at the regular relative position 8a,
It can be seen that even at the relative position 8b when the misalignment occurs, the lengths of the wirings separated by the mask openings are the same. That is, it can be seen that there is no change in the resistance value of the obtained resistance element.

Even when the bending angle is not 90 °, the mask is formed so as to be as parallel as possible to the bisector 25 of the wiring bending angle θ to minimize the fluctuation of the resistance element. Can be minimized. Even if they are not completely parallel, for example, if they are within ± 10 ° from parallel, they can be accepted for normal purposes, but preferably within ± 5 °.

Next, as shown in FIG. 9G, the photoresist 10 is removed to complete the SRAM of this embodiment.

In this embodiment, the low resistance portion is formed by laminating the polysilicon films 7a and 7b and the polysilicon film or the SIPOS film 9, and the high resistance portion is formed by the polysilicon film or S
The IPOS film 9 has a single layer.

In this example, when the wiring width was 0.25 μm and the length of the high resistance portion was 0.8 μm, a resistance element of about 10 ¹¹ Ω was obtained with high accuracy and without variation. In addition, since the load element portion is bent, the wiring resistance of the bit line of the SRAM does not become a problem, and the variation of the resistance value can be suppressed. Can meet the standards. Furthermore, the standby characteristic and the soft error rate due to alpha rays were small.

In this embodiment, the wiring shape is formed after the high-resistance portion and the low-resistance portion are formed first. However, the wiring shape is formed first with a low-resistance material film, and then the photoresist is formed using a photoresist. The wiring of the bent portion may be removed, and a high-resistance material film may be formed again on the removed portion to form a wiring including a high-resistance portion and a low-resistance portion.

[Embodiment 2] In this embodiment, the case where the resistance element of the present invention is used for an SRAM as in Embodiment 1 will be described. 10 and 11 are views for explaining the manufacturing process. In FIG. 6, X1-X corresponding to the bending of the wiring is shown.
FIG. 4 is an expanded view of a cross section along 2.

First, as shown in FIGS. 7A to 7C, the interlayer insulating film 5 is formed in the same manner as in the first embodiment.
As shown in (a), a polysilicon film or a SIPOS film 11 is deposited on the entire surface as a high resistance material film to a thickness of 30 to 150 nm. Subsequently, a photoresist 12 is formed as a mask for ion implantation, and then ion implantation of P or As is performed at a dose of 1 × 10 ¹⁴ to 1 × 10 ¹⁶ atm / cm ² .

Next, as shown in FIG. 10B, the photoresist 12 is removed. Polysilicon film or SIPOS film 11 where P or As is ion-implanted
b is a low-resistance portion, which is a portion of the polysilicon film or SIPOS film 1 where P or As is not ion-implanted.
1a is a high resistance portion.

Next, as shown in FIG. 11C, a photoresist 13 serving as a mask for processing the polysilicon film or the SIPOS films 11a and 11b into a wiring shape is formed.

Next, as shown in FIG. 11D, after etching the polysilicon film or the SIPOS films 11a and 11b, the photoresist 13 is removed to complete the SRAM.

The thus formed SIPOS film 11a without ion implantation and the SIPOS film 1 with ion implantation are formed.
FIG. 15 shows a relative positional relationship between the wiring pattern 1 b and the photoresist 12. As described above, also in the present embodiment, the photoresist 12 (12a,
The line where the end of 2b) intersects with the wiring pattern is formed so as to be as parallel as possible to the bisector of the bending angle θ of the wiring. Therefore, the position 12b when misalignment occurs from the regular relative position 12a of the photoresist 12.
Since the length of the wiring covered by the photoresist is the same even when the resistance is shifted, there is no variation in the resistance value of the resistance element, and no variation occurs between the paired resistance elements.

In this case, as in the first embodiment, even when the bending angle is not 90 °, a mask is formed so as to be as parallel as possible to the bisector 25 of the wiring bending angle θ. By doing so, it is possible to minimize the fluctuation of the resistance element. Even if they are not completely parallel, for example, if they are within ± 10 ° from parallel, they can be accepted for normal purposes, but preferably within ± 5 °.

The SRAM provided with the resistance element thus obtained exhibited excellent characteristics as in the first embodiment.

In this embodiment, a polysilicon film or S
After ion implantation into the IPOS film 11, the wiring shape was formed by etching, but after forming the wiring shape first,
The resistance of the high-resistance material film at the location where the low-resistance portion is formed may be reduced by ion implantation.

In the first and second embodiments, the resistance element used as the load element of the SRAM has been described as an example.
The wiring width, the length of the high resistance portion, and the like are not limited to the AM, and can be appropriately determined according to the target resistance value.

Further, it is preferable that the material that can be used is appropriately selected according to the application in which the resistance element is used. In the first embodiment, doped polysilicon is used as the wiring for forming the low resistance portion. However, in other applications, other conductive materials such as a metal such as Al can be used. Further, the ion implantation amount in the second embodiment can be appropriately adjusted according to the purpose.

Embodiment 3 (Reference Example) This embodiment is a further different embodiment of the present invention.
As shown in FIGS. 9A and 9B, the wiring 20 is bent so that the low-resistance portions 22a and 22b sandwiching the high-resistance portion 21 are parallel to each other. In this case, the boundary 23 between the high resistance portion 21 and the low resistance portions 22a and 22b may be formed to be perpendicular to the wiring 20 as shown in FIG.

The manufacture of this wiring structure is described in the first or second embodiment.
It can be performed according to. In that case, the mask boundary 28
The line which crosses the pattern of the wiring 20 may be either a right angle as shown in FIG.

According to this embodiment, a resistive element having an accurate resistance value can be formed in a narrow region as in the first and second embodiments.

[Embodiment 4] The structure of the SRAM to which the manufacturing method of Embodiment 1 or 2 is applied is not particularly limited, but one example thereof will be described in more detail with reference to FIGS. explain.

FIG. 20 is a plan view showing one memory cell of this SRAM structure, which includes a straight line A1-A1 '(this line passes through the center of the bit contact BC2) and a straight line A2.
-A2 '(this line passes through the center of the bit contact BC1), and the straight line B1-B1' (this line passes through the center of the ground contact GC1) and the straight line B2-B.
A rectangle surrounded by 2 '(this line passes through the center of the bit contact GC2) is a memory cell unit.
In the horizontal direction, a large number of the memory cell units are repeated to arrange the cells, and in the vertical and vertical directions, the cells are repeated so that adjacent cells have an inverted symmetric shape.

In FIG. 20, power supply line Vcc and load elements R1 and R2 connected thereto are indicated by oblique lines, and ground line Vcc is shown.
ss is indicated by a thick solid line, and the storage node diffusion layers D1, D2,
The active regions such as the sources S1 and S2 and the field oxide film regions are indicated by dotted lines. A wavy line indicates that the cell is connected to an adjacent cell.

In this SRAM structure, the word lines WL1,
WL1 ′ is 2 in the direction perpendicular to the bit lines BL1 and BL2.
In this arrangement, the storage node diffusion layers D1 and D2 are connected to the bit line BL.
1 and BL2, the word lines WL1 and WL
Bit line BL from the middle so as to vertically intersect
1 and BL2. The driver transistors Td1 and Td2 are connected to two word lines WL1 and WL2.
1 ′ and are arranged obliquely with the bit lines BL1 and BL2. That is, in the memory cell of this structure, the channel direction of the transfer transistors Ta1 and Ta2 and the channel direction of the driver transistors Td1 and Td2 are arranged obliquely, the bit line and the channel direction of the driver transistor are oblique and the channel direction of the transfer transistor is oblique. The directions are arranged in parallel. Further, the driver transistors Td1, Td2 and the transfer transistor Ta
1. The gate of Ta2 is arranged between the source and the drain.

Next, a description will be given from the lower layer side with reference to FIGS.

FIG. 21 shows an active region, a gate electrode, ground contacts GC1 and GC2 shared contacts SC.
1, patterns of SC1, and bit contacts BC1, BC2 are shown. The active areas are the word lines WL1, WL
1 'are arranged obliquely, for example, at an angle of 45 degrees, and the portions intersecting the word lines WL1 and WL1' are arranged vertically.
The gate electrodes of the driver transistors Td1 and Td2 are
The word lines WL1 and WL1 'are arranged obliquely, for example, at an angle of 45 degrees so as to be orthogonal to the active region. The gate electrodes of the transfer transistors Ta1 and Ta2 are the word lines WL1 and WL1 '. Ground contact GC
1, GC2 is disposed on the opposite side of the storage node diffusion layers D1, D2 with the driver transistors Td1, Td2 interposed therebetween.
The ground contact is used in common with the adjacent cells. Shared contacts SC1 and SC2 are arranged such that the gate electrodes of driver transistors Td1 and Td2 extend to opposing storage node diffusion layers D2 and D1, respectively, and are connected to both the gate electrodes and storage node diffusion layers D1 and D2. . Bit contacts BC1 and BC2 are
Storage node diffusion layer D sandwiching word lines WL1 and WL1 '
1, placed on the side opposite to D2.

FIG. 22 shows a pattern of the ground line Vss. Note that the ground line Vss in FIG. 22 is a pattern in the case where the ground line Vss is used as a second layer wiring on a gate which is a first layer wiring. Therefore, the ground line Vss is arranged at a certain distance from the shared contacts SC1 and SC2 and the bit contacts BC1 and BC2 to be formed in a later step.

FIG. 23 shows power supply line Vcc and load element R
1 and R2 are shown. The power supply line Vcc is arranged in the same direction as the word line while maintaining a certain distance from the bit contacts BC1 and BC2. In the present invention, the load element R
1, R2 is connected to power supply line Vcc and shared contact SC.
1. The bent portion of the wiring connecting to SC2 is made to have high resistance. The manufacturing method can be performed according to the method described in Example 1 or Example 2.

Further, in this embodiment, the description has been given of the high resistance type SRAM, but the same can be applied to a TFT type SRAM.

FIG. 24 shows patterns of bit lines BL1 and BL2. The bit lines BL1 and BL2 are connected to the word line W
Two are arranged in the vertical direction with respect to L1 and WL1 '.

In the SRAM structure of this embodiment, driver transistors Td1 and Td2 are connected to word lines WL1 and WL
1 ′, the driver transistor Td
1, the channel direction of Td2 is arranged obliquely to the channel direction of the transfer transistors Ta1, Ta2,
The gates of the driver transistors Td1 and Td2 and the transfer transistors Ta1 and Ta2 have sources,
It is arranged perpendicular to the drain.

Therefore, a cell layout with a small aspect ratio is realized, and the length of the bit line can be shortened, so that the bit line capacity is reduced. Since no imbalance occurs, the stability of the memory cell is excellent in operation, and since the resistance values of the load resistors R1 and R2 are accurate and have no imbalance, the minimum operating voltage of the SRAM cell can be reduced.

[0068]

According to the present invention, in the manufacturing process, the resistance value hardly changes even if some mask misalignment occurs, and the variation between the resistance elements is small even when a large number of resistance elements are manufactured at the same time. An element is obtained.

An SRAM using this resistance element is:
Since the load element portion is bent, the wiring resistance of the bit line of the SRAM does not cause any problem, and the standby characteristic and the soft error rate due to alpha rays are small.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit of an SRAM.

FIG. 2 is a view showing a bent portion of the resistance element of the present invention.

FIG. 3 is a view showing a bent portion of the resistance element of the present invention.

FIG. 4 is a diagram for explaining a bending angle θ, a high-resistance portion, a low-resistance portion, and a positional relationship between boundaries thereof in the resistance element of the present invention.

FIG. 5 is a diagram illustrating a positional relationship between a bending angle θ, a high-resistance portion, a low-resistance portion, and a boundary thereof in the resistance element of the present invention.

FIG. 6 is a diagram showing wirings on which the load elements of the SRAM described in the first and second embodiments are formed.

FIG. 7 is a process sectional view illustrating the manufacturing process of the first embodiment.

FIG. 8 is a process sectional view illustrating the manufacturing process of the first embodiment, following FIG. 7;

FIG. 9 is a process cross-sectional view for explaining the manufacturing process of the first embodiment, following FIGS. 7 and 8;

FIG. 10 is a process cross-sectional view for explaining a manufacturing process in Example 2.

FIG. 11 is a process sectional view illustrating the manufacturing process of the second embodiment, following FIG. 10;

FIG. 12 is a view showing a photoresist mask used in Example 1.

FIG. 13 is a diagram showing a positional relationship between a photoresist mask and wiring used in Example 1.

FIG. 14 is a diagram showing a positional relationship between a photoresist mask and wiring used in Example 1.

FIG. 15 is a diagram illustrating a positional relationship between a photoresist mask and wiring used in Example 2.

FIG. 16 is a diagram illustrating a positional relationship between a load resistance (high resistance portion) and a low resistance portion in a conventional SRAM.

FIG. 17 is a diagram showing a wiring pattern formed of high-resistance semi-insulating polysilicon in an SRAM.

FIG. 18 is a diagram showing a positional relationship between a wiring pattern formed of high-resistance semi-insulating polysilicon and a mask for ion implantation in a conventional SRAM.

19 is a diagram showing the shape condition of the resistive element of the reference example.

FIG. 20 is a diagram showing one example of an SRAM structure to which the resistance element of the present invention is applied.

FIG. 21 is a partial view of a layout of an SRAM structure to which the resistance element of the present invention is applied.

FIG. 22 is a partial view of a layout of an SRAM structure to which the resistance element of the present invention is applied.

FIG. 23 is a partial view of a layout of an SRAM structure to which the resistance element of the present invention is applied.

FIG. 24 is a partial view of a layout of an SRAM structure to which the resistance element of the present invention is applied.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 field oxide film 3 gate oxide film 4 gate electrode 5 interlayer insulating film 6 shared contact 7, 7a, 7b polysilicon film 8 photoresist 8a regular position of photoresist 8b position of misaligned photoresist 9 Polysilicon film or SIPOS film 10 Photoresist 11 Polysilicon film or SIPOS film 12 Photoresist 12a Regular position of photoresist 12b Position in case of misalignment of photoresist 20 Wiring 21 High resistance part 22, 22a, 22b Low resistance part 23 Boundary between high resistance part and low resistance part 25 Bisection line of bending angle θ 26 Line where the end of photoresist opening intersects with wiring 27 Photoresist opening 28 Mask boundary

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁷ Identification symbol FI H01L 21/822 (56) References JP-A-57-172761 (JP, A) JP-A 1-260849 (JP, A) Features JP-A-58-30151 (JP, A) JP-A-54-140488 (JP, A) JP-A-62-199046 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27 / 04 H01C 7/00 H01C 13/00 H01C 17/06 H01L 21/265 H01L 21/822

Claims (12)

(57) [Claims] 1. A resistance element having a bent portion having a bent angle θ, and formed of a wiring layer including a high-resistance portion and a low-resistance portion provided in a region including the bent portion, wherein: The boundary between the bent portion and the high resistance portion is defined by the bending angle θ of 2
A resistance element characterized by being a straight line substantially parallel to an equal line. 2. The resistance element according to claim 1, wherein said high resistance portion is formed of polysilicon or semi-insulating polysilicon, and said low resistance portion is formed of doped polysilicon. 3. A method of manufacturing a resistance element having a bent portion having a bent angle θ, a wiring layer including a high resistance portion provided in a region including the bent portion and a low resistance portion, A step of forming a low-resistance material film over the entire surface of the substrate; and an opening in a region including a bent portion of a wiring layer to be formed later.
Forming a mask that becomes a straight line that is substantially parallel to the bisector, and etching the low-resistance material film exposed from the mask opening; and subsequently forming a high-resistance material film over the entire surface. Forming a wiring structure by patterning the low-resistance material film and the high-resistance material film. 4. A method for manufacturing a resistance element formed by a wiring layer having a bent portion having a bent angle θ and a high-resistance portion provided in a region including the bent portion and a low-resistance portion, A step of forming a low-resistance material film over the entire surface of the substrate; a step of shaping the low-resistance material film to form a wiring layer; and forming a wiring in a region including a bent portion of the wiring layer. Forming a mask in which a line crossing the layer pattern is a straight line substantially parallel to the bisector of the bending angle θ, and etching the wiring layer formed of the low-resistance material film exposed from the mask opening And a step of forming a wiring layer using a high-resistance material film so as to cover at least the wiring layer removed by this step. 5. The resistance element according to claim 3, wherein said high resistance material is polysilicon or semi-insulating polysilicon, and said low resistance material is doped polysilicon. 6. A method for manufacturing a resistance element having a bending portion having a bending angle θ, and a wiring layer including a high resistance portion provided in a region including the bending portion and a low resistance portion. A step of forming a high-resistance material film on the entire surface of the substrate; and a line that covers a region including a bent portion of a wiring layer formed later and crosses the wiring layer pattern is substantially equal to a bisector of the bending angle θ. A method for manufacturing a resistance element, comprising: a step of forming a mask that becomes a parallel straight line; and a step of lowering the resistance of a high-resistance material film using the mask. 7. A method of manufacturing a resistance element having a bending portion having a bending angle θ, and a wiring layer including a high resistance portion provided in a region including the bending portion and a low resistance portion. A step of forming a high-resistance material film over the entire surface of the substrate; a step of forming a shape of the high-resistance material film to form a wiring layer; and covering a region including a bent portion of the wiring layer, forming a wiring layer pattern. A step of forming a mask whose crossing line is a straight line substantially parallel to the bisector of the bending angle θ; And a method for manufacturing a resistance element. 8. The method according to claim 6, wherein the high-resistance material is polysilicon or semi-insulating polysilicon, and the step of reducing the resistance is performed by ion implantation. . 9. A semiconductor device comprising the resistance element according to claim 1. 10. A method for manufacturing a semiconductor device, comprising the method for manufacturing a resistance element according to claim 3 as one step. 11. An S circuit comprising a flip-flop circuit using the resistance element according to claim 1 as a load element.
RAM. 12. A method of manufacturing an SRAM having a flip-flop circuit including the method of manufacturing a resistance element according to claim 3 as one step.