JP3166750B2 - Semiconductor device manufacturing method and semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a cylindrical stacked capacitor and a semiconductor device, and more particularly to a method for preventing the generation of particles due to peeling of a formed film and the yield accompanying the generation of particles. The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device capable of preventing the deterioration.

[0002]

2. Description of the Related Art In recent years, as DRAM cells have shrunk, it has become necessary to obtain a required capacitor capacity with a limited occupied area, and semiconductor memory devices having cylinder-type stacked electrodes have been actively developed. As such a conventional technique, for example, there is a technique described in JP-A-10-289981. That is, in the conventional technique, in a method of manufacturing a semiconductor memory device having a storage node electrode having a cylindrical capacitor (cylinder type stacked capacitor), a step of forming a SiN film on an interlayer insulating film, and a step of forming a conductor on the SiN film A step of depositing a film, a step of depositing an insulating film whose film quality in the thickness direction changes substantially periodically on the conductive film, and patterning the insulating film and the conductive film by anisotropic etching to form a columnar shape. Forming the portion, etching the insulating film of the columnar portion by isotropic etching to make the side wall of the insulating film of the columnar portion uneven, and depositing a conductive film as one electrode of the cylindrical capacitor. Forming a cylindrical conductive film on the side wall of the columnar portion by etching back the conductive film serving as one electrode of the cylindrical capacitor by anisotropic etching. And a step of product, and depositing a conductor film to the other electrode of the tubular capacitor. According to such a conventional technique, the insulating film sidewall of a columnar portion formed by anisotropically etching the insulating film and the conductor film whose film quality in the film thickness direction changes substantially periodically isotropically etched. One electrode of a cylindrical capacitor formed along the uneven surface of the insulating film side wall and a tube formed along the surface of the electrode by using an etching rate difference due to a difference in film quality in etching by the In a cylindrical capacitor composed of an insulating film of a cylindrical capacitor and the other electrode of the cylindrical capacitor formed along the insulating film, the electrode area of the cylindrical capacitor increases and the capacitance of the capacitor increases. Therefore, it is disclosed that a desired capacitance of the capacitor can be reliably obtained without increasing the height of the cylindrical capacitor so that a highly integrated semiconductor memory device can be manufactured.

[0003]

However, the prior art has a problem that the yield is remarkably reduced due to particles generated from the outer peripheral portion of the wafer, and it is difficult to put it to practical use. The present invention has been made in view of such a problem, and its purpose is to prevent the generation of particles due to peeling of the formed film and the like,
An object of the present invention is to provide a method of manufacturing a semiconductor device and a semiconductor device that can prevent a decrease in yield due to generation of particles.

[0004]

According to the first aspect of the present invention, there is provided a cylinder type stacked capacitor which prevents generation of particles due to peeling of a formed film and the yield accompanying the generation of particles. A method of manufacturing a semiconductor device capable of preventing a reduction, comprising: a step of forming a capacitance contact step which is a step formed at an edge of a wafer when forming a capacitance contact; Stacking step, which is a step formed at the edge of the wafer when forming a trench,
Setting the position closer to the wafer periphery than the position of the capacitive contact step. The gist of claim 2 of the present invention is:
Forming a trench on the capacitor contact plug in the form of the lower electrode of the cylinder type with the stack stage being set closer to the wafer periphery than the capacitor contact stage when forming the trench. A method for manufacturing a semiconductor device according to claim 1. According to another aspect of the present invention, there is provided a semiconductor having a cylindrical stacked capacitor, capable of preventing generation of particles due to peeling of a formed film and the like, and capable of preventing a reduction in yield due to generation of particles. A method of manufacturing a device, comprising: forming a capacitor contact step which is a step formed at an edge of a wafer when forming a capacitor contact; and forming a trench serving as a mold of a cylinder-type lower electrode. A step of setting a stack step, which is a step formed at the edge of the wafer, on the wafer peripheral side from the position of the capacitive contact step, and masking the center of the wafer with the resist with respect to the capacitive contact step, Removing the doped silicon film formed on the wafer edge and / or the back surface. It resides in the method of production. The gist of claim 4 of the present invention is a step of etching back the entire surface of the wafer except for the inside of the trench to be a cylinder to remove an oxide film, and etching back the entire surface of the wafer except for the inside of the trench to be a cylinder. And the wafer edge portion and / or
4. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of etching back the doped silicon film formed on the back surface and removing the doped silicon film. According to a fifth aspect of the present invention, there is provided a semiconductor device having a cylindrical stacked capacitor, comprising: a capacitor contact step which is a step formed at an edge portion of a wafer when forming a capacitor contact; When forming a trench that becomes the mold for the lower electrode of the mold,
And a stack stage, which is a step formed at an edge of the wafer closer to the periphery of the wafer than the position of the capacitive contact stage. The gist of claim 6 of the present invention is that the stack stage is set closer to the wafer periphery than the capacitance contact stage,
6. The semiconductor device according to claim 5, further comprising a trench formed on the capacitor contact plug and serving as a shape of the cylinder-type lower electrode. According to a seventh aspect of the present invention, there is provided a semiconductor device having a cylindrical stacked capacitor, comprising: a capacitor contact step which is a step formed at an edge of a wafer when forming a capacitor contact; When forming a trench serving as a mold for the lower electrode of the mold, except for the stack stage, which is a step formed at the edge of the wafer closer to the wafer than the position of the capacitive contact stage, and the wafer edge and the back surface And a doped silicon film formed closer to the center of the wafer than the capacitive contact stage. According to another aspect of the present invention, there is provided a semiconductor device having a cylindrical stacked capacitor, comprising: a capacitor contact step which is a step formed at an edge of a wafer when forming a capacitor contact; When forming a trench that becomes the mold for the lower electrode of the mold,
A stack stage, which is a step formed at the edge of the wafer closer to the wafer periphery than the position of the capacitive contact stage,
A doped silicon film formed on the wafer center side of the capacitive contact stage, excluding the wafer edge or the back surface.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The features of the embodiment described below are that a step portion (capacitance contact step) formed at the wafer edge portion when forming a capacitor contact and a trench serving as a cylinder type lower electrode are formed. Step (stacking step) formed at the edge of the wafer and a phosphorus-doped silicon film (DOPOS film) serving as the main body of the cylindrical lower electrode
Is to define the positional relationship with the peripheral removal portion. That is, the position of the step (stack step) formed at the wafer edge when forming a trench serving as the mold of the cylinder-type lower electrode is changed to the step (capacitance contact step) formed at the wafer edge when forming the capacity contact. ) (Outside of the wafer) and the step of removing the periphery of the phosphorus-doped silicon film (DOPOS film) (fourth step).
Step) is provided, and the mask position is set to the inside (toward the center of the wafer) of the step (capacitive contact step) formed at the wafer edge when forming the capacitive contact. As a result, peeling of the phosphorus-doped silicon film (DOPOS film) from the wafer edge can be prevented. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. 1 to 6 schematically show the wafer edge portion (wafer edge portion 100) and the cell portion 200 together. Hereinafter, only a portion related to the formation of the cylindrical stacked capacitor will be described.

FIG. 1 is an element cross-sectional view for explaining a first step in a semiconductor device manufacturing method and a semiconductor device according to an embodiment of the present invention. In the first step, first, the first substrate is formed on the semiconductor substrate 10 on which the transistor and the like are formed.
Interlayer insulation (BPSG: Boro-Phospho Si)
(License Glass) film 12, and then a second interlayer insulating film (NSG film) 14, which is used as an interlayer insulating film. Next, a capacitor contact forming process is performed to open a capacitor contact hole in a predetermined portion of the semiconductor substrate 10. Here, as shown in FIG. 1, the wafer edge portion 100 is rinsed with an organic solvent, or the wafer edge portion 100 is exposed and etched to remove the interlayer insulating film of the wafer edge portion 100. After the capacitor contact formation process, an oxide film is formed on the sidewalls on the inner wall of the capacitor contact hole, and after removing the oxide film formed on the back surface, a silicon nitride (SiN) film serving as the stopper nitride film 18 is formed. Thereafter, the bottom of the contact hole is opened again by performing etch back. At this time, it should be noted that the oxide film and the silicon nitride film on the sidewalls are similarly formed in the step portion (capacitance contact step) 19 formed in the wafer edge portion 100 when the capacitance contact is formed. . Next, after implanting phosphorus into the bottom of the contact hole, the natural oxide film and the like are removed, and the capacitor contact hole is filled with a phosphorus-doped silicon film (DOPOS film) 16. Next, a capacitor contact plug is formed by etch back, and a silicon nitride film is formed thereon again. Fig. 1
Was formed.

FIG. 2 is a sectional view of the device for explaining a second step following the first step of FIG. In the second step, as shown in FIG. 2, a cylindrical lower electrode 62 described later with reference to FIG.
A BPSG film 22 and an NSG film 24 are sequentially formed.

FIG. 3 is a sectional view of the device for explaining a third step following the second step of FIG. In the third step, as shown in FIG. 3, in the stack polysilicon formation step, a concave portion (trench) 36 serving as a mold for the cylinder-type lower electrode 62 was opened on the capacitor contact plug. At this time, the photoresist is removed by exposing the periphery and the like, and the BPSG film 22 and the NSG film 24 are removed in the same manner as in the capacitive contact formation process. Was not fully considered. In the present invention,
A step (stacking step) 32 formed in the wafer edge portion 100 when forming a trench serving as a mold of the cylinder type lower electrode 62 is replaced with a step (capacitance contact step) formed in the wafer edge portion 100 when forming a capacity contact. ) 19
Outside (the periphery of the wafer). Then, FIG.
Then, a phosphorus-doped silicon film (DOPOS film) 34 serving as a main body of a cylindrical lower electrode 62 described later is formed.

FIG. 4 is an element cross-sectional view for explaining a fourth step following the third step of FIG. As a fourth step newly provided in the present invention, as shown in FIG. 4, a resist is formed on the inner side (wafer center side) of a step portion (capacitive contact step) 19 formed on the wafer edge portion 100 at the time of forming a capacitive contact. By masking at 42, the phosphorus-doped silicon film (DOPOS film) 34 on the wafer edge portion 100 and the entire back surface (the upper surface of the semiconductor substrate 10 in the drawing) is removed. next,
SOG (silica) is applied and baked to bury silica inside the cylinder (recess (trench) 36). At this time, S near the step (capacitive contact step) 19 formed in the wafer edge portion 100 when forming the capacitive contact.
When OG is spin-coated, a phenomenon occurs in which SOG remaining without being shaken off due to surface tension is formed to be thicker than other portions. This results in a silica residue 52 (see FIG. 5) described later after the oxide film etch back in the next step.

FIG. 5 is an element cross-sectional view for explaining a fifth step (a step of removing the periphery of the phosphorus-doped silicon film (DOPOS film) 34) subsequent to the fourth step of FIG. In a fifth step, as shown in FIG. 5, the entire surface is etched back to replace silica (oxide film) with a concave portion (trench) 3 serving as a cylinder.
6 is removed except inside. Here, when SOG is spin-coated near the step portion (capacitive contact step) 19 formed on the wafer edge portion 100 at the time of forming the capacitive contact in the fourth step, the remaining SOG that has not been shaken off by the surface tension becomes another. Due to the phenomenon that the film is formed thicker than the portion, the silica remaining 52 is not removed in the fifth step. Further, the phosphorus-doped silicon film (DOPOS film) 34 is etched back to remove the phosphorus-doped silicon film (DOPOS film) 34 except for the inside of the concave portion (trench) 36 serving as a cylinder, similarly to silica (oxide film). .

FIG. 6 is a sectional view of the element for explaining a sixth step following the fifth step of FIG. Next, in the sixth step,
The BPSG film 22 and the NSG film 24 are removed with hydrofluoric acid,
As shown in FIG. 6, a cylindrical lower electrode 62 is formed.

In the prior art, the position of the step portion (capacitance contact step) 19 formed in the wafer edge portion 100 when forming the capacitor contact, and the position of the wafer edge portion when forming a trench serving as the cylinder type lower electrode 62 are formed. No consideration has been given to the relationship between the positions of the step portions (stack steps) 32 formed at 100. Also, the DOPOS film 34 in the peripheral portion was not removed. On the other hand, in the present invention, the position of the step portion (stacking step) 32 formed in the wafer edge portion 100 when forming the concave portion 36 (trench) serving as the mold of the cylindrical lower electrode 62 is determined when forming the capacitive contact. It is set outside the position of the step (capacitance contact step) 19 formed on the wafer edge part 100 (on the peripheral side of the wafer), and a phosphorus-doped silicon film (DOPOS)
A step (fourth step) of removing the periphery of the film (film) 34 is provided, and the mask position is set at the wafer edge portion 10 when forming the capacitive contact.
It is characterized in that it is set on the inner side (on the wafer center side) of the step (capacitive contact step) 19 formed at 0.

As described above, according to the present embodiment, first, the BPSG film 22 used as the cylinder mold is used.
(Capacitance contact step) 19 formed at the wafer edge portion 100 during the formation of the capacitance contact before removing the NSG film 24 and the NSG film 24 with hydrofluoric acid, and the cylindrical lower electrode 62
When forming a trench which becomes a mold of the wafer edge portion 10
By removing in advance the sidewalls formed in the step portion (stack step) 32 formed at 0, generation of particles due to peeling of the formed film and the like can be prevented, and a decrease in yield due to generation of particles can be prevented. Become like Second, a step (capacitance contact step) 19 formed on the wafer edge portion 100 when forming the capacitor contact and a step formed on the wafer edge portion 100 when forming a trench serving as a mold for the cylinder-type lower electrode 62. The effect that the silicon film or the like formed on the sidewall can be prevented from being lifted off or peeled off in a later step in the section (stack stage) 32, and the yield is prevented from lowering become able to.

It should be noted that the present invention is not limited to the above embodiments, and it is clear that the embodiments can be appropriately modified within the scope of the technical idea of the present invention. Further, the number, position, shape, and the like of the constituent members are not limited to the above-described embodiment,
The number, position, shape, and the like suitable for carrying out the present invention can be obtained. In each drawing, the same components are denoted by the same reference numerals.

[0015]

Since the present invention is configured as described above, the following effects can be obtained. First, before removing the BPSG film and the NSG film used as the cylinder mold with hydrofluoric acid, a step (capacity contact step) formed at the wafer edge when forming the capacitance contact, and the cylinder type lower electrode Preliminary removal of sidewalls at the steps (stacking steps) formed at the wafer edge when forming the mold trenches prevents generation of particles due to peeling of the formed film and prevents generation of particles. Thus, it is possible to prevent the yield from decreasing.

Second, a step (capacitance contact step) formed at the wafer edge when forming the capacitor contact and a step formed at the wafer edge when forming a trench serving as a cylinder type lower electrode type (Stack stage)
In addition, the silicon film and the like formed on the sidewalls can be prevented from being lifted off or peeled off in a later step, and a decrease in yield can be prevented.

[Brief description of the drawings]

FIG. 1 is a sectional view of an element for explaining a first step in a semiconductor device manufacturing method and a semiconductor device according to an embodiment of the present invention.

FIG. 2 is an element sectional view for explaining a second step following the first step in FIG. 1;

FIG. 3 is an element cross-sectional view for explaining a third step following the second step in FIG. 2;

FIG. 4 is an element sectional view for explaining a fourth step following the third step in FIG. 3;

FIG. 5 is an element cross-sectional view for explaining a fifth step following the fourth step in FIG. 4;

FIG. 6 is an element cross-sectional view for explaining a sixth step following the fifth step in FIG. 5;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate 12 ... 1st interlayer insulating film (BPSG film) 14 ... 2nd interlayer insulating film (NSG film) 16 ... Phosphorus-doped silicon (DOPOS) film 18 ... Stopper nitride film 19 ... Capacitance contact step 22 ... BPSG film 24 ... NSG film 32 ... Stack stage 34 ... Phosphorus-doped silicon film (DOPOS) 36 ... Concave part (trench) 42 ... Resist 52 ... Silica residue 62 ... Cylinder type lower electrode 100 ... Wafer edge part 200 ... Cell part

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/108 H01L 21/822 H01L 21/8242 H01L 27/04

Claims (8)

(57) [Claims] 1. A method of manufacturing a semiconductor device having a cylinder type stacked capacitor, capable of preventing generation of particles due to peeling of a formed film or the like and preventing a decrease in yield due to generation of particles. Forming a capacitor contact step, which is a step formed at the edge of the wafer when forming the capacitor contact, and forming the capacitor contact step at the edge of the wafer when forming a trench serving as a cylinder-type lower electrode mold Setting a stack step, which is a stepped portion, closer to the periphery of the wafer than the position of the capacitive contact step. 2. A trench having a shape of a cylinder-type lower electrode is opened on a capacitor contact plug in a state where the stack stage is set closer to the wafer periphery than the capacitor contact stage when forming the trench. 2. The method according to claim 1, further comprising the step of forming a hole. 3. A method of manufacturing a semiconductor device having a cylinder-type stacked capacitor, capable of preventing generation of particles due to peeling of a formed film and the like, and capable of preventing a reduction in yield due to generation of particles. Forming a capacitor contact step, which is a step formed at the edge of the wafer when forming the capacitor contact, and forming the capacitor contact step at the edge of the wafer when forming a trench serving as a cylinder-type lower electrode mold Setting a stack step, which is a stepped portion, on the wafer peripheral side from the position of the capacitive contact step; forming a mask on the wafer center side with respect to the capacitive contact step on the wafer edge part and / or the back surface Removing the doped silicon film. 4. A step of etching back the entire surface of the wafer except for the inside of the trench to become a cylinder to remove an oxide film, and etching back the entire surface of the wafer except for the inside of the trench to become a cylinder, and the wafer edge portion and / or the back surface. And removing the doped silicon film formed by etching back by etching back.
13. The method for manufacturing a semiconductor device according to claim 1. 5. A semiconductor device having a cylinder-type stacked capacitor, wherein a capacitor contact step, which is a step formed at an edge of a wafer when forming a capacitor contact, is used as a cylinder-type lower electrode. A semiconductor device, comprising: forming a trench; and a stack step, which is a step formed at an edge of the wafer closer to the periphery of the wafer than the position of the capacitor contact step. 6. The semiconductor device according to claim 6, further comprising a trench formed on the capacitor contact plug and serving as a cylinder-type lower electrode, with the stack stage being set closer to the wafer periphery than the capacitor contact stage. The semiconductor device according to claim 5, wherein 7. A semiconductor device having a cylinder-type stacked capacitor, wherein the capacitance contact step is a step formed at an edge of a wafer when forming a capacitance contact, and serves as a cylinder-type lower electrode. When forming the trench, a stack stage which is a step formed at the edge of the wafer closer to the wafer side than the position of the capacitance contact stage, and a wafer other than the capacitance contact stage, excluding the wafer edge and the back surface A doped silicon film formed on the center side. 8. A semiconductor device having a cylinder type stacked capacitor, wherein a capacitor contact step, which is a step formed at an edge of a wafer when forming a capacitor contact, is used as a cylinder type lower electrode. When forming the trench, a stack stage which is a step formed at an edge portion of the wafer closer to the periphery of the wafer than the position of the capacitive contact stage, and a wafer other than the capacitive contact stage, excluding the wafer edge portion or the back surface A doped silicon film formed on the center side.