JP3164021B2 - Method for manufacturing semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly, to a method for manufacturing a semiconductor memory device using an HSG (Hemi
The present invention relates to a method of manufacturing a stacked DRAM having a storage node electrode made of a polycrystalline silicon film.

[0002]

2. Description of the Related Art Even in a DRAM composed of memory cells having a stacked storage node electrode, as the memory cell size is reduced, even a memory cell with a small occupied area has a sufficient charge storage capacity. It is required to secure. To this end, three-dimensional devices have been devised to effectively increase the opposing area between the storage node electrode and the cell plate electrode, and one of them is an HSG processing technology.

The HSG processing technique is as follows, for example, with reference to Japanese Patent Application Laid-Open No. 5-304273 filed by the applicant of the present invention. For example, an N-type amorphous silicon film is patterned on the surface of the insulating film (N
An amorphous silicon film pattern is formed, and a native oxide film on the upper surface and side surfaces of the amorphous silicon film pattern is removed. Then, under ultra high vacuum of the order of 10 ^-7 Pa, 60
It is heated to a high temperature of about 0 ° C., for example, disilane (Si ₂ H
₆ ) An HSG treatment that is exposed to the molecular flow is performed. This H
By the SG process, crystal nuclei of silicon crystal grains are formed on the upper surface and side surfaces of the amorphous silicon film pattern, and the amorphous silicon film pattern is converted into a polycrystalline silicon film pattern. In the process of conversion from amorphous to polycrystalline (phase transition), silicon crystal grains grow from the crystal nuclei on the upper surface and side surfaces of the amorphous silicon film pattern. At the stage of conversion to the polycrystalline silicon film pattern, the upper surface and side surfaces are covered with hemispherical silicon crystal grains (HSG-Si).

The HSG processing described in the above-mentioned Japanese Patent Application Laid-Open No. 5-304273 is applied to the formation of a DRAM, but does not mention the specific structure and manufacturing method of a memory cell of the DRAM. The structure and manufacturing method of a DRAM formed by the present inventors using the HSG processing technology described in this patent publication will be specifically described.

First, FIG. 9 is a schematic plan view of a DRAM.
And FIG. 10 which is a schematic cross-sectional view of the DRAM and is a schematic cross-sectional view taken along line AA and line BB of FIG. 9 and has a stacked storage node electrode to which the above-described HSG processing technology is applied. The configuration of the DRAM will be described. This D
The RAM is formed according to the 0.25 μm design rule, and is as follows. Note that, here, in order to avoid complicating the drawing and to facilitate understanding, a hierarchical schematic plan view (that is, FIG. 9A shows the positional relationship between active regions, MOS transistors, word lines, and bit lines). 9 (b) shows the positional relationship between the word lines, bit lines and storage node electrodes). In FIG. 9, the (line) width of the active region, word lines and bit lines is intentionally shown. In FIG. 10, only the conductors (excluding the silicon substrate) are hatched in FIG.

A cell array region 351 is provided on the surface of the P-type silicon substrate 301, and a peripheral circuit region 352 (a semiconductor element provided in the peripheral circuit region) is provided on the surface of the P-type silicon substrate 301 surrounding the cell array region 351. Is omitted). Active regions 302 surrounded by a field oxide film 311 having a thickness of about 280 nm are regularly arranged in the cell array region 351. The minimum width and the minimum interval of the active region 302 are each 0.3 μm, and the pitch in the column direction (in the direction parallel to the bit line) and the pitch in the row direction (in the direction parallel to the word line) of the active region 302 are respectively 2.4 μm
And about 1.2 μm. The shape of the active region 351 excluding the portion adjacent to the peripheral circuit region 352 on the side related to the bit line is T-shaped, and the shape of the active region 302 in the portion adjacent to the peripheral circuit region 352 on the side related to the bit line. Is L-shaped. On the surface of the active region 302, a gate oxide film 312 with a thickness of about 8 nm is provided. Word lines 314a, 314b, 3 also serving as gate electrodes
14c, 314d, 314e, 314f, etc.
It is composed of a tungsten polycide film of about 0 nm,
Each of the plurality of active regions 3 via the gate oxide film 312
02 and extends over the peripheral circuit region 352. The line widths and intervals of the word lines 314b and the like are each 0.3 μm. On the surface of active region 302, N-type source / drain regions 315A and 315B are provided in a self-alignment manner with field oxide film 311 and word line 314a. N-type source / drain regions 315A, 3
The junction depth (X _j ) of each of the 15B is about 0.15 μm.

[0007] Field oxide film 311, gate oxide film 3
12, the cell array region 35 including the word line 314a, etc.
The surfaces of the first and peripheral circuit regions 352 are covered with a first interlayer insulating film 321. The thickness of the interlayer insulating film 321 immediately above the N-type source / drain regions 315A and 315B is about 500 nm, and the interlayer insulating film 321 is, for example, a film in which a BPSG film is stacked on a silicon oxide film (for example, an HTO film). . Interlayer insulating film 321 and gate oxide film 3
12 and a bit contact hole 322 reaching the N-type diffusion layer 315A. The diameter of the bit contact hole 322 is about 0.25 μm □. Bit lines 324a, 324b, 324c, 324d and the like connected to the N-type source / drain regions 315A via the bit contact holes 322 are provided on the surface of the interlayer insulating film 321. These bit lines 324a and the like have a film thickness of 15
A tungsten silicide film of about 0 nm,
It is orthogonal to the word lines 314 a and the like via the interlayer insulating film 321 and extends over the peripheral circuit region 352.

The interlayer insulating film 3 including the bit lines 324a and the like
The surface of 21 is covered with a second interlayer insulating film 331 made of a silicon oxide insulating film having a thickness of about 400 nm. N-type source / drain region 31 penetrating through interlayer insulating film 331, interlayer insulating film 321 and gate oxide film 312
A node contact hole 332 reaching 5B is provided. The diameter of the node contact hole 332 is also 0.25 μm □
These node contact holes 332 are filled with contact plugs 333 made of a conductor film (for example, an N-type polycrystalline silicon film).

On the surface of the interlayer insulating film 331, each is directly connected to a contact plug 333 and has a thickness of 800 nm.
A storage node electrode 334 composed of an m-type N-type polycrystalline silicon film pattern is provided. The length (in the direction parallel to the bit line 324a and the like) and the width (in the direction parallel to the word line 314a and the like) of the storage node electrode 334 are about 0.9 μm and about 0.3 μm, respectively. Is 0.3μ
m. One row (for example, belonging to word line 314a) of storage node electrode 334 provided adjacent to peripheral circuit region 352 and near the end of cell array region 351
And two columns (for example, belonging to bit lines 324a and 324b)
Except for the storage node electrode 334, the top and side surfaces of the storage node electrode 334 are covered with HSG-Si. The upper surface and the side surface of the storage node electrode 334 and the upper surface of the interlayer insulating film 331 between the storage node electrode 334 are directly covered with the capacitor insulating film 336. The thickness of the capacitor insulating film 336 at least at a portion covering the upper surface and the side surface of the storage node electrode 334 is about 5 nm in terms of a silicon oxide film. For example, the cell plate electrode 337 made of an N-type polycrystalline silicon film having a thickness of about 150 nm to 200 nm
The storage node electrode 334 is covered via the reference numeral 36.

Next, FIG. 11 which is a schematic cross-sectional view of a DRAM manufacturing process and is a schematic cross-sectional view taken along the line AA in FIG.
FIG. 12 which is a schematic cross-sectional view of a manufacturing process of the AM and is a schematic cross-sectional view taken along the line BB of FIG. 9 and FIG. 9 and FIG. 10 together with reference to FIG. 9 and FIG. A method for manufacturing a DRAM having the storage node electrode of FIG.

First, a cell array region 351 and a device isolation region of the peripheral circuit region 352 on the surface of the P-type silicon substrate 301 have a thickness of about 280 nm (for example, LOCOS).
A (type) field oxide 311 is formed. In the active region 302 of the cell array region 351 (the active region of the peripheral circuit region 352 is not shown), a gate oxide film 312 having a thickness of about 8 nm is formed by thermal oxidation.
An N-type polycrystalline silicon film (having a high concentration) having a thickness of about 100 nm (not explicitly shown) is formed on the entire surface. This N-type polycrystalline silicon film is formed by a method in which phosphorus is thermally diffused into a non-doped polycrystalline silicon film by LPCVD, or LPCVD using monosilane (SiH ₄ ) as a source gas and phosphine (PH ₃ ) as an impurity gas. To form an N-type amorphous silicon film and heat-treat it. Further, a tungsten silicide film having a thickness of about 100 nm is formed by, for example, sputtering. The laminated conductor film composed of the tungsten silicide film and the N-type polycrystalline silicon film is sequentially patterned by anisotropic etching, and word lines 314a, 314b, 31 each composed of a tungsten polycide film having a thickness of about 200 nm.
4c, 314d, 314e, 314f, etc. (and gate electrodes of peripheral circuits, not shown) are formed [FIG.
FIG.

Using these word lines 314a and the like and the field oxide film 311 as a mask, 40 keV, 2 × 10 ¹³
N-type source / drain regions 315A and 315B are formed in the active region 302 and the like by ion implantation of phosphorus of about cm ⁻² or the like. Note that the N-type source / drain regions 315A,
Although 315B has a low concentration at this stage, it is 30 ke after forming the bit contact hole and the node contact hole.
V, about 5 × 10 ¹⁴ cm ^-2 of contact ion implantation of phosphorus is performed, and these N-type source / drain regions 315 are formed.
A, 315B are finally a low concentration N-type region and a medium concentration N
An N-type diffusion layer having a mold region. Although not shown, the N-type source / drain regions (and the P-type source / drain regions) constituting the MOS transistors of the peripheral circuit are N-type source / drain regions 315A and 315B.
[FIG. 9, FIG. 10].

Next, an HTO film (not explicitly shown) on the entire surface,
A BPSG film (not explicitly shown), a flattening process, and the like are performed, and N-type source / drain regions 315A and 315B are formed.
First interlayer insulating film 3 having a thickness of about 500 nm immediately above
21 are formed. Interlayer insulating film 321, gate oxide film 31
2 are sequentially anisotropically etched to form a bit contact hole 322 reaching the N-type source / drain region 315A. LP at about 100 Pa using tungsten hexafluoride (WF ₆ ) and dichlorosilane (SiH ₂ Cl ₂ ) as a source gas and argon (Ar) as a carrier gas.
The CVD is performed at about 600 ° C. to form a tungsten silicide film (not shown) having a thickness of about 150 nm on the entire surface. This tungsten silicide film is patterned by anisotropic etching, and bit lines 324 a and 324 connected directly to N-type source / drain regions 315 A via bit contact holes 322.
b, 324c, 324d, etc. [FIG. 9, FIG.
0].

Subsequently, a silicon oxide-based insulating film is formed and planarized on the entire surface, and a second film having a thickness of about 400 nm is formed.
Is formed. Interlayer insulating film 331,
The interlayer insulating film 321 and the gate oxide film 312 are sequentially anisotropically etched to form N-type source / drain regions 315.
A node contact hole 332 reaching B is formed. For example, a contact plug 333 filling the node contact hole 332 is formed by forming an N-type polycrystalline silicon film by LPCVD or the like. LPCVD at about 10 ⁻³ Pa to 20 ⁻⁴ Pa using monosilane (SiH ₄ ) as a source gas and phosphine (PH ₃ ) as an impurity gas is performed, for example, at 510 ° C. An N-type amorphous silicon film 343 having a thickness and an impurity concentration of about 1 × 10 ¹⁹ cm ⁻³ to 2 × 10 ²⁰ cm ⁻³ is formed [FIGS. a)].

Thereafter, the N-type amorphous silicon film 343 is patterned by anisotropic etching to form an N-type amorphous silicon film pattern 344 [FIG.
(B), FIG. 12 (b)].

After the natural oxide film on the upper surface and the side surface of the N-type amorphous silicon film pattern 344 is removed, monosilane (Si) is applied at about 600 ° C. under an ultra-high vacuum of the order of 10 ⁻⁶ Pa.
When exposed to the H ₄ ) molecular flow or disilane (Si ₂ H ₆ ) molecular flow, the N-type polycrystalline silicon film pattern is converted into an N-type polycrystalline silicon film pattern to form the storage node electrode 334. At this time, as described above, one row (for example, belonging to the word line 314a) of the storage node electrode 334 and two columns (for example, the bit lines 324a, 324b) are provided adjacent to the peripheral circuit region 352 and near the end of the cell array region 351. Except for the storage node electrode 334 (belonging to 324b), the upper surface and side surfaces of the storage node electrode 334 are covered with HSG-Si. However, the storage node electrode 3 belonging to the word line 314a, the bit line 324a or the bit line 324b
34, a line (word line 314a) connecting the side surfaces of the storage node electrode located at the outermost periphery of the cell array region 351.
Circuit region 3 of storage node electrode 334 belonging to
From the line connecting the side surfaces of the storage node electrode 334 belonging to the bit line 324a to the side surface of the peripheral circuit region 352 side of the bit line 324a) within a range of 0.7 μm to 0.9 μm.
The grain size of the silicon crystal grains on the side or top surface of the storage node electrode 334 is small, and the density of HSG-Si is low [FIGS. 11 (c) and 12 (c)].

Next, a capacitive insulating film (not explicitly shown) is formed on the entire surface.
Is formed. The capacitance insulating film in a portion covering the upper surface and the side surface of the storage node electrode 334 has an ONO structure,
The equivalent silicon oxide film thickness of the capacitive insulating film in these portions is about 5 nm. 150 nm to 200 n film thickness on the entire surface
An m-type (high concentration) N-type polycrystalline silicon film is formed. The N-type polycrystalline silicon film and the capacitor insulating film are sequentially patterned to form a capacitor insulating film 336 and a cell plate electrode 337 (FIGS. 9 and 10).

[0018]

As described above, one row (× 2) of storage node electrodes 334 belonging to, for example, a word line 314 a provided adjacent to the peripheral circuit region 352 and near the end of the cell array region 351. And two columns (× 2) of storage node electrodes 334 belonging to bit lines 324a and 324b, for example,
Conversion is inadequate. Therefore, one row (for example, belonging to the word line 314a) of memory cells provided near the peripheral circuit area 352 and near the end of the cell array area 351 and 2
The charge storage capacity value with the memory cells of the column (for example, belonging to the bit lines 324a and 324b) becomes lower than the charge storage capacity values of the other memory cells, and the electric storage capacity value of each memory cell by the HSG processing. The goal of increasing the number of people cannot be completely achieved. On the other hand, if, for example, the occupied area of the cell array region 352 is increased to add 2 × 2 rows and 2 × 2 columns of dummy cells per one cell array region 351, the original purpose is achieved.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor memory device in which each memory cell is completely HSG-controlled without providing a dummy cell and suppressing the effective area of the cell array region from increasing. It is in.

[0020]

According to a first aspect of the method of manufacturing a semiconductor memory device of the present invention, a dummy region is provided on a surface of a P-type silicon substrate so as to surround a cell array region provided on the surface of the P-type silicon substrate. And a field oxide film is formed on an element isolation region on the surface of the P-type silicon substrate provided with a peripheral circuit region on the surface of the P-type silicon substrate around the dummy region. And a plurality of first active regions regularly arranged in the cell array region and a required dummy region excluding a peripheral circuit region related to a word line and a dummy region sandwiched between the cell array regions. A step of partitioning a second active region provided in the portion, forming a gate oxide film in the first and second active regions, and forming the first active region via these gate oxide films. Forming a gate electrode also serving as a word line on the region, forming an N-type source / drain region and an N-type diffusion layer in the first and second active regions, respectively; Forming a first interlayer insulating film covering the first interlayer insulating film, forming a bit contact hole penetrating through the first interlayer insulating film and the gate oxide film and reaching one of the N-type source / drain regions; Forming a bit line extending in a direction orthogonal to the word line and connected to one of the N-type source / drain regions through the bit contact hole on the surface of the first substrate; Forming a second interlayer insulating film covering the second interlayer insulating film, and penetrating the second interlayer insulating film, the first interlayer insulating film, and the gate oxide film, respectively, to form the other of the N-type source / drain regions; When reaching the N-type diffusion layer Forming an N-type amorphous silicon film on the entire surface, patterning the amorphous silicon film, and forming the N-type source through the node contact hole in the cell array region. A first amorphous silicon film pattern connected to the other of the drain regions is formed, and the dummy region has a predetermined width at a position at a required distance from these first amorphous silicon film patterns; Forming a second amorphous silicon film pattern having a shape surrounding the cell array region by applying a pressure to the first and second amorphous silicon film patterns under a high temperature and an ultra-high vacuum. Exposure to molecular flow or disilane molecular flow gives
The upper surface and the side surfaces of the second amorphous silicon film pattern are covered with hemispherical silicon crystal grains, and the first and second amorphous silicon film patterns are respectively made of first and second polycrystalline silicon. HSG to convert to film pattern
Forming a storage node electrode and a dummy electrode made of the first and second polycrystalline silicon film patterns by forming the same, and forming a capacitive insulating film covering at least the upper surface and side surfaces of the storage node electrode and the dummy electrode. Forming a conductive film on the entire surface, patterning the conductive film, and forming a cell plate electrode covering the storage node electrode and the dummy electrode via the capacitor insulating film. Preferably, the N-type diffusion layer is provided only on the side of the dummy region where the bit line extends. More preferably, the predetermined width is at least 1.0 μm.

Second Embodiment of Manufacturing Method of Semiconductor Storage Device of the Present Invention
According to the aspect, a field oxide film is formed on an element isolation region on a surface of a P-type silicon substrate provided with a peripheral circuit region on a surface of a P-type silicon substrate around a cell array region provided on a surface of the P-type silicon substrate Forming a plurality of active regions regularly arranged in the cell array region, forming a gate oxide film on the active region, and forming the gate oxide film on these active regions via these gate oxide films. Forming a gate electrode also serving as a word line, forming N-type source / drain regions in these active regions; forming a first interlayer insulating film covering the surface of the P-type silicon substrate; A bit contact hole penetrating through the interlayer insulating film and the gate oxide film and reaching one of the N-type source / drain regions is formed, and a direction perpendicular to the word line is formed on the surface of the first interlayer insulating film. Forming a bit line extending and connected to one of these N-type source / drain regions through these bit contact holes; and forming a second interlayer insulating film covering the first interlayer insulating film. Forming a node contact hole penetrating through the second interlayer insulating film, the first interlayer insulating film and the gate oxide film and reaching the other of the N-type source / drain regions; An amorphous silicon film is formed, and the amorphous silicon film is patterned to form a first amorphous silicon film connected to the other of the N-type source / drain regions through the node contact hole in the cell array region. A second pattern having a shape surrounding the cell array region at a position spaced from the first amorphous silicon film pattern by a predetermined distance.
Forming an amorphous silicon film pattern of
Converting the first and second amorphous silicon film patterns into a storage node electrode and an N-type polycrystalline silicon film pattern, respectively; A capacitor insulating film covering the side surface is formed, a conductor film is formed on the entire surface, and the conductor film is etched using the photoresist film pattern covering the cell array region as a mask. Forming a cell plate electrode covering the node electrode, and further sequentially etching and removing the capacitive insulating film and the polycrystalline silicon film pattern using the photoresist film pattern as a mask. Preferably, the predetermined interval is equal to or more than twice the thickness of the conductor film and twice the alignment margin, and is equal to or less than 2.0 μm.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Prior to the description of the embodiments of the present invention, a technical study process by the present inventors, which has reached the present invention, will be described.

By subjecting the amorphous silicon film pattern provided on the surface of the interlayer insulating film made of a silicon oxide-based insulating film to the above HSG process, the exposed surface (side surface and upper surface) of the amorphous silicon film pattern ) To HSG-Si
Is formed because the formation of crystal nuclei of silicon crystal grains in this process selectively occurs on the exposed surface of the amorphous silicon film pattern as compared with the surface of the interlayer insulating film. According to the knowledge obtained from the experimental study results of the present inventors, since this treatment is performed at a high temperature of about 600 ° C. under an ultra-high vacuum of the order of 10 ⁻⁶ Pa, the adsorption in the interlayer insulating film is suppressed. Silanol bonds (Si-O) such as water evaporation and interlayer insulating film surface
H) is released from H) due to the dissociation of the OH group, and a natural oxide film is easily formed on the exposed surface of the amorphous silicon film pattern, which hinders the formation of HSG-Si (HSG-Si). Formation failure).

As one method of countermeasures against the HSG-Si formation defect, a method of avoiding separation of moisture from the interlayer insulating film and the like can be considered. For example, if the upper surface of the interlayer insulating film is covered with the silicon nitride film, the above-described desorption of moisture from the interlayer insulating film during the HSG process is avoided. However, when the upper surface of the interlayer insulating film is covered with the silicon nitride film (in contrast to the case where the interlayer insulating film is formed of a silicon oxide-based insulating film), the silicon crystal grains during the HSG process are reduced. The above selectivity for the formation of crystal nuclei cannot be obtained. As a result, crystal nuclei of silicon crystal grains are also formed on the surface of the silicon nitride film by the HSG treatment, and the side surface and the upper surface are covered with HSG-Si (the amorphous silicon film pattern is converted). 2.) Silicon crystal grains are also formed in an island shape on the surface of the interlayer insulating film between the storage node electrodes, so that leakage between memory cells is likely to occur.

The embodiment of the present invention relates to the case where the (second) interlayer insulating film immediately below the storage node electrode is made of a silicon oxide based insulating film. As described above, when the second interlayer insulating film is made of a silicon oxide-based insulating film, the above-mentioned HSG-Si failure is caused (with a width) in the amorphous silicon film pattern provided at the edge of the cell array region. It is occurring in a concentrated manner. The first embodiment of the present invention focuses on this phenomenon. In addition, the present inventors have examined the relationship between the exposed width of the upper surface of the interlayer insulating film and the HSG-Si conversion defect in a portion adjacent to the amorphous silicon film pattern provided at the edge of the cell array region. Done. The second embodiment of the present invention is based on the knowledge obtained from the study results.

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a schematic plan view of a DRAM, and FIG.
FIG. 2 is a schematic cross-sectional view of the AM and is a schematic cross-sectional view taken along line AA and BB in FIG. 1.
DRAM according to an example of the first embodiment is 0.25 μm
It is formed by the design rules and is as follows.
Note that, here, in order to avoid complicating the drawings and to facilitate understanding, a hierarchical schematic plan view (that is, FIG.
FIG. 1A shows the positional relationship between the active region, the MOS transistor, the word line and the bit line, and FIG. 1B shows the positional relationship between the word line, the bit line and the storage node electrode. In FIG. 1 (a), the active regions, word lines and bit lines (line) widths and intervals are intentionally shifted, and in FIG. 1 (a), the N-type diffusion layer formed in the second active region has a left side. The hatching consisting of the downward dotted line is applied. In FIG. 2, only the conductors (excluding the silicon substrate) are hatched by solid lines.

The cell array region 151 is provided on the surface of the P-type silicon substrate 101, and the surface of the P-type silicon substrate 101 surrounding the cell array region 151 is, for example, 1.2.
A dummy region 153 having a predetermined width of μm is provided, and a peripheral circuit region 152 is provided on the surface of the P-type silicon substrate 101 surrounding the dummy region 153. The predetermined width of the dummy region 153 is equal to the predetermined width of a dummy electrode described later,
In consideration of the width at which SG-Si failure occurs, the thickness is preferably at least 1.0 μm. At least a part of the dummy region 153 in the present example of the first embodiment can be provided with a semiconductor element forming a peripheral circuit, unlike a normal dummy region. Note that illustration of semiconductor elements provided in the peripheral circuit region 152 (and the dummy region 153) is omitted.

The cell array region 151 has a thickness of 280 n.
The first active regions 102 surrounded by about m field oxide films 111 are regularly arranged. Active area 102
Have a minimum width and a minimum interval of 0.3 μm, respectively.
The pitch in the column direction (parallel to the bit line) and the pitch in the row direction (parallel to the word line) of the active region 102 are about 2.4 μm and about 1.2 μm, respectively. Peripheral circuit area 1 on the bit line side via dummy area 153
The shape of the active region 151 excluding the portion adjacent to the region 52 is T
The active region 102 at a portion adjacent to the peripheral circuit region 152 on the side related to the bit line via the dummy region 153 has an L-shape. The dummy region 153 located between the peripheral circuit region 152 related to the bit line and the cell array region 151 has the second active region 10
3 are provided. The width of the active region 103 is 0.3 μm
The distance between the active region 102 and the indirect region 103 is at least about 0.3 μm. Active region 102,
On the surface of 103, a gate oxide film 112 having a thickness of about 8 nm is provided.

Word lines 114a and 114 also serving as gate electrodes
4b, 114c, 114d, 114e, 114f, etc.
At least a dummy region 153 is formed of a tungsten polycide film having a thickness of about 200 nm and traverses over the plurality of active regions 102 via the gate oxide film 112.
Extending above. The line widths and intervals of the word lines 114b and the like are each 0.3 μm. Field oxide film 111 and word line 114a are formed on the surface of active region 102.
N-type source / drain regions 115A,
115B is provided. On the surface of the active region 103, an N-type diffusion layer 115C is provided in a self-aligned manner with the field oxide film 111. X _j of each of the N-type source / drain regions 115A and 115B and the N-type diffusion layer 115C is about 0.15 μm.

Field oxide film 111, gate oxide film 1
12, the cell array region 15 including the word lines 114a, etc.
1, the surface of the peripheral circuit region 152 and the surface of the dummy region 153 are covered with the first interlayer insulating film 121. N-type source / drain regions 115A, 11 of interlayer insulating film 121
The film thickness directly above 5B or the like is about 500 nm, and the interlayer insulating film 121 is made of, for example, a film in which a BPSG film is laminated on an HTO film. Interlayer insulating film 121 and gate oxide film 11
2 and a bit contact hole 122 reaching the N-type diffusion layer 115A. The diameter of the bit contact hole 122 is about 0.25 μm □. On the surface of the interlayer insulating film 121, bit lines 124a, 124b, 124c, 124d and the like connected to the N-type source / drain regions 115A via the bit contact holes 122 are provided. These bit lines 124a and the like have a thickness of 150
nm of a tungsten silicide film, and intersects orthogonally with the word lines 114a and the like via the interlayer insulating film 121,
It extends over the peripheral circuit region 152 across the N-type diffusion layer 105C.

The interlayer insulating film 1 including the bit lines 124a and the like
The surface of 21 is covered with a second interlayer insulating film 131 made of a silicon oxide based insulating film having a thickness of about 400 nm. In the cell array region 151, N is formed through the interlayer insulating film 131, the interlayer insulating film 121, and the gate oxide film 112.
A node contact hole 132 reaching the mold source / drain region 115B is provided. The dummy region 153 is provided with at least one contact hole 132C penetrating through the interlayer insulating film 131, the interlayer insulating film 121, and the gate oxide film 112 and reaching the N-type diffusion layer 115C. The diameter of the node contact hole 132 is also 0.25 μm □
It is about. The diameter of the contact hole 132C is also, for example, 0.
It is about 25 μm square. These node contact holes 13
2. The contact plug 132 made of a conductor film (for example, an N-type polycrystalline silicon film)
33.

Each of the node contact holes 13 is formed on the surface of the interlayer insulating film 131 immediately above the cell array region 151.
2 is provided with a storage node electrode 134 connected to the N-type source / drain region 115 </ b> B via the contact plug 133 provided in the second. The contact hole 13 is formed on the surface of the interlayer insulating film 131 immediately above the dummy region 153.
A dummy electrode 135 connected to the N-type diffusion layer 115C via a contact plug 133 provided in 2C is provided. Storage node electrode 134, dummy electrode 1
Reference numeral 35 denotes an N-type polycrystalline silicon film pattern having a thickness of about 800 nm. Storage node electrode 134
Has a length (in a direction parallel to the bit line 124a and the like) and a width (in a direction parallel to the word line 114a and the like) of about 0.9 μm and 0.3 μm, respectively. 0.3 μm. The distance between the outermost storage node electrode 134 (of the storage node electrodes 134 provided on the cell array region 151) and the dummy electrode 135 is, for example, about 0.3 μm.

In the first embodiment, unlike the conventional DRAM subjected to the HSG processing shown in FIGS. 9 to 12, all the storage node electrodes 134 provided on the cell array region 131 are different. Top and side surfaces are HSG-Si
Covered by On the other hand, in the dummy electrode 135, the side surface on the peripheral circuit region 152 side and 0.7 μm
On the upper surface having a width of about 0.9 μm, HSG failure occurs, and the grain size of silicon crystal grains is small, and the density of HSG-Si is low. However, the side surface of the dummy electrode 135 on the cell array region 151 side and 0.3 mm
HSG-Si is formed on the upper surface having a width of about μm to 0.5 μm. The upper surface and the side surface of the storage node electrode 134 and the dummy electrode 135 and the upper surface of the interlayer insulating film 131 between the storage node electrode 134 and the dummy electrode 1
The upper surface of the interlayer insulating film 131 between the storage node electrode and the storage node electrode is directly covered with the capacitor insulating film 136. The thickness of the capacitor insulating film 136 at least at a portion covering the upper surface and the side surface of the storage node electrode 134 and the dummy electrode 135 is about 5 nm in terms of a silicon oxide film. For example, a film thickness of 150 nm to 200 nm
The cell plate electrode 137 made of an N-type polycrystalline silicon film covers the storage node electrode 134 and the dummy electrode 135 via the capacitor insulating film 136.

In the present example of the first embodiment, an N-type diffusion layer 115C is provided in the dummy region 153, and the dummy electrode 135 is electrically connected to the N-type diffusion layer 115C. In addition, it is possible to prevent the dummy electrode 135 covered with the cell plate electrode 137 via the capacitor insulating film 136 from being in an electrically floating state. Further, since the second active region 103 is not provided in the dummy region 153 between the peripheral circuit region 152 and the cell array region 151 related to the word line, the first active region 103 is not provided.
In this example of the embodiment, the dummy area 1
53 can be effectively used as a peripheral circuit area. That is, the area of the effective cell array region (the cell array region 1) according to the present example of the first embodiment.
51 (the value obtained by adding the area of the portion substantially functioning as the dummy region (2 × 1 row)) to the area of the effective cell array region provided with the dummy cells in the conventional DRAM is 2 × 2 columns. The effective area of the cell array region can be reduced accordingly.

The dummy electrode 135 according to the present example of the first embodiment has a band-like and annular shape having a width of, for example, about 1.2 μm, and
1 surrounding the storage node electrode 134 provided thereon. However, in the first embodiment, the shape of the dummy electrode 135 is not limited to the shape of the present example. In addition, the second region provided in the dummy region 153
The shape of the active region 103 (and the N-type diffusion layer 115C) is not limited to the shape of the present embodiment. However, a portion of the dummy region 153 interposed between the peripheral circuit region 152 related to the word line and the cell array region 151
It is not preferable to provide the second active region in the second region. If the second active region is provided in such a dummy region, the effective area of the cell array region becomes equal to the effective cell array region when the dummy cell is provided in the conventional DRAM. Furthermore, since the N-channel MOS transistors are vertically stacked in the dummy region in this portion due to the presence of the word line, all the N-type diffusion regions provided in the second active region divided by the word line are provided. It is essential to provide a contact hole having the same shape as the contact hole 132C for the layer.

FIG. 3 is a schematic cross-sectional view of the DRAM manufacturing process, taken along the line AA in FIG. 1, and FIG. 3 is a schematic cross-sectional view of the DRAM manufacturing process, taken along the line BB in FIG. Referring to FIG. 4 and FIG. 1 and FIG. 2 together, a DRAM according to an example of the first embodiment will be described.
Is formed as follows.

First, a field oxide film 111 (for example, of LOCOS type) having a film thickness of about 280 nm is formed in the cell array region 151, the dummy region 153, and the element isolation regions of the peripheral circuit region 152 on the surface of the P-type silicon substrate 101. In the cell array region 151 and the dummy region 153, the first active region 102 and the second active region 103 (the active region provided in the peripheral circuit region 152 and the dummy region 153 associated with the peripheral circuit are provided (see above). The active region (which is different from the second active region 103) is not shown), but is partitioned. In the active regions 102 and 103 of the cell array region 151 and the dummy region 153, a gate oxide film 112 having a thickness of about 8 nm is formed by thermal oxidation. An N-type polycrystalline silicon film (having a high concentration) having a thickness of about 100 nm (not explicitly shown) is formed on the entire surface. The method of forming the N-type polycrystalline silicon film includes a method of thermally diffusing phosphorus into a non-doped polycrystalline silicon film by LPCVD,
Alternatively, a method may be used in which an N-type amorphous silicon film is formed by LPCVD using monosilane (SiH ₄ ) as a source gas and phosphine (PH ₃ ) as an impurity gas, and heat-treated. Further, a tungsten silicide film having a thickness of about 100 nm is formed by, for example, sputtering.
The laminated conductor film composed of the tungsten silicide film and the N-type polycrystalline silicon film is sequentially patterned by anisotropic etching, and the word lines 114a, 114b,
114c, 114d, 114e, 114f and the like (and, not shown, gate electrodes of peripheral circuits) are formed (FIGS. 1 and 2).

The N-type source / drain regions 115A and 115A and the N-type source / drain regions 115A and N are implanted by ion implantation of phosphorus of about 40 keV and about 2 × 10 ¹³ cm ^{−2 using} the word lines 114a and the field oxide films 111 and 112 as masks. -Type source / drain region 115B and N-type diffusion layer 115
C and the like are formed in the active region 102 and the active region 103 and the like. The N-type source / drain regions 115A, the N-type source / drain regions 115B, and the N-type diffusion layers 115C
Are low concentration at this stage, but after formation of the bit contact hole or the node contact hole, 30 keV, 5
A contact ion implantation of about 10 ¹⁴ cm ^-2 of phosphorus is performed, and these N-type source / drain regions 115A, N
-Type source / drain region 115B and N-type diffusion layer 11
5C finally becomes an N-type diffusion layer having a low-concentration N-type region and a medium-concentration N-type region. Although not shown, the N-type source / drain regions (and the P-type source / drain regions) constituting the MOS transistor of the peripheral circuit
Are N-type source / drain regions 115A,
This is performed before and after the formation of the drain region 115B and the N-type diffusion layer 115C [FIGS. 1 and 2].

Next, an HTO film (not shown in the figure) is formed on the entire surface,
A BPSG film (not explicitly shown), a flattening process, and the like are performed to form N-type source / drain regions 115A and 115B.
A first interlayer insulating film 121 having a thickness of about 500 nm immediately above the above is formed. Interlayer insulating film 121, gate oxide film 1
12 are sequentially anisotropically etched to form bit contact holes 122 reaching the N-type source / drain regions 115A and the like.
Are formed. LPCVD at about 100 Pa using tungsten hexafluoride (WF ₆ ) and dichlorosilane (SiH ₂ Cl ₂ ) as source gas and argon (Ar) as carrier gas at about 600 ° C. A tungsten silicide film (not explicitly shown) having a thickness of about 150 nm is formed. This tungsten silicide film is patterned by anisotropic etching, and bit lines 124a, 124 connected directly to N-type source / drain regions 115A through bit contact holes 122.
24b, 124c, 124d, etc. are formed (FIGS. 1 and 2).

Subsequently, a silicon oxide-based insulating film is formed and planarized on the entire surface, and a second film having a thickness of about 400 nm is formed.
Is formed. Interlayer insulating film 131,
The interlayer insulating film 121 and the gate oxide film 112 are sequentially anisotropically etched to form a node contact hole 132 reaching the N-type source / drain region 115B in the cell array region 151 and an N-type diffusion layer in the dummy region 153. A contact hole 132C reaching 103 is formed.
For example, by forming an N-type polycrystalline silicon film by LPCVD or the like, the node contact holes 132 and the contact holes 13 are formed.
Contact plugs 133 each filling 2C are formed. 10 ^-3 Pa to 20 using monosilane (SiH ₄ ) as a source gas and phosphine (PH ₃ ) as an impurity gas.
LPCVD at about ^-4 Pa is performed, for example, at 510 ° C., and a 1 × 1
An N-type amorphous silicon film 143 having an impurity concentration of about 0 ¹⁹ cm ^{−3 to} 2 × 10 ²⁰ cm ⁻³ is formed [FIG.
(A), FIG. 4 (a)].

Thereafter, the N-type amorphous silicon film 143 is patterned by anisotropic etching, and an N-type amorphous silicon film pattern 144 is formed on the cell array region 151.
Is formed, and an N-type amorphous silicon film pattern 145 is formed in the dummy region 153 [FIGS.
(B)].

N-type amorphous silicon film pattern 144, 1
After removing the native oxide film on the top and side surfaces of 45, 6
Monosilane (SiH ₄ ) molecular flow or disilane (Si ₂ H ₆ ) under an ultra-high vacuum of the order of 10 ⁻⁶ Pa at around 00 ° C.
Exposure to molecular flow, N-type polycrystalline silicon film pattern 1
44 and 145 are converted into N-type polycrystalline silicon film patterns to form storage node electrodes 134 and dummy electrodes 135. At this time, as described above, all the storage node electrodes 13 provided on the cell array region 131 are
4 are covered with HSG-Si. On the other hand, the side surface of dummy electrode 135 adjacent to peripheral circuit region 152 and 0.7 μm to 0.9 μm
An HSG defect occurs on the upper surface having a width of about the same size, the grain size of silicon crystal grains is small, and the density of HSG-Si is low. However, the side surface of the dummy electrode 135 on the side of the cell array region 151 and 0.3 μm to 0.
HSG-Si is formed on the upper surface having a width of about 5 μm [FIGS. 3C and 4C].

Thereafter, a capacitance insulating film (not explicitly shown) is formed on the entire surface. The capacitance insulating film in the portion covering the upper surface and the side surface of the storage node electrode 134 has an ONO structure, and the equivalent thickness of the capacitance insulating film in these portions is about 5 nm as a silicon oxide film. Film thickness of 150 nm to 20 on the entire surface
An approximately 0 nm (high concentration) N-type polycrystalline silicon film is formed. The N-type polycrystalline silicon film and the capacitor insulating film are sequentially patterned to form a capacitor insulating film 136 and a cell plate electrode 137 (FIGS. 1 and 2).

In the first embodiment, a dummy region having a form surrounding the cell array region is required.
In the second embodiment of the present invention, no dummy area is required.

FIG. 5 is a schematic plan view of a DRAM, and FIG.
Referring to FIG. 6 which is a schematic cross-sectional view of the AM and is a schematic cross-sectional view taken along line AA and line BB in FIG.
DRAM according to an example of the first embodiment is also 0.25 μm.
It is formed by the design rules and is as follows.
In this case, too, in order to avoid complicating the drawing and to facilitate understanding, a hierarchical schematic plan view (that is, FIG.
FIG. 5A shows the positional relationship between the active region, the MOS transistor, the word line and the bit line, and FIG. 5B shows the positional relationship between the word line, the bit line and the storage node electrode. In FIG. 6, the active regions, word lines and bit lines are intentionally shifted in (line) width and spacing, and in FIG. 6 (excluding the silicon substrate).
Only the conductors are hatched by solid lines.

A cell array region 251 is provided on the surface of P-type silicon substrate 201, and a peripheral circuit region 252 is provided on the surface of P-type silicon substrate 201 surrounding cell array region 251. Note that illustration of a semiconductor element provided in the peripheral circuit region 252 is omitted. In the cell array region 251, active regions 202 surrounded by a field oxide film 211 having a thickness of about 280 nm are regularly arranged. The minimum width and the minimum interval of the active region 202 are each 0.3 μm, and the pitch in the column direction (parallel to the bit line) and the pitch in the row direction (parallel to the word line) of the active region 202 are each about 2.4 μm. And 1.2 μm
It is about. Peripheral circuit area 252 related to bit line
The shape of the active region 251 excluding the portion adjacent to the bit line has a T shape, and the shape of the active region 202 at the portion adjacent to the peripheral circuit region 252 on the side related to the bit line has an L shape. On the surface of the active region 202, a gate oxide film 212 having a thickness of about 8 nm is provided.

Word lines 214a, 21 also serving as gate electrodes
4b, 214c, 214d, 214e, 214f, etc.
It is composed of a tungsten polycide film having a thickness of about 200 nm, and extends over the plurality of active regions 202 through the gate oxide film 212 to the peripheral circuit region 252. The line width and spacing of the word lines 214b and the like are each 0.3 μm. On the surface of active region 202, N-type source / drain regions 215A and 215B are self-aligned with field oxide film 211 and word line 214a.
Is provided. N-type source / drain region 215
_{Xj of} A, 215B is about 0.15 μm.

Field oxide film 211, gate oxide film 2
12, the cell array region 25 including the word lines 214a, etc.
1, the surface of the peripheral circuit region 252 is the first interlayer insulating film 22
Covered by 1. The thickness of the interlayer insulating film 221 immediately above the N-type source / drain regions 215A and 215B is 5
The thickness of the interlayer insulating film 221 is, for example, H
It is composed of a film in which a BPSG film is laminated on a TO film. A bit contact hole 222 penetrating through the interlayer insulating film 221 and the gate oxide film 212 and reaching the N-type diffusion layer 215A is provided. The diameter of the bit contact hole 222 is 0.25μ.
It is about m □. On the surface of the interlayer insulating film 221, bit lines 224a, 224b connected to the N-type source / drain regions 215A via the bit contact holes 222 are formed.
224c, 224d and the like are provided. The bit lines 224a and the like are formed of a tungsten silicide film having a thickness of about 150 nm, and extend orthogonally to the word lines 214a and the like via the interlayer insulating film 221 and extend on the peripheral circuit region 252.

The interlayer insulating film 2 including the bit line 224a
The surface of 21 is covered with a second interlayer insulating film 231 made of a silicon oxide insulating film having a thickness of about 400 nm. The cell array region 251 has N through the interlayer insulating film 231, the interlayer insulating film 221 and the gate oxide film 212.
A node contact hole 232 reaching the mold source / drain region 215B is provided. Node contact hole 2
32 also has a diameter of about 0.25 μm □. The node contact hole 232 is filled with a contact plug 233 made of a conductor film (for example, an N-type polycrystalline silicon film).

On the surface of the interlayer insulating film 231 immediately above the cell array region 251, each of the node contact holes 23 is formed.
2 is provided with a storage node electrode 234 connected to the N-type source / drain region 215B via the contact plug 233 provided in the second. Storage node electrode 234 is formed of an N-type polycrystalline silicon film pattern having a thickness of about 800 nm. The length (in the direction parallel to the bit line 224a and the like) and the width (in the direction parallel to the word line 214a and the like) of the storage node electrode 234 are each equal to 0.
The distance is about 9 μm and about 0.3 μm, and the interval between the storage node electrodes 234 is about 0.3 μm.

Also in the second embodiment, unlike the conventional DRAM subjected to the HSG processing shown in FIGS. 9 to 12, all the storage node electrodes 234 provided on the cell array region 231 are provided. Top and side surfaces are HSG-Si
Covered by The upper surface and the side surface of the storage node electrode 234 and the upper surface of the interlayer insulating film 231 between the storage node electrode 234 are directly covered with the capacitor insulating film 236. At least the storage node electrode 23
The film thickness of the capacitive insulating film 236 at the portion covering the upper surface and the side surface of 4 is about 5 nm in terms of a silicon oxide film.
For example, a cell plate electrode 237 made of an N-type polycrystalline silicon film having a thickness of about 250 nm to 200 nm covers the storage node electrode 234 via the capacitor insulating film 236.

The reason why the side surfaces and the top surfaces of all the storage node electrodes 234 are covered with HSG-Si in the present embodiment of the second embodiment is the same as that of the above-described embodiment of the first embodiment. On the other hand, the method strongly depends on the manufacturing method, and it is difficult to explain the structure.

FIG. 7 is a schematic cross-sectional view of the DRAM manufacturing process and is a schematic cross-sectional view taken along the line AA of FIG. 5, and FIG. 7 is a schematic cross-sectional view of the DRAM manufacturing process and is a schematic cross-sectional view taken along the line BB of FIG. Referring to FIG. 8 and FIGS. 5 and 6 together, the DRAM according to the example of the second embodiment is described.
Is formed as follows.

First, a cell array region 251 and a device isolation region of the peripheral circuit region 252 on the surface of the P-type silicon substrate 201 have a thickness of about 280 nm (for example, LOCOS).
Field oxide film 211 is formed, and an active region 202 (peripheral circuit region 252) is formed in the cell array region 251.
Are not shown in the drawing). A gate oxide film 212 having a thickness of about 8 nm is formed on the active region 202 of the cell array region 251 by thermal oxidation.
Is formed. An N-type polycrystalline silicon film (having a high concentration) having a thickness of about 100 nm (not explicitly shown) is formed on the entire surface. The method of forming this N-type polycrystalline silicon film is based on the LPCV
A method of thermally diffusing phosphorus into a non-doped polycrystalline silicon film by D, or LP using monosilane (SiH ₄ ) as a source gas and phosphine (PH ₃ ) as an impurity gas.
A method may be used in which an N-type amorphous silicon film is formed by CVD and this is heat-treated. Further, a tungsten silicide film having a thickness of about 100 nm is formed by, for example, sputtering. The laminated conductor film composed of the tungsten silicide film and the N-type polycrystalline silicon film is sequentially patterned by anisotropic etching to form a word line 214 composed of a tungsten polycide film having a thickness of about 200 nm.
a, 214b, 214c, 214d, 214e, 214
f (and a gate electrode of a peripheral circuit, not shown) are formed (FIGS. 5 and 6).

40 keV, 2 × 10 ^{13 using} these word line 214a and field oxide film 211 as a mask.
N-type source / drain regions 215A, 215B and the like are formed in the active region 202 and the like by ion implantation of phosphorus of about cm ⁻² or the like. The N-type source / drain regions 215
A, 215B and the like have a low concentration at this stage, but after forming a bit contact hole or a node contact hole,
Contact ion implantation of phosphorus of about 0 keV and about 5 × 10 ¹⁴ cm ⁻² is performed, and these N-type source / drain regions 215A, 215B and the like finally have a low-concentration N-type region and a medium-concentration N-type region. Becomes an N-type diffusion layer. Although not shown, the N-type source / drain regions (and the P-type source / drain regions) constituting the MOS transistor of the peripheral circuit are N-type source / drain regions 215A, 215A.
This is performed before and after the formation of 15B [FIGS. 5 and 6].

Next, an HTO film (not explicitly shown),
A BPSG film (not explicitly shown), a flattening process, and the like are performed to form N-type source / drain regions 215A and 215B.
Thus, a first interlayer insulating film 221 having a thickness of about 500 nm immediately above is formed. Interlayer insulating film 221, gate oxide film 2
12 are sequentially anisotropically etched to form bit contact holes 222 reaching the N-type source / drain regions 215A and the like.
Are formed. LPCVD at about 100 Pa using tungsten hexafluoride (WF ₆ ) and dichlorosilane (SiH ₂ Cl ₂ ) as a raw material gas and argon (Ar) as a carrier gas is performed at about 600 ° C. to form a film on the entire surface. A tungsten silicide film (not explicitly shown) having a thickness of about 150 nm is formed. This tungsten silicide film is patterned by anisotropic etching, and bit lines 224a and 224a, which are directly connected to N-type source / drain regions 215A via bit contact holes 222.
24b, 224c, 224d and the like are formed (FIGS. 5 and 6).

Subsequently, a silicon oxide-based insulating film is formed and planarized on the entire surface, and a second film having a thickness of about 400 nm is formed.
Is formed. Interlayer insulating film 231,
The interlayer insulating film 221 and the gate oxide film 212 are sequentially anisotropically etched, and a node contact hole 232 reaching the N-type source / drain region 215B is formed in the cell array region 251. For example, by forming an N-type polycrystalline silicon film by LPCVD, the node contact hole 2 is formed.
A contact plug 233 filling 329 is formed. 10 ^-3 Pa to 20 ^-4 P using monosilane (SiH ₄ ) as a source gas and phosphine (PH ₃ ) as an impurity gas
LPCVD at about 510 ° C. is performed, for example, at about 510 ° C., and the entire surface has a thickness of about 800 nm and 1 × 10 ¹⁹
N having an impurity concentration of about cm ^{−3 to} 2 × 10 ²⁰ cm ⁻³
A type amorphous silicon film (not explicitly shown) is formed.

Next, by using a photoresist film pattern (not shown) as a mask, the N-type amorphous layer is formed by anisotropic etching using boron trichloride (BCl ₃ ) and chlorine (Cl ₂ ) as an etching gas. The amorphous silicon film is patterned, and N-type amorphous silicon film patterns 244 and 24 are formed on the cell array region 251 and the peripheral circuit region 252, respectively.
5 are formed. N-type amorphous silicon film pattern 245
Has the same shape as the N-type amorphous silicon film pattern 145 in the example of the first embodiment, and has a required width of, for example, about 5 μm. N-type amorphous silicon film pattern 244 and N-type amorphous silicon film pattern 245 located at the outermost periphery of cell array region 252
Is a predetermined distance of, for example, about 0.6 μm (FIGS. 7A and 8A).

The required width of the N-type amorphous silicon film pattern 245 is at least 1.0 μm, like the predetermined width of the N-type amorphous silicon film pattern 145. Since the predetermined width of the N-type amorphous silicon film pattern 145 corresponds to the width of the dummy region 153, it is not preferable to set the predetermined width to be large. On the other hand, the N-type amorphous silicon film pattern 24
Since 5 is finally removed, the required width of the N-type amorphous silicon film pattern 245 can be set wider. N-type amorphous silicon film patterns 245, 244
Has the following restrictions. Due to a request from a photolithography process related to the formation of the cell plate electrode, the predetermined interval is twice the thickness (for example, 200 nm) of the conductor film forming the cell plate electrode and the alignment margin (0.25 μm) in photolithography.
It is preferable that the sum be equal to or more than twice (eg, about 0.5 μm) twice as large as 0.05 μm in the m design rule. (Relationship between the exposed width of the upper surface of the interlayer insulating film 231 at the portion adjacent to the N-type amorphous silicon film pattern 244 provided on the outermost periphery of the cell array region 251 and the HSG-Si failure) performed by the present inventors According to the examination result, when the exposed width of the upper surface of the interlayer insulating film 231 becomes about 2.2 μm to 2.5 μm, the HSG
In the conversion process, the N-type amorphous silicon film pattern 244 located at the outermost periphery of
-An N-type polycrystalline silicon film pattern with poor Si formation is obtained.
From this examination result, it is preferable that the predetermined interval is 2.0 μm or less.

Next, the N-type amorphous silicon film pattern 24
The natural oxide film on the side and top surfaces of 4,245 is removed,
HSG processing is performed. Accordingly, the N-type amorphous silicon film pattern 244 is converted into a storage node electrode 234, and the N-type amorphous silicon film pattern 245 is converted into an N-type polycrystalline silicon film pattern 246. Due to the presence of the N-type amorphous silicon film pattern 245 (functioning as a dummy pattern) having the required width and the predetermined interval, the storage node electrode 234 obtained by the HSG processing has an HSG-Si formation defect. Does not occur [FIGS. 7 (b) and 8 (b)].

Thereafter, a capacitance insulating film (not explicitly shown) is formed on the entire surface. Capacitive insulating films at portions covering the upper surface and side surfaces of storage node electrode 234 and N-type polycrystalline silicon film pattern 246 have an ONO structure, and the equivalent thickness of the capacitive insulating film at these portions is 5n.
m. An N-type polycrystalline silicon film (having a high concentration) having a thickness of about 150 nm to 200 nm is formed on the entire surface. Using the photoresist film pattern 247 covering the cell array region 251 as a mask, the N-type polycrystalline silicon film and the capacitor insulating film are patterned by isotropic etching using sulfur hexafluoride (SF ₆ ) as an etching gas. A cell plate electrode 247 and a capacitance insulating film 236 are formed (FIGS. 7C and 8C). Further, the N-type polysilicon film pattern 24 is isotropically etched with sulfur hexafluoride (SF ₆ ) using the photoresist film pattern 247.
6 is removed to form the DRAM according to the example of the second embodiment (FIGS. 5 and 6).

In the present embodiment of the second embodiment, unlike the above-described embodiment of the first embodiment, as a result, no dummy region is provided (that is, the effective area of the cell array region is not provided). HSG-Si without large area increase)
Incompatibility can be avoided.

[0064]

As described above, according to the first aspect of the method of manufacturing a semiconductor memory device of the present invention, a dummy cell is provided in a cell array region to form a DRAM with HSG processing. Compared with the method of increasing the effective area, the dummy area is provided around the cell array area and the dummy electrode is provided on the dummy area, so that the increase in the effective area of the cell array area is reduced and the storage node electrode is reduced. It becomes easy to avoid HSG-Si formation failure.

Further, according to the second aspect of the method of manufacturing the semiconductor memory device of the present invention, the dummy pattern is formed on the peripheral circuit region at the stage of forming the storage node electrode without providing the dummy region. By providing a silicon film pattern and removing the N-type amorphous silicon film pattern at the stage of forming the cell plate electrode, the HSG-Si of the storage node electrode can be obtained without any effect on the effective area of the cell array region. It becomes easy to avoid the formation failure.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of an example of the first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of the example of the first embodiment, taken along line AA and BB in FIG. 1;

FIG. 3 is a schematic cross-sectional view of the manufacturing process of the example of the first embodiment, and is a schematic cross-sectional view of the manufacturing process along line AA in FIG. 1;

FIG. 4 is a schematic cross-sectional view of the manufacturing process of the one example of the first embodiment, and is a schematic cross-sectional view of the manufacturing process along line BB in FIG. 1;

FIG. 5 is a schematic plan view of an example of the second embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view of the example of the second embodiment, taken along line AA and BB in FIG. 5;

FIG. 7 is a schematic cross-sectional view of the manufacturing process of the example of the second embodiment, and is a schematic cross-sectional view of the manufacturing process along line AA in FIG. 5;

8 is a schematic cross-sectional view of the manufacturing process of the example of the second embodiment, and is a schematic cross-sectional view of the manufacturing process taken along line BB in FIG. 5;

FIG. 9 is a schematic plan view of a conventional DRAM having a memory cell made of HSG-Si.

10 is a schematic cross-sectional view of the conventional DRAM, and is a schematic cross-sectional view taken along line AA and line BB in FIG.

11 is a schematic cross-sectional view of a manufacturing process of the conventional DRAM, which is a schematic cross-sectional view of the manufacturing process along line AA in FIG. 9;

FIG. 12 is a schematic cross-sectional view of a manufacturing process of the conventional DRAM, which is a schematic cross-sectional view of the manufacturing process taken along line BB in FIG. 9;

[Explanation of symbols]

101, 201, 301 P-type silicon substrate 102, 103, 202, 302 Active region 111, 211, 311 Field oxide film 112, 212, 312 Gate oxide film 114a-114f, 214a-214f, 314a-
314f word line 115A, 115B, 215A, 215B, 315A,
315B N-type source / drain region 115C N-type diffusion layer 121,131,221,231,321,331
Interlayer insulating films 122, 222, 322 Bit contact holes 124a to 124d, 224a to 224d, 324a to
324d Bit line 132, 232, 332 Node contact hole 132C Contact hole 133, 233, 333 Contact plug 134, 234, 334 Storage node electrode 135 Dummy electrode 136, 236, 336 Capacity insulating film 137, 237, 337 Cell plate electrode 143, 343 N-type amorphous silicon film 144, 145, 244, 245, 344 N-type amorphous silicon film pattern 151, 251, 352 Cell array region 152, 252, 352 Peripheral circuit region 153 Dummy region 246 N-type polycrystalline silicon film Pattern 247 Photoresist film pattern

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-8-181290 (JP, A) JP-A-5-315543 (JP, A) JP-A-6-151711 (JP, A) JP-A-7-151 335842 (JP, A) JP-A-8-264732 (JP, A) JP-A-7-202023 (JP, A) JP-A-9-8250 (JP, A) International publication 96/12301 (WO, A1) ( 58) Investigated field (Int.Cl. ⁷ , DB name) H01L 27/108 H01L 21/822 H01L 21/8242 H01L 27/04

Claims (5)

(57) [Claims] 1. A dummy region is provided on a surface of a P-type silicon substrate surrounding a cell array region provided on a surface of the P-type silicon substrate, and a surface of the P-type silicon substrate around the dummy region is provided. The P provided with a peripheral circuit area
A field oxide film formed in an element isolation region on the surface of the p-type silicon substrate, and a plurality of first active regions provided regularly in the cell array region on the surface of the p-type silicon substrate; Partitioning a portion of the peripheral circuit region and a second active region provided in a required portion of the dummy region excluding a portion of the dummy region sandwiched between the cell array regions; And forming a gate oxide film in the second active region, forming a gate electrode serving also as a word line on the first active region via the gate oxide film, and forming a gate electrode in the first and second active regions. Are N-type source / drain regions and N
Forming a type diffusion layer; forming a first interlayer insulating film covering the surface of the P-type silicon substrate; and penetrating the first interlayer insulating film and the gate oxide film to form the N-type source / drain. Forming a bit contact hole reaching one of the regions, extending on a surface of the first interlayer insulating film in a direction orthogonal to the word line, and forming the N-type source / drain region through the bit contact hole; Forming a bit line connected to one of the first and second layers; forming a second interlayer insulating film covering the first interlayer insulating film; respectively forming the second interlayer insulating film and the first interlayer insulating film; Forming a node contact hole and a contact hole penetrating through the gate oxide film and reaching the other of the N-type source / drain regions and the N-type diffusion layer; and forming an N-type amorphous silicon film on the entire surface. Put the amorphous silicon film Forming a first amorphous silicon film pattern connected to the other of the N-type source / drain regions through the node contact hole in the cell array region, and forming the first amorphous silicon film pattern in the dummy region. Forming a second amorphous silicon film pattern having a predetermined width at a predetermined distance from the amorphous silicon film pattern and surrounding the cell array region; The first and second amorphous silicon film patterns are exposed to a monosilane (SiH ₄ ) molecular flow or a disilane (Si ₂ H ₆ ) molecular flow under a high temperature and an ultra-high vacuum. The upper and side surfaces of the amorphous silicon film pattern are covered with hemispherical silicon crystal grains, and the first and second amorphous silicon film patterns are respectively replaced by first and second polycrystalline silicon film patterns. Forming a storage node electrode and a dummy electrode made of the first and second polycrystalline silicon film patterns by performing a process of converting into HSG (HSG conversion process); Forming a capacitor insulating film covering the side surface, forming a conductor film on the entire surface, patterning the conductor film, and forming a cell plate electrode covering the storage node electrode and the dummy electrode via the capacitor insulating film; And a method of manufacturing a semiconductor memory device. 2. The method according to claim 1, wherein the N-type diffusion layer is provided only on the side of the dummy region where the bit line extends. 3. The method according to claim 1, wherein the predetermined width is at least 1.0 μm. 4. A field oxide is formed on an element isolation region on a surface of the P-type silicon substrate provided with a peripheral circuit region on a surface of the P-type silicon substrate around a cell array region provided on the surface of the P-type silicon substrate. Forming a film to partition a plurality of active regions provided regularly in the cell array region; forming a gate oxide film in the active region; and forming the active region through the gate oxide film. Forming a gate electrode also serving as a word line thereon and forming N-type source / drain regions in the active region; forming a first interlayer insulating film covering a surface of the P-type silicon substrate; A bit contact hole penetrating through the first interlayer insulating film and the gate oxide film and reaching one of the N-type source / drain regions is formed, and is formed on a surface of the first interlayer insulating film at right angles to the word line. Extend in the direction Forming a bit line connected to one of the N-type source / drain regions through the bit contact hole; forming a second interlayer insulating film covering the first interlayer insulating film; Forming a node contact hole penetrating through the second interlayer insulating film, the first interlayer insulating film and the gate oxide film and reaching the other of the N-type source / drain regions; A first amorphous silicon film pattern connected to the other of the N-type source / drain regions through the node contact hole in the cell array region by forming a porous silicon film and patterning the amorphous silicon film; Forming a second amorphous silicon film pattern having a form surrounding the cell array region at a position spaced apart from the first amorphous silicon film pattern by a predetermined distance; Converting the first and second amorphous silicon film patterns into a storage node electrode and an N-type polycrystalline silicon film pattern, respectively, by performing an SG process; and at least upper surfaces of the storage node electrode and the polycrystalline silicon film pattern Forming a capacitor insulating film covering the side surfaces, forming a conductor film on the entire surface, etching the conductor film using a photoresist film pattern covering the cell array region as a mask, and etching the conductor film via the capacitor insulating film; Forming a cell plate electrode covering the storage node electrode;
And etching the capacitive insulating film and the polycrystalline silicon film pattern sequentially using the photoresist film pattern as a mask. 5. The method according to claim 1, wherein the predetermined interval is two times the thickness of the conductor film.
Is greater than the sum of the double and the alignment margin twice,
5. The method according to claim 4, wherein the thickness is 2.0 [mu] m or less.