JP3156771B2 - Method and circuit for slew rate control including through current prevention - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a high-speed LSI CM
By providing an output transistor on / off timing adjustment circuit having a function of preventing a through current in a front stage of a totem pole type output circuit of an input / output buffer circuit in an OS, biCOMS circuit, a slew rate of an output waveform of the buffer circuit is provided. The present invention relates to a method and a circuit for performing control and preventing a through current from increasing accordingly.

[0002]

2. Description of the Related Art In the prior art of the present invention, generally, in order to control slew rate only, transistors in an output stage are connected in parallel as shown in FIG. 3, and the transistors are operated one by one. It is known that the driving current gradually increases if it goes down, and it is possible to dull the edge of the output waveform.

However, this means that the pull-up transistor (pull-down transistor) in the output stage is turned on and the pull-down transistor (pull-up transistor) on the opposite side is gradually turned off at the same time.
Naturally, the time during which the transistors on the pull-up side and the pull-down side are ON at the same time increases, and there is a drawback that the through current necessarily increases.

[0004] In this case, although the reflection noise can be reduced by making the waveform dull, there is a problem that an increase in the through current causes an increase in ground noise and radiation noise, and also an increase in power consumption. Was.

Some proposals have been made for circuit configurations for reducing the through current. For example, an output circuit configuration disclosed in Japanese Patent Application Laid-Open No. 8-84057 is one of them. FIG. 4 (a) shows a configuration diagram thereof, and FIG. 4 (b) shows an operation of the configuration. An output circuit including a P-type MOS transistor 401 connected to the power supply Vcc side, an N-type MOS transistor 402 connected to the ground G side, and an output terminal 431 connected to the drain of the transistor 401 and the transistor 402. In the device, the rise of the gate of the transistor 402 is delayed with respect to the rise of the gate of the transistor 401, and the fall of the gate of the transistor 402 is advanced with respect to the fall of the gate of the transistor 401.
2 simultaneously suppresses a through current from the power supply Vcc to the ground G.

On the other hand, the present invention provides a slew rate controller.
A roll timing adjustment circuit is provided to control the operation of the pull-up and pull-down transistors,
Since the pull-down transistor is rapidly turned off, no through current flows and the pull-up transistor can be gradually turned on, the slew rate can be controlled, and the structure and effect of the prior art are achieved. In terms of

[0007]

The slew rate control is used to reduce reflection noise, ground noise, and normal mode radiation noise by slowing the rise / fall of a digital circuit waveform. I have.

The dulling of the waveform in accordance with the operating frequency as described above is generally performed as a countermeasure against reflection noise. In recent years, however, a slew rate control has been used as a countermeasure against radiation noise that increases as the clock frequency increases. You have to do more.

Research has revealed that while the technology of LSIs used in computers is changing to CMOS, a radiated noise may be caused by a through current flowing when the CMOS circuit operates. Was.

Particularly, in an output buffer circuit, when an input signal is inverted, complementary connected transistors may be momentarily turned on at the same time. Therefore, a through current flows from the power supply side to the ground side through this transistor array. . This through current causes an increase in power consumption.

An object of the present invention is to provide a slew rate control circuit for realizing a total optimal noise countermeasure including radiation noise by controlling a slew rate while suppressing a through current. .

[0012]

According to the present invention, there is provided a slew rate control circuit including a shoot-through current prevention circuit, comprising: an output-stage pull-up transistor connected to a power supply; A timing adjustment circuit A for sending an ON / OFF timing signal for holding down, an output pull-down transistor connected to the ground, and a timing for sending an ON / OFF timing signal for controlling a slew rate of an output waveform to the transistor and holding down a through current. It has an adjustment circuit B and an output terminal derived from a connection point between the pull-up transistor and the pull-down transistor.

The timing adjusting circuit A includes an N-channel transistor and a resistor and a capacitor forming a time constant circuit, and the timing adjusting circuit B includes a P-channel transistor and a resistor and a capacitor forming a time constant circuit. 2 is one embodiment of the invention.

Further, the present invention includes a circuit in which the resistance of the timing adjustment circuit is a gate resistance using a transistor.

It is also conceivable that the capacitor of the timing adjustment circuit has a thicker signal pattern to serve as a parasitic capacitance of the signal line.

In the timing adjustment circuit A, an N-channel transistor operated by an input signal is connected between a power supply and the gate of an output stage pull-up transistor, and is connected between a connection line up to the gate of the output stage pull-up transistor and ground. , A resistor and a capacitor are connected. In the timing adjustment circuit B, a P-channel transistor operated by an input signal is connected between the ground and the gate of the output stage pull-down transistor, and a resistor is connected between the connection line and the power supply. Is connected between the connection line and the ground, which is also a preferred embodiment of the present invention.

In the method of slew rate control including through current prevention according to the present invention, the step (201) in which an input signal changes from a low level to a high level, and the step of starting operation of the transistor of the timing adjustment circuit A to ON ( 202), a step of starting the operation of the transistor of the timing adjustment circuit B to OFF (204), and a step of quickly turning the gate input signal of the pull-up transistor to the high level and turning off the pull-up transistor earlier than the pull-down transistor ON (202). 203), the gate input signal of the pull-down transistor slowly goes to the high level and the pull-down transistor slowly turns on (205), and the input signal changes from the high level to the low level (206). Tiger of adjustment circuit A Step (207) of starting operation of the transistor to OFF, step (209) of starting operation of the transistor of the timing adjustment circuit B to ON (209), and the gate input signal of the pull-up transistor becomes low level at a slow speed. In the step (208) of slowly turning on, the gate input signal of the pull-down transistor quickly becomes low level, and the pull-down transistor is turned off earlier than the pull-up transistor is turned on.
(210).

Normal CMOS (Complementary Metal Ox)
ide Semiconductor) In digital circuits, P-chCM
It comprises only an OS transistor 401 and an N-ch CMOS transistor 402 . On the other hand, in the present invention, output transistor ON / OFF timing adjustment circuits A and B are provided at the gates of the CMOS transistors 101 and 102 in the output stage.

The adjustment circuits A and B control the slew rate of the output waveform by easing the ON timing of the output stage transistor, and maintain the slew rate adjustment function by not changing the OFF timing. In this state, an operation of suppressing the through current flowing in the output transition state is performed. Therefore, after adjusting the slew rate,
Normally, the increase of the through current accompanying it can be suppressed low, so that both low noise and low power consumption can be achieved.

A description will be given with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of a circuit to which a method of slew rate control including through current prevention according to the present invention is applied, and a timing operation diagram thereof.

Here, a CMOS inverter circuit having a slew rate control circuit including a through current prevention function of the present invention is shown. By supplying the signal from the slew rate control circuit to the output stage transistor, if the transistor is turned off, the OF
F, and when it is turned on, it is gradually turned on (the transistor becomes O
The output resistance and the drain-source resistance at the time of N gradually decrease. ). This makes it possible to adjust the degree of dullness of the edge of the output waveform and the slew rate. The ON / OFF state of the pull-up and pull-down transistors
Generation of a through current can be prevented by adjusting the OFF timing so that the other transistor is gradually turned on after one of the transistors is turned off.
The through rate control circuit including the through current prevention function of FIG. 1 is configured as follows. That is, it is composed of a timing adjustment circuit A for sending an ON / OFF timing signal to the output pull-up transistor and a timing adjustment circuit B for sending an ON / OFF timing signal to the output-stage pull-down transistor.

Each of the timing adjusting circuits A and B includes a transistor, a resistor, and a capacitor. In the timing adjustment circuit A, an N-
The channel transistor is connected between the power supply and the gate of the output stage pull-up transistor.
A resistor and a capacitor are connected between the connection line to the gate of the transistor and GND. In the timing adjustment circuit B, the P-ch transistor operated by the input signal is GN
A resistor is connected between D and the gate of the output stage pull-down transistor, a resistor is connected between the connection line and the power supply, and a capacitor is connected between the connection line and GND.

[0023] Hereinafter will be described with reference to the timing diagram shown in FIG. 1 (b) Operation of the slew rate control circuit including a through current preventing function.

First, at time T0, when the input signal changes from low level to high level (step 20).
1), the transistors of the timing adjustment circuits A and B start operating at time T1 (steps 202 and 20).
4). In the timing adjustment circuit A, the transistor
As a result, a current rapidly flows through a resistor and a capacitor connected to the source of the transistor, and the signal input to the gate of the pull-up transistor in the output stage quickly becomes a high level.

On the other hand, in the timing adjustment circuit B, when a transistor is turned off, a CR time constant circuit is formed by a resistor and a capacitor connected to the drain of the transistor, and a high level is obtained by a curve characterized by the time constant. Until the time T2 slowly rises.

The output stage transistor receiving the signal from these timing adjustment circuits has a pull-up side which is quickly turned on by the signal which rapidly goes high as described above.
FF (step 203), and the pull-down side is slowly turned on by a signal that slowly goes high.
N (step 205).

Pull-up side transistor turns off rapidly
As a result, a through current does not flow, and the slew rate can be controlled by slowly turning on the pull-down transistor.

Next, suppose that the input signal changes from High level to Low level at time T3 (step 2).
06), the transistors of the timing adjustment circuits A and B start operating at time T4 (steps 207 and 2).
09). In the timing adjustment circuit A, the transistor is O
By performing FF, a CR time constant circuit is formed by the resistor and the capacitor connected to the source of the transistor, and the curve is characterized by the time constant and is low.
It slowly descends to the level at time T5.

On the other hand, in the timing adjustment circuit B, when a transistor is turned on, a current rapidly flows through a resistor and a capacitor connected to the source of the transistor.
The signal input to the gate of the output stage pull-down transistor quickly goes to a low level.

The output stage transistor receiving the signal from these timing adjustment circuits gradually turns on the pull-up side by the signal which slowly goes low as described above, and rapidly goes high level on the pull-down side. It is rapidly turned off by a signal (step 20).
8, 210).

As a result, since the pull-down transistor is rapidly turned off, a through current does not flow, the pull-up transistor can be gradually turned on, and the slew rate control is successful .

[0032]

As described above, in the slew rate controller circuit including the through current prevention function of the present invention, the timing adjustment circuit is designed so that the pull-up transistor and the pull-down transistor of the output stage are not simultaneously turned on. Is provided so that one transistor is turned off and then the other transistor starts to be turned on, so that a through current is very unlikely to occur.

Therefore, the through current is very small and the flowing time is very short, so that ground noise and radiation noise can be reduced, and power consumption can be reduced.

Further, the slew rate can be controlled by processing the input signal by the timing adjustment circuit so that the output stage transistor is gradually turned on when the output stage transistor is turned on.

Generally, when the slew rate control is performed, the through current increases.
There is an effect that a slew rate control can be performed and a through current can be suppressed to a low level, which has been impossible so far.

[Brief description of the drawings]

FIG. 1A is a slew rate control circuit including a through current prevention function according to the present invention. FIG. 3B is an operation timing chart of the slew rate control circuit including the through current prevention function of the present invention.

FIG. 2 is a flowchart of a first embodiment of a slew rate control including a through current prevention function of the present invention.

FIG. 3 is an explanatory diagram of a slew rate control.

FIG. 4A is a configuration diagram showing one embodiment of a conventional technique. FIG. 5B is an operation diagram according to the configuration shown in FIG.

DESCRIPTION OF SYMBOLS 101 output stage pull-up transistor 102 output stage pull-down transistor 103 output terminal 104 power supply terminal 105 timing adjustment circuit A 106 timing adjustment circuit B 107 input terminal 301 pull-up transistor 302 pull-down transistor 303 output terminal 304 Power supply terminal 307 Input terminal 401 P-type MOS transistor 402 N-type MOS transistor 431 Output terminal 434 Input terminal (a) 435 Input terminal (b)

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03K 17/00-17/70

Claims (4)

(57) [Claims] 1. High-speed LSI CMOS, bi-CMOS
In a totem-pole type output circuit of an input / output buffer circuit in a circuit, an output stage pull-up transistor connected to a power supply and an ON / OFF control circuit which controls a slew rate, which is an inclination angle of an output waveform, to reduce a through current. A timing adjustment circuit A for sending an OFF timing signal, an output stage pull-down transistor connected to the ground, and a timing adjustment circuit B for sending an ON / OFF timing signal for controlling a slew rate of an output waveform to suppress a through current to the transistor A slew rate control circuit including a through current prevention function, comprising: an output terminal derived from a connection point between the pull-up transistor and the pull-down transistor. 2. The timing adjustment circuit A has a resistor.
2. The slew rate control circuit having a through current prevention function according to claim 1, further comprising an N-channel transistor, and wherein the timing adjustment circuit B includes a P-channel transistor having a resistance . Wherein said timing adjustment circuit, the slew rate control circuit including a through current preventing function according to claim 2, wherein including those with parasitic capacitance of the signal line by thickening the signal pattern. 4. A pull-up transistor (10 ) in an output stage.
1) and the pull-down transistor (102) in the output stage
Timing adjustment circuit A (105) and timing
The control circuit B (106) controls the waveform inclination angle.
-Under the rate control, pull-down
Transistor (102) is a timing adjustment circuit B (106)
I / O buffer times subject to slew rate control
A method of slew rate control including prevention of a through current in a path, wherein a step (202) in which an input signal changes from a low level to a high level causes a transistor of the timing adjustment circuit A to start operating to ON (202). ), And the step (204) in which the transistor of the timing adjustment circuit B starts to turn off, and the gate input signal of the pull-up transistor quickly becomes high level, and the pull-up transistor is turned off earlier than the pull-down transistor is turned on. Step (2)
03), the gate input signal of the pull-down transistor slowly goes to the high level, the pull-down transistor slowly turns on (205), and the input signal changes from the high level to the low level (206) . Accordingly , a step (207) in which the transistor of the timing adjustment circuit A starts to operate OFF, a step (209) in which the transistor of the timing adjustment circuit B starts operation ON (209), and the gate input signal of the pull-up transistor is slow. , The pull-up transistor is slowly turned on (208), and the gate input signal of the pull-down transistor is quickly turned to low, and the pull-down transistor is turned off earlier than the pull-up transistor ON (21).
0) and a method of slew rate control including through current prevention.