JP3155816B2 - Nonvolatile storage element, nonvolatile storage device using the same, and method of driving nonvolatile storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory element, a nonvolatile memory device using the same, and a method of driving the nonvolatile memory device.

[0002]

2. Description of the Related Art Conventionally, as a nonvolatile memory device using a ferroelectric (hereinafter referred to as a nonvolatile memory), one ferroelectric capacitor 1 and one switching MOS as shown in FIG. Field-effect transistor (hereinafter referred to as MOSFET (metal oxide semiconductor field e
2) as one non-volatile memory element (hereinafter, referred to as a memory cell), and the memory cells are arranged in an array.
SYSTEM DESIGN "1988 MAY PP117-123 S. BAKE and JP-A-63-201998).

In the above-mentioned nonvolatile memory, since destructive reading is performed instead of non-destructive reading, the polarization inversion of the ferroelectric material is large, the fatigue of the ferroelectric thin film is increased, and the number of rewritable times is reduced. In addition, a charge amount (about 30 fF) equivalent to that of a DRAM is required for sensing, and a relatively large residual polarization is required. For this reason, the selection range of the ferroelectric material is reduced, and the suitability for miniaturization is limited, so that it is difficult to manufacture a memory.

To cope with this, a field effect transistor (hereinafter referred to as M) having a ferroelectric gate film in a memory cell is used.
When an FS (metal ferroelectric semiconductor) FET is used, nondestructive reading becomes possible, and the number of rewritable times is improved as compared with the nonvolatile memory of FIG. In addition, since what is required for sensing is not the amount of charge due to remanent polarization but the charge density, the MFSFET can be miniaturized. Furthermore, the remanent polarization required for sensing is
The memory can be relatively small, 1 μC / cm ² or less, and the material can be selected in a wide range, so that the memory can be easily manufactured.

FIG. 8 is a sectional view of an MFSFET. In the figure
Where A is a P-type silicon substrate and SD is an N-type source.
A drain diffusion layer, 3 is a conductive thin film serving as a gate electrode, 4
Is a ferroelectric gate film, 5 is an interlayer insulating film, 6 is a source
A rain electrode, comprising a conductive thin film 3 and a ferroelectric gate film;
4 have an MFS structure. As ferroelectric material
Is mainly PZT, PLZT, PbTiO_Three, BaTiO
_ThreeABO such as_ThreePerovs of type (A, B: metal elements)
Kite structure is used, but shows ferroelectricity
If it is a material, that is not the case. Examples of other materials include
For example, BaMgF _Four, NaCaF_Three, K_TwoZnCl_Fouretc
A halogen compound, Zn_1-XCd_xTe, GeTe, S
n_TwoP_TwoS₆And the like. Was
However, the conductive thin film 3 and the ferroelectric gate film 4 or
Between the electrical gate film 4 and the source-drain diffusion layer SD
In addition, it is possible to insert a buffer layer.

The ferroelectric material of the MFSFET has a PE hysteresis characteristic as shown in FIG. In the figure, a voltage that gives an electric field E _sat or more to the ferroelectric is referred to as V
_max (> 0). When a voltage of + V _max is applied to the gate, it is polarized to the state of A and a channel is formed. Thereafter, even if the gate voltage is set to 0, the state becomes B, polarization remains, and the channel remains formed. Conversely, when a voltage of -V _max (or a voltage of + V _max is applied to the substrate) is applied to the gate, polarization is performed to the state of C, and when the voltage is set to 0, D is applied.
State. No channel is formed in this process.

FIG. 10 shows an example of a nonvolatile memory using an MFSFET. FIG. 10 is an equivalent circuit diagram of a nonvolatile memory using an MFSFET. This nonvolatile memory includes MFSFETs 10A, 10B and 10 as shown in FIG.
MO for switching on the source and drain of C and 10D
SFETs 11A, 11B, 11C, 11D and 12
A, 12B, 12C, and 12D are connected in series, and memory cells 13A, 13B, 13C, and 13D are arranged in a matrix with a predetermined capacity (four bits in the figure). In the following description, MF
When the SFETs 10A, 10B, 10C, and 10 are collectively referred to as “MFSFET10”, MOSFETs 11A and 11
B, 11C and 11D are collectively referred to as "MOSFET1".
1 "and MOSFETs 12A, 12B, 12C and 12D are collectively referred to as" MOSFET 12 ".

Each MFSFET 10 and MOSFET 1
Gate lines GL1-1 and GL1
2-1, GL3-1 and GL1-2, GL2-2, G
L3-2 are connected respectively. Also, each MOSF
Bit lines BL1 and BL2 are connected to the drain of ET11.
Are connected respectively. Furthermore, each MOSFET 1
The two sources are each grounded to the ground.

In the nonvolatile memory, when writing information (data) to the memory cell 13A, a high voltage H is applied to the gate lines GL1-1 and GL2-1.
And a low voltage L is applied to the gate line GL3-1 and a low voltage L is applied to the bit line BL1. The gate lines GL1-2, G
A low voltage L is applied to L2-2 and GL3-2, and a high voltage H is applied to the bit line BL2. Then, the MFSFET1 in the memory cell 13A
0A ferroelectric gate film is in a predetermined electric polarization state,
Data can be written.

[0010]

In recent years, with the development of the semiconductor industry, integration of nonvolatile memories has been required.
In order to meet this demand, it is conceivable to improve the degree of integration of the memory cell array circuit. However, the memory cell array circuit shown in FIG.
Because of the one-cell structure, it could not contribute much to the integration of the nonvolatile memory.

Therefore, a nonvolatile memory having a one-transistor / one-cell structure as shown in FIG. 11 has been proposed. FIG. 11 is an equivalent circuit diagram of a nonvolatile memory having a one-transistor / one-cell structure. This nonvolatile memory includes MFSFETs 20A, 20B and 20 as shown in FIG.
Memory cell 21 composed of C, 20D, 20E, 20F
A, 21B, 21C, 21D, 21E, 21F are arranged in a matrix with a predetermined capacity (6 bits in the figure). In the following description, MFS
FETs 20A, 20B, 20C, 20D, 20E, 20
F is generally referred to as "MFSFET 20".

The source of each MFSFET 20 is connected to a word line WL1, WL2, respectively. The source and drain of the adjacent MFSFET 20 are connected for each word line, and the source-drain connection midpoint and the MFSFETs 20A, 20C, 20B at both ends are connected.
D, 20F source and drain, bit line BL
1, BL2, BL3 and BL4 are connected respectively.

In the nonvolatile memory, when writing data to the memory cell 21D, a high voltage H is applied to the word line WL2 and a write voltage L is applied to the bit lines BL1 and BL2. In addition,
The low voltage L is applied to the word line WL1, the write inhibit voltage H is applied to the bit line BL3, and the bit line BL4 is open.

Then, the MFS in the memory cell 21D
A potential difference occurs between the gate and the drain of the FET 20D, and M
Since the ferroelectric gate film of the FSFET 20D is polarized,
Data can be written. On the other hand, in the memory cell 21E where writing is not performed, the MFSFET 20E
No potential difference occurs between the gate and drain of the MFSFET
Since the ferroelectric gate film of 20E is not polarized, no data is written.

However, in the nonvolatile memory shown in FIG. 11, when writing data to the memory cell 21D, as described above, the memory cell 21B sharing the bit line BL1 with the memory cell 21D is used. MFS
Since the low voltage L is applied to the gate of the FET 20B and the write inhibit voltage H is applied to the drain of the MFSFET 20B,
A potential difference also occurs between the gate and the drain of B, and this potential difference may cause a change in the polarization state of the ferroelectric gate film of the MFSFET 20B. Therefore, data stored in the memory cell 21B may be destroyed.

SUMMARY OF THE INVENTION In view of the above, the present invention provides a nonvolatile storage element which does not need to destroy information stored in a non-selected nonvolatile storage element at the time of writing information while achieving high integration. It is an object of the present invention to provide a nonvolatile storage device and a method for driving the nonvolatile storage device .

[0017]

According to the present invention, there is provided a nonvolatile memory device comprising: a semiconductor substrate having a source region and a drain region sandwiching a channel region; A formed ferroelectric gate film, a gate electrode formed on the ferroelectric gate film, a gate wiring formed on the gate electrode, and a gate electrode on a drain region side of the gate electrode,
A writing sidewall made of a conductive material formed in an insulating state with respect to the ferroelectric gate film and the semiconductor substrate; and a gate electrode, a ferroelectric gate film and a semiconductor substrate on the source region side of the gate electrode. On the other hand, there is provided a read sidewall made of a conductive material formed in an insulating state, and the write sidewall is connected to a gate wiring.

In the nonvolatile memory device using the nonvolatile memory element, the nonvolatile memory elements are arranged in a matrix, and the gate of each nonvolatile memory element is
The word lines are connected to each other, the sources and drains of the adjacent nonvolatile memory elements are connected to each word line, the source-drain connection intermediate points, the sources and drains of the nonvolatile memory elements at both ends, and The bit lines are connected to the sidewalls.

Since this nonvolatile memory device has a one-transistor / one-cell structure, it contributes to high integration.
In the method for driving a nonvolatile memory device, at the time of writing information, a first high voltage is applied to a word line connected to the nonvolatile memory element to be written, and the nonvolatile memory element to be written is selected. Therefore, a write voltage is applied to the bit line connected to the drain of the nonvolatile storage element, and a write inhibit voltage is applied to the bit line connected to the drain of the non-selected nonvolatile storage element. And applying a first low voltage lower than the first high voltage to the other word lines and bit lines, and when reading information, to a word line connected to a nonvolatile memory element for reading. in contrast, the non
When data is written to the volatile element, the source
A high voltage for forming a channel between the drain and the drain is applied to select a nonvolatile memory element from which data is read, so that a bit line connected to a read sidewall of the nonvolatile memory element is read. Apply voltage,
The bit line connected to the source is grounded to ground, and the bit line connected to the drain is
A high voltage for sensing conduction between a source and a drain is applied, and when erasing information, a second voltage is applied to the semiconductor substrate .
A low voltage is applied to a word line connected to a nonvolatile memory element for erasing by applying a high voltage.
The second low voltage is applied.

In the above driving method, a potential difference occurs between the gate and the drain of the nonvolatile memory element selected at the time of writing information, polarization occurs in the ferroelectric gate film, and data is written. At this time, the reading sidewall is
Since the gate electrode, the ferroelectric gate film, and the semiconductor substrate are formed in an insulated state, the transistor portion of the sidewall is not turned on, and the area below the reading sidewall is always an offset region, The electrons are aligned in the channel region excluding the side offset region.

On the other hand, at the time of writing, a write inhibit voltage is applied to the drain of an unselected nonvolatile memory element to which a low voltage is applied to the gate. Since it is formed insulated from the ferroelectric gate film and the semiconductor substrate and is connected to the gate wiring, the transistor portion of the side wall is not turned on, and the area below the write side wall is always offset. Since the write inhibit voltage of the drain is cut off by the offset region on the drain side, the polarization of the ferroelectric gate film of the non-selected nonvolatile memory element does not need to be changed, and information is destroyed. It will not be done.

At the time of reading information, the transistor portion of the reading sidewall is turned on. At this time,
If information is written in the nonvolatile memory element, electrons are aligned between the source region and the drain region to form a channel, and the information is read. Also, when erasing information, a reverse bias is applied at the time of writing, and the ferroelectric gate films of all the non-volatile memory elements connected to one word line undergo polarization reversal. All lines are erased.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to FIGS. An electrical configuration of the nonvolatile memory device (hereinafter, referred to as a nonvolatile memory) according to the present embodiment will be described with reference to FIG. FIG. 1 is an equivalent circuit diagram of a nonvolatile memory according to one embodiment of the present invention.

As shown in FIG. 1, the nonvolatile memory of this embodiment has a one-transistor / one-cell structure, and a field-effect transistor (hereinafter, referred to as an MF) having a ferroelectric gate film.
SFET (metal ferroelectric semiconductor field e
ffect transistor)) 30A, 30B, 30C,
A nonvolatile memory element (hereinafter, referred to as a nonvolatile memory cell) 31 including 30D, 30E, 30F, 30G, and 30H
A, 31B, 31C, 31D, 31E, 31F, 31
G and 31H are arranged in a matrix with a predetermined capacity (8 bits in the figure). In the following description, MFSFETs 30A, 30B, 30C, 30D, 3
0E, 30F, 30G, and 30H are collectively referred to as "MF
SFET 30 ".

The MFSFETs 30A, 30B, 3
The word lines WL1 and WL2 are connected to the gates of 0C, 30D and 30E, 30F, 30G, and 30H, respectively, and the adjacent MFSFETs 30A, 30B, 30C, 30D, and 3 are connected to each of the word lines WL1 and WL2.
Sources and drains of 0E, 30F, 30G, and 30H are connected. Furthermore, the MFSFETs 30A, 30D and 30D at the source-drain connection midpoint and both ends
E, source and drain of 30H and MFSF to be described later
The bit line BL is placed on the reading side wall of the ET30.
1, BL2, BL3, BL4, BL5, BL6, BL
7, BL8 and BL9 are respectively connected.

The operation of writing, reading, and erasing information (data) in the nonvolatile memory will be described. <Write> Data write is performed serially for each word line. For example, the nonvolatile memory cells 31A, 31B, 31 to which the word line WL1 is connected
It is assumed that data is written to C and 31D.

First, in order to apply a high voltage H to the word line WL1 and select the nonvolatile memory cell 31A, a write voltage is applied to the bit line BL3 connected to the drain of the MFSFET 30A of the memory cell 31A. L is applied to the non-selected nonvolatile memory cells 31B,
31C, 31D MFSFETs 30B, 30C, 30D
Bit lines BL5 and BL connected to the drains of
7, BL9 is applied to the other word lines WL2 and bit lines BL1, BL2, B
A low voltage L is applied to L4, BL6 and BL8, respectively.

Then, a potential difference is generated between the gate and the drain of the MFSFET 30A according to the operation principle of the MFSFET 30 described later, and the ferroelectric gate film of the MFSFET 30A is polarized, so that data is written to the memory cell 31A. On the other hand, MFSFETs 30B, 30C, 3
No potential difference occurs between the gate and the drain of 0D, and MFS
Since the ferroelectric gate films of the FETs 30B, 30C, and 30D are not polarized, data is not written in the memory cells 31B, 31C, and 31D.

Next, in order to apply a low voltage L to the bit line BL3 and select the nonvolatile memory cell 31B, write to the bit line BL5 connected to the drain of the MFSFET 30B of the memory cell 31B. When the input voltage L is applied, data is written to the memory cell 31B. Thereafter, the low voltage L is sequentially applied to the bit lines BL5 and BL7 in the direction of arrow X shown in FIG.
C, 31D, the memory cells 31C, 3
By applying the write voltage L to the bit lines BL7 and BL9 connected to the drains of the 1D MFSFETs 30C and 30D, respectively, the memory cells 31C and 31
D is written with data. <Read> For example, it is assumed that data stored in the nonvolatile memory cell 31A is read. In order to apply a high voltage H to the word line WL1 connected to the memory cell 31A and select the memory cell 31A, the high voltage H is applied to the bit line BL2 connected to the reading sidewall of the MFSFET 30A of the memory cell 31A. A read inhibit voltage L or a read voltage H is applied, the bit line BL1 connected to the source is grounded, and a high voltage H is applied to the bit line BL3 connected to the drain.

When the read inhibit voltage L is applied to the bit line BL2, the transistor portion of the read sidewall is not turned on, and the data read is inhibited. on the other hand,
When a read voltage H is applied to the bit line BL2,
The transistor portion of the read side wall is turned on, and data can be read. At this time, the memory cell 31
If data is written to A, MFSFET 30A
And the channel is formed. By sensing this state with a decoder and a sense amplifier (not shown) connected to the outside, data stored in the memory cell 31A is read. <Erase> Data is erased collectively for each word line. For example, it is assumed that data is erased from the nonvolatile memory cells 31A, 31B, 31C, and 31D to which the word line WL1 is connected. High voltage H for semiconductor substrate
And a low voltage L is applied to the word line WL1. Its will Then, the memory cell 31A, 31B, 31
C, 31D MFSFETs 30A, 30B, 30C, 3
Since a reverse bias is applied to the gate of 0D when data is written and the ferroelectric gate films of the MFSFETs 30A, 30B, 30C, and 30D are inverted, the memory cell 31
The data stored in A, 31B, 31C, and 31D are collectively erased.

The structure of the MFSFET 30 is shown in FIG.
This will be described with reference to FIG. FIG. 2 is a sectional view showing the structure of the MFSFET, and FIG. 3 is a plan view thereof. MFSF
As shown in FIG. 2, the ET 30 has N
A P-type silicon substrate 43 having a (100) plane orientation on which a type source region 41 and an N-type drain region 42 are formed; a ferroelectric gate film 44 formed on a channel region 40;
Gate electrode 45 formed on ferroelectric gate film 44
And a gate wiring 46 formed on the gate electrode 45, and has a so-called MFS structure.

Immediately above the source region 41 and the drain region 42, LOCOS (local oxidation of silicon)
There is provided a field oxide film 47 formed in a thick film by the method. Then, on the field oxide film 47, S
An iO ₂ film 48 is formed. On the drain region 42 side of the gate electrode 45, a writing sidewall 49 is formed via a SiO ₂ film 48 in an insulating state with respect to the gate electrode 45, the ferroelectric gate film 44 and the semiconductor substrate 43. On the source region 41 side, a reading sidewall 50 is formed via a SiO ₂ film 48 in an insulated state with respect to the gate electrode 45, the ferroelectric gate film 44 and the semiconductor substrate 43.

The side walls 49 and 50 are made of a conductive material, and the width D is set to 0.2 to 0.3 μm. The write side wall 49 is connected to the gate wiring 46 and the read side wall 50
Are surrounded by a SiO ₂ film 48. Further, as shown in FIG. 3, the gate wiring 46 is routed in a direction orthogonal to the reading side wall 50.

A method for manufacturing the MFSFET 30 will be described with reference to FIG. FIG. 4 is a cross-sectional view showing a method for manufacturing the MFSFET in the order of steps. As shown in FIG.
The SiO ₂ film 6 is formed on the P-type silicon substrate 43 by thermal oxidation.
After the formation of the Si ₃ N ₄ film 61 on the SiO ₂ film 60,
To form As in FIG. 4 (b), the follower Seo lithography, a resist is coated on the Si ₃ N ₄ film 61 by etching the Si ₃ N ₄ film 61 is removed, leaving the transistor operation region, SiO ₂ film Expose 60.

As shown in FIG. 4C, the Si ₃ N ₄ film 61 is used as a mask, and phosphorus ions are doped by, for example, an implant, and the N region is formed on the surface layer of the P-type silicon substrate 43 with the channel region 40 interposed therebetween. Form source region 41 and N-type drain region 42 are formed. As shown in FIG. 4D, a thick field oxide film 47 is formed by growing the SiO ₂ film 60 on the source region 41 and the drain region 42 by a LOCOS method such as steam oxidation. At this time, the depth of the source region 41 and the drain region 42 is
The O ₂ film 60 grows and becomes shallow due to erosion.

As shown in FIG. 4E, by etching,
After removing the Si ₃ N ₄ film 61 and the SiO ₂ film on the channel region, for example, CVD (chemical vapor deposition)
n) Ferroelectric 62, polysilicon 63
Are sequentially deposited. As shown in FIG. 4F, after a resist is applied on the polysilicon 63 by the phosolithography technique, a part of the ferroelectric 62 and the polysilicon 63 is removed by etching to form a ferroelectric gate film. 44,
A gate electrode 45 is formed.

As shown in FIG. 4G, an SiO ₂ film 48 is formed on the entire surface by thermal oxidation. As shown in FIG. 4H, a conductive material 64 such as polysilicon is deposited on the SiO ₂ film 48 by, eg, CVD. FIG. 4 (i)
As described above, the polysilicon 64 is removed by etching to form sidewalls 49 and 50 on both sides of the gate electrode 45 (on the side of the source region 41 and the drain region 42). .

As shown in FIG. 4J, the entire surface is covered with the SiO ₂ film 48 by, for example, the CVD method. As shown in FIG. 4K, a resist 65 is applied on the SiO ₂ film 48 so as to cover the reading side wall 50 and a mask is applied. Then, the SiO ₂ film 48 is selectively removed by HF etching. Then, a part of the gate electrode 45 and the write sidewall 49 are exposed.

As shown in FIG. 4 (l), after removing the resist 65, polysilicon is deposited on the gate electrode 45,
The gate wiring 46 is formed so as to be connected to the write sidewall 49. In the sidewall forming step shown in FIG. 4I, the thickness of the polysilicon 64 and the width of the sidewalls 49 and 50 are substantially equal. This can be done by controlling the thickness. Therefore, the side wall 4
In Nos. 9, 50, regardless of the phosolithography technology, a small one can be formed, so that the gate length does not need to be increased so much and does not affect high integration.

The operation principle of the FET 30 will be described with reference to FIGS.
This will be described with reference to FIG. FIG. 5 is a diagram showing the operation principle of the FET, and FIG. 6 is an equivalent circuit diagram of the FET. FIG. 5A shows a write state, and FIG. 6B shows a read state. <Write> As shown in FIG. 6A, the MFSF
The high voltage H is applied to the gate of the ET 30, the low voltage L is applied to the source and the reading side wall 50 , and the write voltage L is applied to the drain.
Is applied, a potential difference is generated between the gate and the drain, and as shown in FIG. 5A, polarization occurs in the ferroelectric gate film, and data is written.

At this time, the read sidewall 50 is
Since the gate electrode 45, the ferroelectric gate film 44, and the semiconductor substrate 43 are formed in an insulated state, the transistor portion of the reading side wall 50 is not turned on, and the area below the reading side wall 50 is always an offset region. OS
Becomes Therefore, the electrons are aligned in the channel region excluding the offset region OS.

On the other hand, at the time of writing, an MFSFET in which a low voltage L is applied to the gate (for example, when the MFSFET 30A shown in FIG.
The write inhibit voltage H is applied to the drains 30F, 30G, and 30H as described above. However, the write sidewall 49 includes the gate electrode 45, the ferroelectric gate film 44, and the semiconductor substrate. Since it is formed in an insulated state with respect to 43 and is connected to the gate wiring 46, the transistor portion of the write sidewall 49 is not turned on, and the area below the write sidewall 49 is always an offset region.

Therefore, the write inhibit voltage H of the drain
Is blocked by the drain-side offset region, so that the polarization of the ferroelectric gate film of the MFSFET does not change. Therefore, the information of the MFSFET is not destroyed. <Reading> As shown in FIG. 6B, at the time of reading data, a high voltage H is applied to the gate of the MFSFET, a source is grounded to the ground, a high voltage H is applied to the drain, and When the read voltage H is applied, the transistor portion of the read sidewall 50 is turned on.

At this time, if the ferroelectric gate film is not polarized, that is, if no data is written, no channel is formed between the source region 41 and the drain region 42, and the MFSFET 30 does not conduct. on the other hand,
If the ferroelectric gate film is polarized, that is, if data is written, as shown in FIG.
The electrons are aligned between the first and drain regions 42 to form a channel, and the MFSFETFET 30 is turned on to read data.

As described above, according to the present embodiment, it is possible to contribute to the high integration and not to destroy the data information stored in the non-selected memory cells when writing data. Therefore, FACE (Flash Array Contactle
ss EPROM). It should be noted that the present invention is not limited to the above-described embodiment, and it goes without saying that many modifications and changes can be made within the scope of the present invention.

[0046]

As is clear from the above description, according to the first to third aspects of the present invention, at the time of writing information, the information stored in the non-selected non-volatile memory element is written while achieving high integration. It has an excellent effect that it does not need to be destroyed.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of a nonvolatile memory according to one embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a structure of an MFSFET.

FIG. 3 is a plan view of the same.

FIG. 4 is a cross-sectional view showing a method for manufacturing the MFSFET in the order of steps.

FIG. 5 is a diagram illustrating an operation principle of the MFSFET.

FIG. 6 is an equivalent circuit diagram of the MFSFET.

FIG. 7 is an electric circuit diagram of a memory cell using a conventional ferroelectric capacitor.

FIG. 8 is a cross-sectional view of a conventional MFSFET.

FIG. 9 is a diagram showing PE hysteresis characteristics of a ferroelectric substance.

FIG. 10 is an equivalent circuit diagram of a conventional nonvolatile memory having a three-transistor / 1-cell structure.

FIG. 11 is an equivalent circuit diagram of a conventional nonvolatile memory having a one-transistor / one-cell structure.

[Explanation of symbols]

30, 30A, 30B, 30C, 30D, 30E, 30
F, 30G, 30HMFSFET 31, 31A, 31B, 31C, 31D, 31E, 31
F, 30G, 30H memory cell 40 channel region 41 source region 42 drain region 43 silicon substrate 44 ferroelectric gate film 45 gate electrode 46 gate wiring 49 write sidewall 50 read sidewall WL1, WL2 word line BL1, BL2 , BL3, BL4, BL5, BL6, B
L7, BL8, BL9 bit line

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁷ identification code FI H01L 29/792 (58) Investigated field (Int.Cl. ⁷ , DB name) H01L 21/8247 G11C 11/401 H01L 27/105 H01L 29/788 H01L 29/792

Claims (3)

(57) [Claims] 1. A semiconductor substrate having a source region and a drain region formed with a channel region interposed therebetween, a ferroelectric gate film formed on the channel region, and a gate formed on the ferroelectric gate film. An electrode, a gate wiring formed on the gate electrode, and a conductive material formed on the drain region side of the gate electrode in a state insulated from the gate electrode, the ferroelectric gate film, and the semiconductor substrate. A gate electrode, a ferroelectric gate film, and a read sidewall made of a conductive material formed in an insulating state with respect to the semiconductor substrate on the source region side of the gate electrode. The non-volatile memory element, wherein the embedded sidewall is connected to a gate wiring. 2. The nonvolatile memory element according to claim 1, wherein said nonvolatile memory elements are arranged in a matrix, word lines are respectively connected to gates of said nonvolatile memory elements, and said nonvolatile memory elements are adjacent to each other for each word line. A source and a drain are connected, and a bit line is connected to each of the source-drain connection midpoints, the source and the drain of each of the nonvolatile storage elements at both ends, and each of the read sidewalls. Storage device. 3. The nonvolatile memory device according to claim 2, wherein at the time of writing information, a first high voltage is applied to a word line connected to the nonvolatile memory element to which writing is performed. In order to select a nonvolatile memory element, a write voltage is applied to the bit line connected to the drain of the nonvolatile memory element, and the write voltage is applied to the bit line connected to the drain of the non-selected nonvolatile memory element. the write inhibit voltage is applied Te, first lower than the first high voltage to the other word lines and bit lines
At the time of reading information, a low voltage is applied to the word line connected to the nonvolatile memory element to be read .
When data is written to the device, the source
Apply a high voltage to form a channel between the rain ,
In order to select a nonvolatile memory element from which data is to be read, a read voltage is applied to a bit line connected to a read sidewall of the nonvolatile memory element, and a bit line connected to a source is grounded to ground. And the source line is connected to the bit line connected to the drain.
A high voltage for sensing conduction between drains is applied. When erasing information, a second high voltage is applied to the semiconductor substrate to apply a high voltage to a word line connected to a non-volatile memory element for erasing. A method for driving a nonvolatile memory device, wherein a second low voltage lower than the second high voltage is applied.