JP3153677B2 - Pulse width measuring device, time difference measuring device, and IC testing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse width measuring device for measuring a pulse width with high accuracy without using a high frequency clock, and furthermore, a time difference between any two pulses is determined by using a high frequency clock. A time difference measuring device for measuring with high accuracy as unnecessary, and furthermore, when performing an IC test, a time difference between any two clocks or timings, that is, a phase shift is adjusted as desired. The present invention relates to an IC test apparatus configured to perform an IC test with high accuracy.

[0002]

2. Description of the Related Art FIG. 13 shows a configuration of an example of a time difference measuring apparatus according to the prior art, and FIG. 14 shows an input / output signal waveform of an essential part of the example. The operation thereof will be described below. It is like. That is, as shown, a start signal Ain is supplied to an input terminal 204 of a set / reset flip-flop (hereinafter, simply referred to as RS-F / F) 201.
When the stop signal Bin is sequentially input as a reset input via the input terminal 205 as a set input via the input terminal 205, a pulse having a pulse width equal to the time difference between the start signal Ain and the stop signal Bin (hereinafter, referred to as The signal 211 is simply output as its Q output and supplied to the AND gate 202 as one input. Therefore, in a state where the time difference pulse 211 is supplied to the AND gate 202, the reference clock 208 from the reference clock source 206 is used as another input and A
When input to the ND gate 202, the time difference pulse 21
The reference clock 208 is output from the AND gate 202 as the AND gate output 212 only while the time difference pulse 211 is present, with 1 as a gate control signal. Therefore, when the reference clock 208 output from the AND gate 202 is counted by the count measurement counter 203, the number of the reference clocks 208 is obtained from the output terminal 207 as the final count value 209. In general, since the cycle of the reference clock 208 is known in advance, if the number is multiplied by the clock cycle, the time difference between the start signal Ain and the stop signal Bin can be measured.

[0003] It should be noted that as a known document concerning this kind of apparatus, for example, Hewlett-Packard Company Application Note 200 Fundamentals of the
Electronic Counters (1978) 25th
From page to page 35 (HEWLETT PACKARD APPLICATION NOTE 2
00 FUNDAMENTALS OF THE ERECTORONIC COUNTERS (1978) P
P25-35).

[0004]

By the way, in the case of the above-mentioned prior art, the time difference pulse 211 output from the RS-F / F 201 and the reference clock 208 are generally in an asynchronous state. Of the reference clocks 208 to be output, those output first or last may have a pulse width not sufficiently large. As shown in FIG. 14, for example, while the reference clock 208 is being input to the AND gate 202, the start signal A
When "in" is input, the time difference pulse 211 is input as a gate control signal to the AND gate 202 for the first time after the input time, so that the reference clock 208 output first from the AND gate 202 has the pulse width Is Tp with respect to the original pulse width Tpws of the reference clock 208.
It is output as the state reduced to w1. Further, even when the stop signal Bin is input while the reference clock 208 is being input to the AND gate 202, the time difference pulse 211 does not exist at the time of the input, so the output from the AND gate 202 is finally output. The reference clock 208 is output in a state where its pulse width is reduced to Tpw2 from the original pulse width Tpws of the reference clock 208. In such a case, the problem is whether or not the reference clock 208 having a pulse width smaller than the original pulse width Tpws of the reference clock 208 can be normally counted by the counting / measuring counter 203. Generally, the pulse widths Tpw1, Tpw2
Is greater than or equal to the pulse width Twmin that can be detected on the input side of the counting / measuring counter 203, as shown in 1), the counting / measuring counter 203 outputs "5" as the final count value 209. If it is less than Twmin, as shown in 2), the count measurement counter 203
Output "3" as the count value 209. Thus, even if the time difference is the same, the count value 209 becomes “4 ± 1”, for example.
The final count value 209 may change (this is usually referred to as ± 1 count error) depending on the input timing of the start signal Ain and the stop signal Bin. Therefore, in such a case, in order to improve the measurement accuracy, it is necessary to repeat the measurement and perform averaging of the measurement results (averaging process). On the other hand, as the measurement accuracy is improved, In fact, it is undeniable that much time is required for measurement.

A first object of the present invention is to provide a pulse width measuring apparatus which can quickly and accurately measure a pulse width without using a high frequency clock. A second object of the present invention is to provide a time difference measuring device which can quickly and accurately measure a time difference between any two pulses without using a high frequency clock.
A third object of the present invention is to perform an IC test.
An object of the present invention is to provide an IC test apparatus capable of performing a test on an IC under test in a state where a time difference between two arbitrary clocks or timings, that is, a phase shift is adjusted with high precision.

[0006]

A first object of the present invention is to basically delay a pulse from the preceding stage in the cascade connection and with the same variable pulse width reduction characteristics which are variable. In between, the pulse width of the pulse is reduced by a fixed pulse width, and a plurality of pulse width reduction circuits for outputting to the subsequent position are provided. A minimum allowable width pulse presence / absence detection circuit for detecting whether or not the pulse width of the pulse to be performed is greater than or equal to the minimum allowable width, and based on the minimum allowable width pulse presence / absence detection result from each of the minimum allowable width pulse presence / absence detection circuits, This is achieved by including a pulse width calculation circuit that externally displays and outputs data indicating the pulse width of the pulse input to the plurality of pulse width reduction circuits.

The second object is basically to provide a time difference pulse generating circuit for outputting a time difference pulse with a time difference between two externally input pulses as a pulse width;
With the time difference pulse from the time difference pulse generation circuit as an input pulse, the pulse width of the pulse is set to a constant pulse width while being cascaded and delaying the pulse from the preceding stage with the same pulse width reduction characteristic. A plurality of pulse width reduction circuits that are output after the plurality of pulse width reduction circuits, and are provided corresponding to the respective pulse width reduction circuits, and the pulse width of the pulse output from the pulse width reduction circuit is equal to or greater than the minimum allowable width. A minimum allowable width pulse presence / absence detection circuit for detecting whether there is a pulse, and a time difference inputted to the plurality of pulse width reduction circuits based on the minimum allowable width pulse presence / absence detection results from each of the minimum allowable width pulse presence / absence detection circuits. A pulse width calculation circuit that externally displays and outputs data indicating the pulse width of the pulse;
It is achieved by comprising to include.

A third object of the present invention is to sequentially apply various test signals to the IC under test at each test cycle, while providing a response signal to the applied test signal from the IC under test.
An IC test apparatus that is sequentially compared with an expected value that is separately created and stored in advance at a predetermined determination timing, so that the quality of the function as an IC is determined from the result of the comparison. A test cycle clock created from the reference clock, a test signal generation timing corresponding to various test signals created based on the test cycle clock, and various applied test signals created based on the test cycle clock. When any two clocks or timings are directly or indirectly input among the determination timings of the response signal, a time difference between the clocks or the timings is measured, and the time difference is determined based on the measurement result. In order to adjust the amount of phase shift between the clocks or the timings as desired, between two externally input pulses A time difference pulse generating circuit that outputs a time difference pulse with the time difference as a pulse width, and a time difference pulse from the time difference pulse generation circuit as an input pulse, in a cascade-connected state, and with the same pulse width reduction characteristic, While delaying the pulse, the pulse width of the pulse is reduced by a constant pulse width, and a plurality of pulse width reduction circuits for outputting the pulse width at the rear are provided, and the pulse width reduction circuit is provided for each of the pulse width reduction circuits. A minimum allowable width pulse presence / absence detection circuit for detecting whether the pulse width of the pulse output from the reduction circuit is equal to or greater than the minimum allowable width, and a minimum allowable width pulse presence / absence detection result from each of the minimum allowable width pulse presence / absence detection circuits A pulse width calculation circuit that externally displays and outputs data indicating the pulse width of the time difference pulse input to the plurality of pulse width reduction circuits, Is achieved by allowed to include a time difference measuring device comprising.

[0009]

Generally, when a pulse is input to a circuit whose delay time at the falling edge is shorter than the delay time at the rising edge, the pulse output through the circuit has a pulse width equal to the input time. It can be obtained as a reduced state as compared with the one in. Therefore, in a state where a delay circuit having a shorter delay time at the falling edge than the delay time at the rising edge (hereinafter referred to as a pulse width reducing circuit) is cascaded in a plurality of stages, a pulse is applied from one end to the delay circuit. Is input, each time the pulse is passed through an individual pulse width reducing circuit, the pulse width is obtained as a state in which the pulse width is reduced by a constant pulse width. Therefore, a minimum allowable width pulse presence / absence detection circuit is provided for each pulse width reduction circuit, and each of the minimum allowable width pulse presence / absence detection circuits has a minimum pulse width of the pulse output from the corresponding pulse width reduction circuit. By detecting whether or not the pulse width is equal to or greater than the allowable width, the number of stages of the pulse width reduction circuit that outputs the output pulse as equal to or greater than the minimum allowable width is known.Furthermore, from the number of stages and the constant pulse width, the input pulse The pulse width is known. If an input pulse to a pulse width reduction circuit connected in cascade is generated as a time difference pulse between two pulses, the time difference can be measured as the pulse width of the time difference pulse.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to FIGS. First, the pulse width measuring apparatus according to the present invention will be described. FIG. 1 shows an example of the entire configuration. As shown, pulse width reduction circuits 1402 to 1404 cascaded in a plurality of stages, and a pulse width reduction circuit 140
Minimum tolerable pulse presence / absence detection circuits 1405 to 1407 provided on the output side corresponding to each of 2 to 1404, and an encoder (pulse width calculation circuit) provided at the output side of the minimum tolerable width pulse presence / absence detection circuits 1405 to 1407 ) 140
8 is included. Each time the pulse to be measured from the input terminal 1420 is sequentially passed through each of the pulse width reduction circuits 1402 to 1404, the pulse width is reduced by a fixed pulse width Tcut, while the pulse width is reduced from each of the pulse width reduction circuits 1402 to 1404. The detected pulse is a corresponding minimum allowable width pulse presence / absence detection circuit 14.
05 to 1407. Minimum allowable width pulse presence / absence detection circuit 1405
1407, pulse width reduction circuits 1402 to 14
04 is the minimum allowable width Twm of the output pulse from each.
If the pulse width is less than the minimum allowable width Twmin, a logical value indicating that the output pulse could not be detected is output. This is what has been output. Encoder 1408
Then, the minimum allowable width pulse presence / absence detection circuits 1405 to 1
Digital data indicating the number N of stages of the pulse width reduction circuit that has passed before the pulse to be measured becomes smaller than the minimum allowable width Twmin is first created based on the logical value output from each of the logic stages 407. The pulse width of the pulse to be measured is calculated from the number of passing stages N, the fixed pulse width Tcut, and the minimum allowable width Twmin, and then output to the external terminal via a terminal 1415. The information is displayed and output to the outside via the interface 1415.
Before the pulse width measurement of the pulse to be measured, each of the minimum allowable pulse presence / absence detection circuits 1405 to 1407 needs to be initialized by a reset signal from the input terminal 1413. Pulse width reduction circuits 1402 to 14
04 constant pulse width Tcu as pulse width reduction amount in each
If t is variably and compulsorily set and controlled to be the same, the variation in the delay time between the pulse width reduction circuits 1402 to 1404 can be corrected prior to the measurement, and the pulse width measurement accuracy can be reduced. It can be improved.
In this example, the number of stages of the pulse width reduction circuit is shown as three, but the number of stages and the installation interval may be appropriately determined according to each case or purpose.

Next, the time difference measuring apparatus according to the present invention will be described. FIG.
FIG. 3 shows a waveform of an input / output signal of the relevant part in an example. As shown in the figure, the configuration is such that a time difference pulse generation circuit 101 is added to the pulse width measurement device shown in FIG. 1 slightly. In 101, time difference pulse 1
The situation is the same as in the case of the pulse width measuring device described above, except that it is generated as 20. That is, as shown in FIG. 2, the time difference measuring device includes a time difference pulse generation circuit 101, three-stage cascade-connected pulse width reduction circuits 102 to 104, and a minimum allowable width pulse presence / absence detection circuit 10
5 to 107 and an encoder 108. Prior to the time difference measurement, the time difference pulse generation circuit 101 and the minimum allowable width pulse presence / absence detection circuits 105 to 107 are initialized by a reset signal from the input terminal 113.
14, the pulse width reduction circuit 102
The constant pulse width Tcut as the pulse width reduction amount in each of the control signals .about.104 is variably set and is forcibly set and controlled to be the same. If the constant pulse width Tcut is controlled as such, the pulse width reduction circuits 102 to
Variations in the delay time between the 104 can be corrected prior to the measurement, and the accuracy of the time difference measurement can be improved.

The operation will be described with reference to FIG. 3. For the time difference pulse generating circuit 101, a start signal Ain is supplied via an input terminal 111 and a stop signal Bin is supplied via an input terminal 112. When sequentially input, a time difference pulse 120 having a pulse width equal to the time difference between the start signal Ain and the stop signal Bin is generated from the time difference pulse generation circuit 101, and is applied to each of the pulse width reduction circuits 102 to 104. They are input sequentially. Now, from each of the pulse width reduction circuits 102 to 104, the pulse width of the leading pulse is Tdh-T
The output pulses 121 to 123 output from the pulse width reduction circuits 102 to 104 are output while being output as output pulses 121 to 123 in a state reduced by dl (= constant pulse width Tcut). , Corresponding to the minimum allowable width pulse presence / absence detection circuits 105-107. In response, the minimum allowable width pulse presence / absence detection circuits 105 to 107 respectively output the output pulses 121 to 121 from the pulse width reduction circuits 102 to 104, respectively.
If the pulse width of 123 is equal to or greater than the minimum allowable width Twmin, pulse detection outputs 131 to 13 indicating that an output pulse has been detected
3 is output. If the pulse width is smaller than the minimum allowable width Twmin, pulse detection outputs 131 to 133 indicating that the output pulse could not be detected are output. The encoder 1408 also determines, based on the pulse detection outputs 131 to 133 from the minimum allowable width pulse presence / absence detection circuits 105 to 107, the number of stages N of the pulse width reduction circuit that has passed until the time difference pulse 120 becomes smaller than the minimum allowable width Twmin. The digital data shown is first created. The number of passing stages N is directly displayed and output to the outside via the output terminal 115, or the time difference pulse N is obtained from the number of passing stages N, the fixed pulse width Tcut, and the minimum allowable width Twmin. 1
Although a detailed description of the pulse width of 20, ie, derivation is omitted, the time difference Ti is Ti = (N + Ｎ) Tcut +
Twmin is calculated and output to the outside via the output terminal 115. As described above, since the accuracy of the time difference Ti is obtained as ± Tcut / 2, the smaller the difference between the delay time at the rising edge and the delay time at the falling edge, the smaller the time difference Ti becomes.
Can be measured with high precision. Incidentally, FIG. 3 shows a case where the pulse width reduction circuits 102 and 103 each output a pulse larger than the minimum allowable width Twmin, but the pulse width reduction circuit 104 does not output a pulse larger than the minimum allowable width Twmin. It is shown.

Here, a more specific example of the configuration of the time difference measuring device will be described with reference to FIG. In this example,
As shown, the time difference pulse generation circuit 101 is an RS-F
/ F 501 and the OR gate 508, the pulse width reduction circuits 102 to 104 are logic gates satisfying Tdh> Tdl (in this example, an AN in which one input is fixed to the “H” state).
D gates) 502 to 504, and the minimum allowable width pulse presence / absence detection circuits 105 to 107 are RS-F / F505
To 507. RS-F
A start signal as a set input to the / F 501 and a stop signal as a reset input are sequentially input, thereby generating a time difference pulse 120 as a Q output and delaying each of the logic gates 502 to 504 sequentially. It has become. In each of the logic gates 502 to 504 as a pulse width reducing circuit, the pulse from the preceding stage is outputted to the succeeding stage with the pulse width reduced by the fixed pulse width Tcut, while the minimum allowable width pulse is detected. RS-F / F505-507 as a circuit
In each case, the output pulses 121 to 123 from each of the logic gates 502 to 504 are input as a set input, so that if the pulse width of the output pulses 121 to 123 is equal to or more than the minimum allowable width Twmin, the output pulse is detected. The pulse detection outputs 131 to 133 are output as "H" state. If the pulse width is less than the minimum allowable width Twmin, the pulse detection outputs 131 to 133 indicate that no output pulse can be detected. Are output as the “L” state. In the time lag measuring device of this example, the constant pulse width Tcut is not actively controlled as being variable by an external control signal. The OR gate 508 operates when a reset signal is input from the input terminal 113 or when the input terminal 112
When a stop signal is input, RS-F / F5
01 is to be initialized (reset).

FIG. 5 also shows a time difference pulse generation circuit 101.
3 shows another specific configuration example. As shown in the figure, in this example, a D-type flip-flop (hereinafter simply referred to as DF / F) 601 and an OR gate 602 are provided, and the data input of the DF / F 601 is in the “H” state. In the fixed state, a start signal is input as a clock signal from the input terminal 111 to be in a set state, while a stop signal is input from the input terminal 112 via the OR gate 602 as a reset input. It is in a reset state, and as a result, a time difference pulse 120 is generated as its Q output.

FIG. 6 shows another specific configuration example of the pulse width reduction circuits 102 to 104, and FIG. 7 shows the operation of the circuit. For simplicity of explanation, the pulse width reducing circuit 10
2, only the pulse width reduction circuits 103 and 10 are shown.
4 has the same configuration. As shown, the pulse width reduction circuit 102 is basically composed of cascaded MOS inverters 701 and 702. The MOS inverter 701 further includes an input terminal between its source and ground. A resistance variable circuit 703 composed of a series-parallel connection of N-type MOS transistors whose resistance as a whole can be desirably set and controlled through a gate electrode by a control signal from 114 is inserted. ing. The time difference pulse 120 from the time difference pulse generation circuit 101 is applied to the MOS inverters 701 and 702
, The output pulse 121 to the pulse width reduction circuit 103 is obtained.
Is supplied as a resistance control signal to the gate electrode in the resistance variable circuit 703, so that the amount of decrease in the pulse width with respect to the time difference pulse 120 is actively controlled. More specifically, in a MOS transistor (series connected body) row in which the gate electrode is set to the “H” state by the resistance value control signal, a current flows from the drain side to the source side, and in the row, Can be approximated as one resistor (hereinafter, the resistance value is referred to as the ON resistance of R). FIG.
As shown in FIG. 5, the total resistance value when only the MOS transistor row A is turned on is R, and the total resistance value when only the MOS transistor row B is turned on is 2R, and M
The total resistance is 3R when only the OS transistor row C is turned on, and 4R when the only MOS transistor row D is turned on. Is what it is.
However, in addition to the above, if two or more MOS transistor arrays are controlled to be simultaneously turned on in an arbitrary combination, various other resistance values can be formed, and thus a desired total on-resistance value, As described below, a constant pulse width Tcut of a magnitude corresponding to the total on-resistance value is obtained.

In the circuit operation, if the rising edge side delay time when the MOS transistor row is turned on in a certain combination is Tdh (1), the total on-resistance in the resistance variable circuit 703 is When the value is set to increase, the rise time Tph (2) increases as compared with Tph (1), so that the delay time Tdh (2) on the rising edge side also increases. As a result, The constant pulse width Tcut is set to be large. Conversely, when the total on-resistance is set to decrease in the resistance variable circuit 703, the delay time Tdh on the rising edge side is set.
As a result of the reduction of (3), the constant pulse width Tcut is set to be small. That is, the constant pulse width Tcut per stage can be variably set by the control signal from the input terminal 114, and the constant pulse width Tcu
If t can be variably set by external control, the variation in the delay time between the pulse width reduction circuits 102 to 104 can be corrected prior to the measurement, thereby improving the accuracy of the time difference measurement. It can be achieved.

FIG. 8 also shows pulse width reduction circuits 102 to
FIG. 9 shows another specific configuration example of the circuit 104, and FIG. 9 shows the circuit operation thereof. For simplicity of explanation, only the pulse width reduction circuit 102 is shown, but the pulse width reduction circuit 10
The same configuration is adopted for 3,104. As shown in FIG.
The time difference pulse 120 from 1) has a plurality of paths 910-9.
12 are input to the three-input / one-output selector 1001 as selected inputs via the logic gates 921 to 923 inserted in the middle of each of the paths. Of these, different capacitive loads (logic gates in this example) 932 and 93 are provided on the gate output sides of the logic gates 922 and 923, respectively.
3 is connected in a branched state, and the pulse width reducing circuit 102 is configured. Each of the capacitive loads 932 and 933 in the present example is configured as a logic gate, and can function as a capacitive load by positively using the fan-in capacitance at the gate.

In the circuit operation, assuming that the capacitive loads 923 and 933 are not connected, the rising edge side delay time Tdh and the falling edge side delay time Tdl are applied to each of the logic gates 921 to 923. Relationship is Tdh
> Tdl, the time difference pulse 120 from the time difference pulse generation circuit 101 has a constant pulse width Tcut.
(= Tdh−Tdl), which can be output from each of the logic gates 921 to 923. However, when the capacitive loads 932 and 933 are connected, the pulse width reduction amounts of the logic gates 921 to 923 are made different from each other. As shown as an output pulse 121 (1) in FIG. 9, when the B input is selected and output from the selector 1001 by the control signal from the input terminal 114, the rising and falling edge side delay times are represented by Tph (1 ), T
If pl (1), the charging time is generally longer than the discharging time, so that Tph (1) and Tpl (1) satisfy Tph (1)> Tph (1).
pl (1). Tph and Tpl are the capacitive loads 9
32 and 933 are proportional to the capacitance values. Therefore, when the C input is selected and output from the selector 1001, the increase amount Tph with respect to the rising edge side delay time is indicated as the output pulse 121 (2).
(2) −Tph (1) is larger than the increase amount Tpl (2) −Tpl (1) with respect to the delay time on the falling edge side. As a result, the constant pulse width Tcut is set to be large. . Conversely, when the A input is selectively output from the selector 1001, the fan-in capacity is in a reduced state as compared with when the B input is selectively output, as shown as an output pulse 121 (3). Therefore, the constant pulse width Tcu
t is set to be small. As described above, the constant pulse width Tcut per stage can be variably set by the control signal from the input terminal 114, and the constant pulse width Tcut can be variably set by external control. , The pulse width reduction circuits 102 to 104
Variations in the delay time between each other can be corrected prior to the measurement, and the accuracy of the time difference measurement can be improved.

FIG. 10 shows another specific configuration example of the minimum allowable width pulse presence / absence detection circuit, and FIG. 11 shows the operation of the circuit. For simplicity of description, only the minimum allowable width pulse presence / absence detection circuit 105 is shown, but the same configuration is adopted for the minimum allowable width pulse presence / absence detection circuits 106 and 107. As shown in the figure, the minimum allowable width pulse presence / absence detection circuit 105 includes a diode bridge 1101 enabled by the output pulse 121 from the pulse width reduction circuit 102 and a voltage source 1102 while the diode bridge 1101 is in a conductive state. A capacitor 1103 that is in a charged state and a comparator 1105 that compares a charging voltage from the capacitor 1103 with a determination reference voltage from an input terminal 1130 are configured as main components, and the charge stored in the capacitor 1103 is Prior to the time difference measurement, a discharge signal can be discharged via the discharge circuit 1104 by a reset signal from the input terminal 113.

The operation is as follows. If the pulse width of the output pulse 121 from the pulse width reduction circuit 102 is longer than the switching time of the diode, the diode bridge 1101 is turned on and the diode bridge 1101 is turned on. , The diode bridge 1101 by the voltage source 1102
Is charged through the capacitor 1103. The charging causes a gradually increasing charging voltage 1106 to be generated in the capacitor 1103.
6 is compared with the judgment reference voltage from the input terminal 1130 by the comparator 1105.
6 reaches the judgment reference voltage or more, the comparator 110
From No. 6, the pulse detection output 131 in the “H” state is output to the encoder 108. That is, assuming that the switching time of the diode is Twmin, if the pulse width of the output pulse 121 is equal to or more than Twmin, the pulse detection output 131 in the “H” state is output from the comparator 1106.
Is obtained. Incidentally, FIG. 11 shows output pulses 122, 1 from the pulse width reduction circuits 103, 104, respectively.
The circuit operation for 23 is also shown. The pulse width of each of the output pulses 121 and 122 is Twmin
As described above, the pulse width Tpw of the output pulse 123 is Twm
in, the output pulses 122, 12
3, the charging voltages 1107 and 1108 change as shown, and the pulse detection outputs 131 and 132 are obtained as "H" state, and the pulse detection output 133 is obtained as "L" state. ing.

Finally, an IC test apparatus including a time difference measuring apparatus will be described. FIG. 12 shows a schematic configuration in one example. Generally, when testing the function of an IC under test by an IC test apparatus, various test signals are sequentially applied from the IC test apparatus to the IC under test every test cycle, while the applied test signals from the IC under test are applied. Are sequentially compared with expected values separately created and stored in advance in the IC test apparatus at a predetermined judgment timing, and based on the result of the comparison, whether the function as an IC is good or bad. Is to be determined. By the way, in recent years, along with the high speed operation of ICs in general,
When testing types, the phase difference between test signals,
It is necessary to maintain a desired relationship with a high precision between the determination timings of the response signal and the like. Therefore, a test cycle clock created from the reference clock, a test signal generation timing corresponding to various test signals created based on the test cycle clock, and a response to various applied test signals created based on the test cycle clock. When any two clocks or timings are directly or indirectly input in the signal determination timing, a time difference between the clocks or the timings is measured, and then the clocks are determined based on the measurement result. Alternatively, in order to adjust the amount of phase shift between timings as desired, an appropriate one of the various time difference measurement devices described above is provided in the IC test device.

The configuration of the timing generator J02 will now be described. In the timing generator J02, based on the original clock J18 from the original J01, a periodic clock for determining the test cycle and various edge clocks (generation timing of the applied test signal) are determined. , A judgment timing (judgment strobe) J16 for the response signal, and the like are generated. The edge clock J16 is supplied to the pin control unit J05 via the delay circuit J04 for adjusting the phase shift between the edge clocks. Pin control unit J0
5, the applied test signal is generated at the timing of generation of the test signal based on the pattern generation data from the pattern generation circuit J03. The generated applied test signal is generated by the driver in the pin electronics unit J06. Is converted into a signal level for the IC under test, and then applied to the IC under test J08 via the switch J07. On the other hand, when a test signal is applied to the IC under test J08, a response signal to the test signal is output from the IC under test J08. The response signal is shaped by a comparator in the pin electronics section J06 via the switch J07. At this time, signal level conversion is also performed based on the reference power supply. The response signal from the comparator is then compared with the expected value from the pattern generation circuit J03 at a predetermined judgment timing by a comparison judgment circuit in the pin control section J05, and the comparison judgment result is output from the timing generation circuit J02. Is stored in the fail memory below the write / read timing J15. The IC power supply under test J09 is a variable power supply for supplying power to the IC under test J08, and the DC measurement circuit J10 is provided for a DC test performed separately from the function test. The execution control of a series of tests described above is performed by the bus J on the IC test apparatus main body J14.
12 is automatically performed by the test control device J13 connected through the test control device J13.
The test results are comprehensively determined by reading out and comparing the comparison determination results saved and stored in the fail memory via the bus J12 as needed.

Incidentally, a time difference measuring circuit J11 is provided in the IC test apparatus main body J14 configured as described above to measure an arbitrary time difference between a test cycle clock and various edge clocks. . In this example, as shown, a reference signal such as an edge clock from the timing generation circuit J16 is input as a start signal, and various test signals transmitted through the switch J07 are selectively used as a stop signal. And the time difference is measured. Time difference measurement circuit J
11 is temporarily stored and held in the test control device J13 via the bus J12, and thereafter, the time difference measuring circuit J is sequentially turned on so that each of the measured time differences becomes a desired value.
By performing the time difference measurement at 11 and the delay adjustment at the delay circuit J04, the phase shift between the test signals is corrected. The phase shift of the determination strobe is corrected by inputting each test signal after the phase shift correction to a corresponding comparator as a reference signal,
This is done by adjusting.

The present invention has been described above. In the description, the pulse width of the signal in the "H" state is exclusively considered, but the same method is applied to the pulse width of the signal in the "L" state. It is clear that this can be dealt with.

[0025]

As described above, according to the first aspect, there is provided a pulse width measuring apparatus which does not require the use of a high frequency clock and which can quickly and accurately measure a pulse width. In the case of (10) to (10), a time difference measuring device capable of measuring the time difference between any two pulses with high accuracy without using a high-frequency clock and quickly is further provided. Is performed, a time difference between any two clocks or timings, that is, an IC test apparatus capable of performing a test on the IC under test with the phase shift adjusted with high precision is obtained. Has become.

[Brief description of the drawings]

FIG. 1 is a diagram showing an overall configuration of an example of a pulse width measuring apparatus according to the present invention.

FIG. 2 is a diagram showing an entire configuration of an example of a time difference measuring device according to the present invention.

FIG. 3 is a diagram showing an input / output signal waveform of a main part of the example.

FIG. 4 is a diagram showing a configuration of an example of a specifically configured time difference measuring device;

FIG. 5 is a diagram illustrating another specific configuration example of the time difference pulse generation circuit;

FIG. 6 is a diagram illustrating another specific configuration example of the pulse width reduction circuit;

FIG. 7 is a diagram showing the circuit operation;

FIG. 8 is a diagram showing still another different specific configuration example of the pulse width reduction circuit.

FIG. 9 is a diagram showing the circuit operation thereof;

FIG. 10 is a diagram showing another specific example of still another configuration of the minimum allowable width pulse presence / absence detection circuit;

FIG. 11 is a diagram showing the circuit operation;

FIG. 12 is a diagram showing a schematic configuration of an example of an IC test apparatus according to the present invention, including a time difference measuring apparatus.

FIG. 13 is a diagram showing a configuration of an example of a time difference measuring device according to the related art.

FIG. 14 is a diagram showing an input / output signal waveform of a main part in an example.

[Explanation of symbols]

101: time difference pulse generation circuit, 102 to 104, 14
02 to 1404: pulse width reduction circuit, 105 to 107,
1405 to 1407: Minimum allowable width pulse presence / absence detection circuit,
108, 1408... Encoders, 502 to 504, 92
1 to 923, 932, 933 ... logic gates, 501, 5
05-507 RS flip-flop, 601 D-type flip-flop, 701 702 MOS inverter,
703: variable resistance value circuit, 1001: selector, 110
1. Diode bridge, 1102. Voltage source, 1103
... capacitors, 1105 ... comparators, J14 ... IC
Test device main body, J11 ... time difference measuring device

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-3-102266 (JP, A) JP-A-2-90070 (JP, A) JP-A-62-147371 (JP, A) (58) Investigation Field (Int.Cl. ⁷ , DB name) G01R 29/02 G01R 31/26 G01R 31/28 G04F 10/00

Claims (11)

(57) [Claims] 1. A pulse width measuring device for measuring a pulse width of a pulse inputted from the outside, wherein said pulse width measuring device is connected in a cascade connection and has a variable pulse width decreasing characteristic. While delaying the pulse from, the pulse width of the pulse is reduced by a constant pulse width, and a plurality of pulse width reduction circuits for outputting to the subsequent position are provided. A minimum allowable width pulse presence / absence detection circuit for detecting whether or not the pulse width of the pulse output from the pulse width reduction circuit is equal to or greater than the minimum allowable width; and a minimum allowable width pulse presence / absence from each of the minimum allowable width pulse presence / absence detection circuits A pulse width calculation circuit that externally displays and outputs data indicating a pulse width of a pulse input to the plurality of pulse width reduction circuits based on a detection result. 2. A time difference measuring device for measuring a time difference between two pulses when two pulses are sequentially inputted from the outside, wherein the time difference between two pulses inputted from the outside is provided. A time difference pulse generating circuit that outputs a time difference pulse with the pulse width as a pulse width, and a time difference pulse from the time difference pulse generation circuit as an input pulse. A plurality of pulse width reducing circuits for reducing the pulse width of the pulse by a constant pulse width and outputting the pulse width at a subsequent position, and a pulse width reducing circuit provided for each of the pulse width reducing circuits. A minimum allowable width pulse presence / absence detection circuit for detecting whether the pulse width of the pulse output from the circuit is equal to or greater than the minimum allowable width; A pulse width calculation circuit for externally displaying and outputting data indicating the pulse width of the time difference pulse input to the plurality of pulse width reduction circuits based on the detection result of the small allowable width pulse presence / absence. 3. A time difference measuring device for measuring a time difference between two pulses when two pulses are sequentially input from the outside, comprising: a first and a second input from the outside.
Pulse as set input and reset input, respectively.
A time difference pulse generation circuit including, as a main component, an RS flip-flop that outputs, as a Q output, a time difference pulse whose pulse width is a time difference between the first and second pulses;
With the time difference pulse from the time difference pulse generation circuit as an input pulse, the pulse width of the pulse is set to a constant pulse width while being cascaded and delaying the pulse from the preceding stage with the same pulse width reduction characteristic. A plurality of pulse width reduction circuits that are output after the plurality of pulse width reduction circuits, and are provided corresponding to the respective pulse width reduction circuits, and the pulse width of the pulse output from the pulse width reduction circuit is equal to or greater than the minimum allowable width. A minimum allowable width pulse presence / absence detection circuit for detecting whether there is a pulse, and a time difference inputted to the plurality of pulse width reduction circuits based on the minimum allowable width pulse presence / absence detection results from each of the minimum allowable width pulse presence / absence detection circuits. A pulse width calculation circuit that externally displays and outputs data indicating the pulse width of the pulse;
Including a time difference measuring device. 4. A time difference measuring device for measuring a time difference between two pulses when two pulses are sequentially input from the outside, wherein the data input is fixed to a high level state. A D-type that outputs a time difference pulse whose pulse width is a time difference between the first and second pulses as a Q output and first and second pulses input from outside as a clock input and a reset input, respectively. A time difference pulse generation circuit including a flip-flop as a main component, and a time difference pulse from the time difference pulse generation circuit as an input pulse, in a cascade-connected state, and with the same pulse width reduction characteristics, a pulse from the preceding stage is used. During the delay,
A plurality of pulse width reducing circuits for reducing the pulse width of the pulse by a fixed pulse width and outputting the pulse width at a subsequent position, and a pulse provided for each of the pulse width reducing circuits and output from the pulse width reducing circuit A minimum allowable width pulse presence / absence detection circuit for detecting whether or not the pulse width of the minimum allowable width pulse is greater than or equal to the minimum allowable width; and detecting the minimum allowable width pulse presence / absence detection result from each of the minimum allowable width pulse presence / absence detection circuits. A pulse width calculation circuit for externally displaying and outputting data indicating the pulse width of the time difference pulse input to the width reduction circuit. 5. A time difference measuring device for measuring a time difference between two pulses when two pulses are sequentially input from the outside, the time difference between two pulses input from the outside. A time difference pulse generating circuit that outputs a time difference pulse with the pulse width as a pulse width, and a time difference pulse from the time difference pulse generation circuit as an input pulse. The pulse width of the pulse is reduced by a fixed pulse width while the rising edge delay time is longer than the falling edge delay time. Is provided corresponding to each of the pulse width reduction circuits, and determines whether or not the pulse width of the pulse output from the pulse width reduction circuit is equal to or greater than the minimum allowable width. The minimum allowable width pulse presence / absence detection circuit to be detected, and the pulse width of the time difference pulse input to the plurality of pulse width reduction circuits based on the minimum allowable width pulse presence / absence detection result from each of the minimum allowable width pulse presence / absence detection circuits. A pulse width calculation circuit for displaying and outputting the indicated data to the outside. 6. When two pulses are sequentially input from the outside, a time difference pulse between the two externally input pulses is set as a pulse width in order to measure a time difference between the two pulses. A time difference pulse generating circuit to output,
With the time difference pulse from the time difference pulse generation circuit as an input pulse, the pulse width of the pulse is set to a constant pulse width while being cascaded and delaying the pulse from the preceding stage with the same pulse width reduction characteristic. A plurality of pulse width reduction circuits that are output after the plurality of pulse width reduction circuits, and are provided corresponding to the respective pulse width reduction circuits, and the pulse width of the pulse output from the pulse width reduction circuit is equal to or greater than the minimum allowable width. A minimum allowable width pulse presence / absence detection circuit for detecting whether there is a pulse, and a time difference inputted to the plurality of pulse width reduction circuits based on the minimum allowable width pulse presence / absence detection results from each of the minimum allowable width pulse presence / absence detection circuits. A pulse width calculating circuit for externally displaying and outputting data indicating a pulse width of the pulse, wherein each of the pulse width reducing circuits includes a first MOS transistor. A converter, a second MOS inverter cascaded to the first MOS inverter, and a resistor inserted between the source side of the first MOS inverter and the ground, and having an overall resistance value externally via a gate electrode. A time difference measuring device comprising a series-parallel connection of N-type MOS transistors which can be set as desired. 7. When two pulses are sequentially input from the outside, a time difference pulse between the two externally input pulses is set as a pulse width to measure a time difference between the two pulses. A time difference pulse generating circuit to output,
With the time difference pulse from the time difference pulse generation circuit as an input pulse, the pulse width of the pulse is set to a constant pulse width while being cascaded and delaying the pulse from the preceding stage with the same pulse width reduction characteristic. A plurality of pulse width reduction circuits that are output after the plurality of pulse width reduction circuits, and are provided corresponding to the respective pulse width reduction circuits, and the pulse width of the pulse output from the pulse width reduction circuit is equal to or greater than the minimum allowable width. A minimum allowable width pulse presence / absence detection circuit for detecting whether there is a pulse, and a time difference inputted to the plurality of pulse width reduction circuits based on the minimum allowable width pulse presence / absence detection results from each of the minimum allowable width pulse presence / absence detection circuits. A pulse width calculating circuit for externally displaying and outputting data indicating a pulse width of a pulse, wherein each of said pulse width reducing circuits includes a pulse from a preceding stage. Are input in the state of being branched into two or more, and two or more logic gates having mutually different capacitive loads connected in a branched state to the gate output side; And a selector for selecting and outputting one of them under the selection control of the time difference measuring device. 8. When two pulses are sequentially input from the outside, the time difference between the two pulses is measured using the time difference between the two externally input pulses as a pulse width to measure the time difference between the two pulses. A time difference pulse generating circuit to output,
With the time difference pulse from the time difference pulse generation circuit as an input pulse, the pulse width of the pulse is set to a constant pulse width while being cascaded and delaying the pulse from the preceding stage with the same pulse width reduction characteristic. A plurality of pulse width reduction circuits that are output after the plurality of pulse width reduction circuits, and are provided corresponding to the respective pulse width reduction circuits, and the pulse width of the pulse output from the pulse width reduction circuit is equal to or greater than the minimum allowable width. A minimum allowable width pulse presence / absence detection circuit for detecting whether there is a pulse, and a time difference inputted to the plurality of pulse width reduction circuits based on the minimum allowable width pulse presence / absence detection results from each of the minimum allowable width pulse presence / absence detection circuits. A pulse width calculation circuit that externally displays and outputs data indicating a pulse width of a pulse, wherein each of the minimum allowable width pulse presence / absence detection circuits includes a pulse The pulse output from the reduction circuit as a set input, the pulse width being the time difference measuring device comprising configured as RS flip-flop is placed only in the set state when the minimum allowable width or more. 9. When two pulses are sequentially input from the outside, a time difference pulse between the two externally input pulses is set as a pulse width in order to measure a time difference between the two pulses. A time difference pulse generating circuit to output,
With the time difference pulse from the time difference pulse generation circuit as an input pulse, the pulse width of the pulse is set to a constant pulse width while being cascaded and delaying the pulse from the preceding stage with the same pulse width reduction characteristic. A plurality of pulse width reduction circuits that are output after the plurality of pulse width reduction circuits, and are provided corresponding to the respective pulse width reduction circuits, and the pulse width of the pulse output from the pulse width reduction circuit is equal to or greater than the minimum allowable width. A minimum allowable width pulse presence / absence detection circuit for detecting whether there is a pulse, and a time difference inputted to the plurality of pulse width reduction circuits based on the minimum allowable width pulse presence / absence detection results from each of the minimum allowable width pulse presence / absence detection circuits. A pulse width calculation circuit that externally displays and outputs data indicating a pulse width of a pulse, wherein each of the minimum allowable width pulse presence / absence detection circuits includes a pulse A diode bridge that is enabled by a pulse output from the reduction circuit, a capacitor that is in a charged state while the diode bridge is in a conductive state, and a comparator that compares a charged voltage from the capacitor with a determination reference voltage. A time difference measuring device configured as a main component. 10. When two pulses are sequentially input from the outside, in order to measure a time difference between the two pulses, a time difference pulse between the two externally input pulses is used as a pulse width. A time difference pulse generation circuit to be output, and a time difference pulse from the time difference pulse generation circuit as an input pulse, while being cascaded and having the same pulse width reduction characteristics, while delaying the pulse from the preceding stage. After reducing the pulse width of the pulse by a fixed pulse width, a plurality of pulse width reduction circuits for outputting to the rear, and a plurality of pulse width reduction circuits provided corresponding to the pulse width reduction circuits, A minimum allowable width pulse presence / absence detection circuit for detecting whether or not the pulse width is equal to or greater than the minimum allowable width; and a minimum allowable width pulse presence / absence detection signal from each of the minimum allowable width pulse presence / absence detection circuits. A pulse width calculation circuit that externally displays and outputs data indicating the pulse width of the time difference pulse input to the plurality of pulse width reduction circuits, wherein the time difference pulse generation circuit includes: An RS flip-flop which outputs first and second pulses input from outside as a set input and a reset input, and outputs a time difference pulse having a pulse width of a time difference between the first and second pulses as a Q output; Alternatively, while the data input is fixed at a high level, the first and second pulses input from the outside are clock input,
As a reset input, a D-type flip-flop that outputs a time difference pulse whose pulse width is a time difference between the first and second pulses as a Q output is a main component, and each of the pulse width reduction circuits includes a first MOS transistor. An inverter, a second MOS inverter cascaded to the first MOS inverter, and a resistor inserted between the source side of the first MOS inverter and the ground, and having a resistance as a whole from outside via a gate electrode. Each of the minimum allowable width pulse presence / absence detection circuits includes a pulse output from the pulse width reduction circuit as a set input. Time difference measurement configured as RS flip-flops that are set only when the pulse width of Road. 11. While various test signals are sequentially applied to the IC under test in each test cycle, a response signal to the applied test signal from the IC under test is different from an expected value previously created and stored separately. An IC test apparatus in which the comparison is sequentially performed under a predetermined determination timing, so that the quality of the function as an IC is determined based on the result of the comparison. Any one of a periodic clock, a test signal generation timing corresponding to various test signals generated based on the test periodic clock, and a determination timing of response signals to various applied test signals generated based on the test periodic clock. When any two clocks or timings are directly or indirectly input, the time difference between the clocks or the timings is measured. Generating a time difference pulse using a time difference between two externally input pulses as a pulse width so that a phase shift amount between the clocks or timings is adjusted as desired based on the measurement result. Circuit and the time difference pulse from the time difference pulse generation circuit as an input pulse, in a cascade-connected state, and with the same pulse width reduction characteristic, while delaying the pulse from the preceding stage, the pulse width of the pulse is changed. A plurality of pulse width reducing circuits for reducing the fixed pulse width and outputting the pulse width at the rear, and provided corresponding to each of the pulse width reducing circuits, wherein the pulse width of the pulse output from the pulse width reducing circuit is minimum allowable A minimum allowable width pulse presence / absence detection circuit for detecting whether or not the pulse width is equal to or greater than a minimum allowable width pulse presence / absence detection circuit from each of the minimum allowable width pulse presence / absence detection circuits; The basis, the pulse width calculating circuit and, IC tester is a time difference measuring device comprising at least provided comprising displaying output data to an external indicating a pulse width of the time difference pulses input to the plurality of pulse width reduction circuit.