JP3152552B2 - Liquid crystal display module signal wiring structure - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal wiring structure for a liquid crystal display module, and more particularly, to a signal wiring for supplying a signal to the liquid crystal display module and a driver IC electrically connected to the signal wiring. The present invention relates to a signal wiring structure of a liquid crystal display module having an improved signal wiring structure between them.

[0002]

2. Description of the Related Art In recent years, liquid crystal display devices have been improved in definition. As the definition becomes higher, the mounting density of signal wirings, driver ICs, and the like mounted on a circuit board is increasing, so that the influence between each mounting member cannot be ignored.

A signal wiring structure of a conventional liquid crystal display module will be described with reference to FIGS. FIG. 7 is a plan view of a signal wiring structure of the conventional liquid crystal display module, and FIG. 8 is an enlarged plan view showing a region surrounded by a dashed line X in FIG. FIG. 10 is a cross-sectional view taken along the solid line A of FIG. 8 at the position where the sample-and-hold capacitor is provided near the end of the driver IC, and FIG. 9 is a portion taken along the solid line B of FIG. FIG. 4 is a cross-sectional view of a position where an output terminal is provided near an end of a driver IC.

As shown in FIG. 7, on a transparent insulating substrate 1 such as a glass substrate or the like, for example, an output signal wiring 2 made of Au / Cr and electrically connected to a liquid crystal display module and an input signal The wiring 3 is formed. A driving driver IC 4 for supplying a signal to the liquid crystal display module is arranged above the insulating substrate 1.

The driver IC 4 includes a plurality of sample-and-hold capacitor rows 5 in which a plurality of sample-and-hold capacitors are arranged. Output terminals 6 that are electrically connected to the plurality of output signal wirings 2 are drawn out from the lower surface of the driver IC 4.

Referring to FIG. 8, the position where the sample-and-hold capacitor row 5 and the output terminal are formed will be clarified. In FIG. 8, numbers 1 to 45 are assigned to the plurality of output terminals 6 of the driver IC 4, respectively, and the output terminals are respectively drawn downward to the positions indicated by the above numbers in the drawing. As is clear from FIG. 8, a plurality of output terminals numbered 1 to 15, 16 to 30, and 31 to 45 are arranged respectively.

A sample-and-hold capacitor array 5 is arranged on the side of the output terminal array in parallel with the output terminal array. The electrical connection structure between each output terminal and the output signal wiring 2 will be described with reference to FIG. A first insulating film 7 made of an insulating material such as SiN ₄ is formed so as to cover the output signal wiring 2 formed on the transparent insulating substrate 1. The first insulating film 7 is formed at one end of the output signal wiring 2 connected to the output terminal 6 so as to expose the output signal wiring 2, thereby forming a contact hole 8. Each output terminal 6 and output signal wiring 2 are formed by conductive paste 9 filled in contact hole 8.
And are electrically connected.

In FIG. 9, reference numeral 10 denotes an insulating resin made of epoxy or acrylic. As is clear from FIG. 10, in the portion where the sample-and-hold capacitor row 5 is provided, the plurality of sample-and-hold capacitors 11 are configured to be covered with an insulating film 12 made of polyimide or the like. And are built in the driver IC 4.

On the other hand, below the portion where the sample-and-hold capacitor row 5 is provided, the above-described first insulating film 7 is formed so as to cover the output signal wiring 2.
The space between the insulating film 7 and the bottom surface of the sample hold capacitor of the driver IC 4 is filled with the second insulating resin 10.

Therefore, between the plurality of sample and hold capacitors 11 and the output signal wiring 2, the first insulating film 7,
The insulating layer is formed by the second insulating resin 10 and the third insulating resin 12.

The driver IC 4 is adhered to the transparent insulating substrate 1 by an insulating resin 10 via an insulating film 7, and the insulating resin 10 ensures electrical insulation between the output terminals 6. Performs functions.

As shown in FIGS. 7 and 8, a plurality of output signal wirings 2 obliquely intersect with the direction in which the sample and hold capacitor row 5 extends from the end connected to the output terminal 6. And extended to the liquid crystal display module side.

The reason why the output signal wiring 2 is arranged obliquely from the output terminal 6 as described above is to make the length of the output signal wiring as short as possible, thereby reducing the wiring resistance.

[0014]

In the above-mentioned liquid crystal display device using the wiring structure of the conventional liquid crystal display module, when an image is actually displayed, line-shaped luminance unevenness sometimes occurs. This will be described with reference to FIG.

The horizontal axis in FIG. 11 indicates the signal wiring number from the left end of the video signal column of the liquid crystal display module, and corresponds to the number given to the output terminal of the driver IC described above. The vertical axis indicates the output voltage level of each signal wiring.

While the output voltage level of each signal line must be uniform, the output voltage level of some output signal lines 2 is very high, as is apparent from FIG. That is, the signal wiring number 30n
+1 and 30n + 30 (where n is 0, 1, 2,
In the signal wiring of 3), the wiring numbers in FIG.
In the signal wiring of No. 0, 31, No. 60 and No. 61,
The output voltage was abnormally high. Furthermore, signal wiring numbers 30n + 2 and 30n + 29 (where n is 0,
In the signal wirings of 1, 2, 3) and the signal wiring of FIG. 11, the voltage of the signal supplied to the driver IC 4 is abnormally high even in the signal wirings of No. 2, 29, 32, 59 and 62. It turned out that it was.

Here, the output voltage level on the vertical axis is relative to the level of the ground potential. In general, a liquid crystal display module is used to prevent deterioration due to polarization of liquid crystal.
AC drive is required. At this time, the center voltage level is set near the center of the output range in consideration of the driving capability of the driver IC. Therefore, the voltage applied to the liquid crystal is represented by a potential difference from the central voltage level (generally referred to as a video center voltage).

Therefore, when abnormally high portions of the low-side signal voltage viewed from the ground potential level are substantially at equal intervals as described above, that is, when the voltage applied to the liquid crystal is low, the display method is the normally white method. In some cases, areas having high luminance in the vertical direction at equal intervals are generated in the liquid crystal display module.

As a matter of course, the normally black method has a drawback in that, unlike the normally white method, areas having low luminance in the vertical direction at equal intervals are generated in the image of the liquid crystal display module.

An object of the present invention is to solve the above-described drawbacks of the signal wiring structure in the conventional liquid crystal display module and to effectively prevent the occurrence of linear luminance unevenness appearing at equal intervals in the vertical direction. To provide a signal wiring structure.

[0021]

A wiring structure of a liquid crystal display module according to the present invention has a transparent insulating substrate and a plurality of signal wirings formed on the transparent insulating substrate and supplying signals to the liquid crystal module. And an insulator layer disposed on the plurality of signal wirings, a plurality of output terminals disposed on the insulating layer, and electrically connected to the plurality of signal wirings, and the inside of each of the plurality of output terminals. A driver IC having a plurality of sample and hold capacitors corresponding to signal wiring, wherein the plurality of sample and hold capacitors are arranged as at least one or more sample and hold capacitor rows in which a plurality of sample and hold capacitors are arranged; And a lower region of the driver IC such that the plurality of signal lines intersect the sample-and-hold capacitor row when viewed from above. In the signal wiring structure of the liquid crystal display module having a structure drawn out from the liquid crystal display module, a height position between a bottom surface of the driver IC and a signal wiring portion below the driver IC, and at least the sample hold capacitor row A signal wiring structure of a liquid crystal display module, characterized in that a conductive film is arranged in a region overlapping with the above.

Preferably, the conductive film is electrically connected to a constant reference potential. The conductive film may be disposed in an insulator layer disposed between the transparent insulating substrate and the driver IC, and is formed directly on the bottom surface of the driver IC as described in claim 4. You may. That is, the conductive film is formed by the driver I
It can be placed at any position between C and the transparent insulating substrate as long as it is electrically insulated from the portion through which signals pass.

[0023]

In the signal wiring structure of the conventional liquid crystal display module, luminance unevenness occurs at regular intervals.
In the planar structure shown in FIG. 8, the plurality of output signal wirings 2 intersect with the sample-and-hold capacitor row 5, and the output signal wirings are provided below the sample-and-hold capacitor row 5 near the end of the sample-and-hold capacitor row 5. It is considered that there is a non-existent portion of No. 2.

That is, a plurality of output signal wirings 2 cross the lower part of the sample-and-hold capacitor row 5, and capacitive coupling occurs with the upper-side sample-and-hold capacitor 11. However, the end side of the sample-and-hold capacitor row 5, that is, the numbers 1, 30, 3 in FIG.
There is no output signal wiring below the sample and hold capacitor beside the output terminal 6 to which 1 is assigned.

Therefore, in the outputs of Nos. 1, 2, 29 to 32, no or only a small amount of capacitive coupling occurs between the output signal wiring and the sample-and-hold capacitor, and the output voltage level is normal. . On the other hand, the output terminals of other numbers 3 to 28 have other output signal wirings below the sample and hold capacitors corresponding to the respective outputs, so that capacitive coupling occurs and the voltage applied to the liquid crystal is Is the original output voltage level (V)
Is added to the voltage (ΔV) generated by the capacitive coupling.

That is, in the normally white system, the output terminals of the numbers 1, 2, 29 to 32 having no capacitive coupling are at the original voltage level (V) and have high luminance. It is considered that the voltages (ΔV) generated by the capacitive coupling are added to the output terminals 3 to 28, the voltage applied to the liquid crystal increases (V + ΔV), and the luminance decreases.

On the other hand, in the signal wiring structure of the present invention, at least a region overlapping the sample-and-hold capacitor row is provided at a height position between the bottom surface of the driver IC and an output signal wiring portion below the driver IC. A conductive film is provided. Therefore, the conductive film eliminates the interaction between the row of sample-and-hold capacitors and the lower signal wiring, thereby preventing the above-mentioned capacitive coupling that has an adverse effect. Therefore, signals supplied to the liquid crystal display module can be made uniform among all output signal wirings. Further, since the increase (ΔV) of the output voltage due to the capacitive coupling is suppressed, the voltage applied to the liquid crystal decreases, and the power consumption can be reduced.

According to the second aspect of the present invention, since the conductive film is connected to a fixed reference potential such as a ground potential, the interaction between the conductive film and the output signal wiring is more effectively eliminated. can do.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be clarified by describing embodiments with reference to the drawings.

FIG. 1 is a plan view of a signal wiring structure of a liquid crystal display module according to an embodiment of the present invention, and FIG. 2 is an enlarged plan view of a region X surrounded by a dashed line in FIG. 4 is a cross-sectional view taken along the solid line A in FIG. 2 at the position where the sample-and-hold capacitor is provided near the end of the driver IC, and FIG. 3 is a portion along the solid line B in FIG. FIG.

Referring to FIG. 1, a large number of output signal wirings 22 are provided on a transparent insulating substrate 21 such as a glass substrate.
The input signal wiring 23 is formed. Output signal wiring 2
2 and the input signal wiring 23 are made of a conductor such as Au / Cr, for example.

A driver IC 24 is mounted above the transparent insulating substrate 21. Although not clearly shown in FIG. 1, a plurality of sample-and-hold capacitor rows 25 in which a plurality of sample-and-hold capacitors are arranged are arranged in the driver IC 24.

Further, a plurality of output terminals (FIG. 3) are drawn downward from the bottom surface of the driver IC 24. The plurality of output terminals 26 are arranged so as to extend in parallel with the sample-and-hold capacitor row 25 as schematically shown in FIG. That is, as shown by the numbers 1 to 15, 16 to 30, 31 to 45 in FIG.
The 15 output terminals are arranged at predetermined intervals so as to form a line, and the output terminals are arranged. This output terminal 2
In parallel with the direction in which 6 are aligned, the above-mentioned sample-and-hold capacitor rows 25 are arranged beside each output terminal row. The two sample and hold capacitors 31 in the sample and hold capacitor row 25 correspond to one output signal line 22. Further, as shown in FIG. 2, one end of each of the plurality of output signal wirings 22 is electrically connected to a corresponding output terminal.

Referring to FIGS. 3 and 4, a connection structure between the output signal wiring 22 and the output terminal 26 will be described. On the transparent insulating substrate 21, the output signal wiring 22 made of Au / Cr or ITO having a thickness of about 1000 to 2000
Is formed, but a first insulating film 27 is formed so as to cover the output signal wiring 22. The insulating film 27 is made of S
made of insulating material such as iN _x, as shown in FIG. 3, the output terminal 26 and the portion to be electrically connected to the output signal line 22, does not cover the output signal line 22. That is, a portion of the output signal wiring 22 that is not covered with the insulating film 27 is formed on one end side of the output signal wiring 22, thereby forming a contact hole 28.

In the contact hole 28, the output signal wiring 22 and the output terminal 26
And are electrically connected. Further, the second insulating resin 30 made of a resin such as epoxy or acrylic is filled between the insulating film 27 and the third insulating resin 33 on the bottom surface of the driver IC 24, for example, the insulating resin 33 made of polyimide. Have been. The driver IC 24 and the first insulating film 27, and eventually the transparent insulating substrate 21, are fixed by the second insulating resin 30.

Therefore, the first insulating film 27, the second insulating resin 30, and the third insulating resin 33 are provided between the plurality of sample and hold capacitors 31 and the output signal wiring 22.
This forms an insulating layer.

In place of the conductive paste 29,
An output terminal 26 may be electrically connected to the output signal wiring 22 by using an anisotropic conductive rubber having conductivity only in the thickness direction. Alternatively, at the time of connection between the output terminal 26 and the output signal wiring 22, another appropriate conductive adhesive or the like can be used.

The structure up to this point is the same as the signal wiring structure of the conventional liquid crystal display module described with reference to FIGS. The feature of this embodiment is that a conductive film 32 is provided between the insulating film 27 and the insulating resin 30 constituting the insulator layer.
Is located. The conductive film 32 is made of, for example, A
1 or an appropriate metal or alloy,
The surface of the insulating film may be covered with a conductive material.

The region where the conductive film 32 is formed is
As shown in FIG.
Is an area including at least an area projected downward of. This is to prevent capacitive coupling between the sample and hold capacitors of the sample and hold capacitor row 25 and the lower output signal wiring 22. Therefore, the conductive film 32
Are located above the plurality of output signal wirings 22 connected to the output terminals numbered 30 to 45 in FIG.
25 may be formed to have a size including a region projected downward, or the output signal wiring 22 or the driver IC 2
4 may be formed in an area wider than the area shown in FIG.

In the present embodiment, the conductive film 32 is connected to a ground potential as a reference voltage. By connecting the conductive film 32 to the ground potential, the capacitive coupling between the output signal wiring 22 and the output terminal 26 can be more effectively cut off.

When the conductive film 32 is connected to the ground potential, the end of the conductive film 32 may be electrically connected to a terminal of the driver IC 24 connected to the ground potential, or the transparent insulating substrate 21 It may be performed by electrically connecting to an electrode pattern connected to a ground potential formed thereon.

The conductive film 32 is formed by forming a metal or alloy such as Al on the upper surface after forming the output signal wiring 22 and the insulating film 27 on the transparent insulating substrate 21.
It can be performed by forming a film by a method such as vapor deposition or the like, and patterning by an appropriate method such as photolithography or etching.

Next, a description will be given of the fact that in the signal wiring structure of the liquid crystal display module of the present embodiment, it is possible to prevent uneven brightness which appears in an image at regular intervals in a conventional technique. FIG.
FIG. 11 is a diagram showing the effect of a sample-and-hold capacitor on an image when the signal wiring structure of the liquid crystal display module of this embodiment is used.
FIG. Also in FIG. 5, output signal wiring 22 corresponding to one row of sample and hold capacitor rows 25 is shown.
Shows the characteristics when the number is 15 (that is, the case shown in FIG. 1).

In FIG. 5, the horizontal axis is the number of the signal wiring from the left end of the video signal column of the liquid crystal display module (see FIG. 2).
The vertical axis indicates the output voltage level of each signal wiring as viewed from the ground potential level.

As is apparent from FIG. 5, in the signal wiring structure of the liquid crystal display module according to the present embodiment, the output voltages of all the output signal wirings 22 are substantially uniform. This is because the conductive film 32 is formed in a region including the region where the sample-and-hold capacitor row 25 is projected downward, and therefore, the capacitive coupling between the output signal wiring 22 and the sample-and-hold capacitor in the sample-and-hold capacitor 25 above. It is considered that adverse effects were prevented. That is, in the conventional technique shown in FIG. 8, the output signal wiring 2 is not located below the sample-and-hold capacitor arranged near the end of the sample-and-hold capacitor row 5, so that the capacitive coupling is not formed near the end. And the original output voltage level. On the other hand, capacitive coupling has occurred between the sample and hold capacitor and the output signal wiring except at the end. Therefore, as shown in FIG. 11, there was a difference in signal voltage between the output signal wirings of about every 30th.

On the other hand, in this embodiment, since the conductive film 32 is interposed, the sample and hold capacitors 31 in the upper sample and hold capacitor row 25 are
Capacitive coupling with the lower output signal wiring 22 is reliably prevented. Therefore, all output signal wirings 22 are arranged in an equivalent state, and it is considered that variations in output voltage levels are significantly reduced. That is, since the potentials of the plurality of output signal lines are equalized, the signal voltage is uniformly supplied to the liquid crystal display module.

Therefore, the voltage applied to the liquid crystal is reduced by preventing the capacitive coupling as in the present embodiment with respect to the luminance difference at equal intervals in the vertical direction, which has conventionally occurred in the normally white method. And a uniform image can be obtained by aligning the images with high areas.

Similarly, in the normally black method, contrary to the normally white method, uniform images can be obtained by adjusting the brightness to the lower one extending in the vertical direction at equal intervals. Further, since the voltage applied to the liquid crystal is reduced, the power consumption of the liquid crystal display module can be reduced.

In the above embodiment, the conductive film 32 is disposed between the insulating film 27 and the insulating resin 30 constituting the insulating layer, that is, in the insulating layer. 32 is the bottom surface of the driver IC 24 and the transparent insulating substrate 21
If it is between the upper output signal wiring 22 and the upper output signal wiring 22,
2 and the output terminal 26 can be formed at any height position as long as they are electrically insulated. That is, it may be embedded in the insulating resin 30.

As shown in FIG. 6, the driver IC 2
4, the conductive film 3 on the third insulating resin 33.
2 may be formed in advance. Further, in the above embodiment,
When a driver IC 24 in which a plurality of output terminals are arranged so that 15 output terminals form one row is used, and the number of output signal wirings corresponding to one row of sample-and-hold capacitors is 15 However, these numbers are not particularly limited. Therefore, the general formula 30n + 1,3 representing the signal wiring number described above.
0n + 30, 30n + 2, and 30n + 29 are merely examples, and the value of n in the above equation also varies according to the number of signal wirings.
n is an integer of 0 or more.

In the above embodiment, since a plurality of signal wirings are extended so as to intersect the sample-and-hold capacitor row in an oblique direction, the arrangement of the conductive film effectively prevents the occurrence of luminance unevenness. However, the present invention can also be applied to a structure in which the signal wiring is drawn out below all the sample and hold capacitors so as to be orthogonal to the sample and hold capacitor row, and the occurrence of luminance unevenness is also reduced. Can be suppressed.

[0052]

According to the present invention, a signal wiring formed on a transparent insulating substrate and supplying an output signal from a driver IC to a liquid crystal display module, a sample hold capacitor provided in the driver IC, Since the conductive film is interposed between them, the interaction between the signal wiring for supplying the output signal from the driver IC to the liquid crystal display module and the sample and hold capacitor, that is, the capacitive coupling is effectively prevented. You. Therefore, the voltage level supplied from each signal wiring to the liquid crystal display module can be made uniform, thereby ensuring the occurrence of line-shaped uneven brightness at regular intervals due to a partial abnormality of the supplied signal voltage. This can be prevented.

Further, by preventing capacitive coupling,
Since an increase in output voltage due to capacitive coupling is also prevented, power consumption of the liquid crystal display module can be reduced.

[Brief description of the drawings]

FIG. 1 is a plan view showing a wiring structure of a liquid crystal display module according to one embodiment of the present invention.

FIG. 2 is an enlarged plan view showing a part of the wiring structure shown in FIG. 1;

FIG. 3 is a cross-sectional view illustrating a wiring structure of the liquid crystal display module according to one embodiment of the present invention, and is an enlarged cross-sectional view illustrating a portion taken along line B in FIG. 2;

4 is a cross-sectional view of a wiring structure of the liquid crystal display module according to one embodiment of the present invention, and is an enlarged cross-sectional view of a portion along line A in FIG.

FIG. 5 is a view for explaining characteristics of the liquid crystal display module according to the embodiment depending on the wiring structure.

FIG. 6 is a cross-sectional view illustrating a modified example in which a conductive film is provided on the bottom surface of a driver IC.

FIG. 7 is a plan view showing a wiring structure of a conventional liquid crystal display module.

FIG. 8 is an enlarged plan view showing a wiring structure of a conventional liquid crystal display module.

9 is a cross-sectional view of a wiring structure of a conventional liquid crystal display module, and is a cross-sectional view along line B in FIG.

FIG. 10 is a cross-sectional view of a wiring structure of a conventional liquid crystal display module, and is a cross-sectional view of a portion along line A in FIG.

FIG. 11 is a view for explaining characteristics of a wiring structure of a conventional liquid crystal display module.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 21 ... Transparent insulating substrate 22 ... Output signal wiring 24 ... Driver IC 25 ... Sample hold capacitor row 26 ... Driver IC output terminal 27 ... First insulating film constituting an insulator layer 28 ... Contact hole 29 ... Conductive paste 30 ... Second insulating resin constituting the insulating layer 31. Sample hold capacitor 32. Conductive film 33. Third insulating resin forming the insulating layer

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G02F 1/1345 G02F 1/133 505 G09G 3/36

Claims (4)

(57) [Claims] 1. A transparent insulating substrate; a plurality of signal wirings formed on the transparent insulating substrate and supplying signals to a liquid crystal module; and an insulator layer disposed on the plurality of signal wirings. And a driver IC disposed on the insulator layer and having a plurality of output terminals electrically connected to the plurality of signal wirings and a plurality of sample-and-hold capacitors corresponding to each of the signal wirings inside. A plurality of sample-and-hold capacitors, wherein the plurality of sample-and-hold capacitors are arranged and arranged as at least one or more sample-and-hold capacitor rows, and the plurality of signal wirings are sample-and-hold capacitors when viewed from above. Driver I to cross the column
A signal wiring structure of a liquid crystal display module having a structure drawn out from a region below C, wherein the signal wiring structure is located at a height position between a bottom surface of the driver IC and a signal wiring portion below the driver IC, and A signal wiring structure for a liquid crystal display module, wherein a conductive film is arranged in a region overlapping a row of sample-and-hold capacitors. 2. The signal wiring structure of a liquid crystal display module according to claim 1, wherein said conductive film is connected to a reference potential. 3. The signal wiring structure of a liquid crystal display module according to claim 1, wherein said conductive film is disposed in said insulator layer. 4. The signal wiring structure of a liquid crystal display module according to claim 1, wherein said conductive film is formed on a bottom surface of said driver IC while being electrically insulated from said output terminal.