JP3152229B2 - Variable capacitance device and crystal oscillator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable capacitor formed on a semiconductor integrated circuit, and more particularly to a variable capacitor for adjusting the frequency of a high-precision temperature-compensated crystal oscillation circuit.

[0002]

2. Description of the Related Art A conventional variable capacitance capacitor is one that converts an output from a memory into a serial-parallel converter as described in Japanese Patent Application Laid-Open No. 62-76801, and switches the capacitor array by giving a larger time constant to the output by a charge / discharge circuit. Met.
This aims to improve the purity (C / N ratio) of the oscillator output.

[0003]

However, in the above-mentioned prior art, it is difficult to form a charge / discharge circuit having a large time constant on a semiconductor integrated circuit, and each capacitance of a capacitor array is reduced for high accuracy. FE
The parasitic capacitance of the T switch cannot be ignored with respect to the capacitance value of the capacitor array, and the capacitance ratio when the capacitor array is turned on / off has been reduced. As a result, there is a problem that the oscillation frequency cannot be adjusted over a wide temperature range. Further, if the number of the capacitor arrays is increased, the correction memory capacity is correspondingly increased, resulting in a problem that the cost is increased. Therefore, the present invention solves such a problem. It is an object of the present invention to reduce the switching noise of the capacitor array, increase the on / off ratio of the capacitance, and perform fine adjustment with a small memory capacity. An object of the present invention is to provide a variable capacitor. Another object is to easily monitor the operation of the control circuit for the variable capacitor.

[0004]

A variable capacitance device according to the present invention comprises a capacitor group having a plurality of capacitors each having one electrode electrically connected in common, and the other electrode of each of the plurality of capacitors. A variable element having a switch element connected between a power supply and control means for controlling a conduction state of the plurality of switch elements, wherein a total capacitance is determined by a sum of capacitors selected by the switch elements; The apparatus outputs a gate voltage of a selected one of the switch elements corresponding to the plurality of capacitors to an external monitor terminal. The gate voltage of the switch element to be output to the external monitor is output-controlled by a monitor control signal (TEST) input from an external terminal. Further, a crystal oscillator according to the present invention includes the variable capacitance device described above.

[0005]

According to the above configuration of the present invention, the potential applied to the gate of one selected switch element can be monitored from the external monitor terminal for the switch elements corresponding to the plurality of capacitors.

[0006]

FIG. 1 is a diagram showing an example in which a variable capacitor according to the present invention is used as a drain capacitor of a crystal oscillation circuit. FIG. 4 shows a specific embodiment of the main part of FIG. 1, and the same components are denoted by the same reference numerals. Figure 4 shows a complementary MOS transistor (CMOS)
Although it is illustrated on the premise of a semiconductor integrated circuit using, the present invention is not limited to this. The major difference of the present invention from the prior art is that the capacitor switch FE
The point is that a plurality of potentials are applied to the gate of the T switch via a D / A converter. This will be described with reference to FIG.

As a digital temperature-compensated crystal oscillator, it is necessary to obtain digitized temperature information from the output of the temperature sensor 1 via an A / D converter 2. The upper bit 31 of the output of the A / D converter is input as an address signal of the storage circuit 3 in which the temperature compensation information is stored, and the lower bit 32 is input via the inverting circuit 6 to the D / A converter 7.
Is input to The output 33 of the storage circuit 3 is provided to the linear converter 5 via the (BCD) decoder 4. In order to reduce the memory capacity, the storage circuit 3 stores correction data at each correction temperature in a binary code. One of the outputs of the decoder 4 to which this is input is one in which the output is in an active state. Incidentally, the decoder 4 and the linear converter 5 can be omitted if the output 33 is equivalent to the output of the decoder 4 or the linear converter in FIG. If the FET switch is directly turned on / off by the output of the decoder 4, the capacitor array needs to take a weighted capacitance value. Therefore, in the present invention, even if the linear conversion circuit is provided and the respective capacitance values of the capacitor array are equal,
Weight control can be performed. By doing so, the total capacitance value of the capacitor array can be minimized, the switching noise can be reduced to a lower level, and the degree of freedom of correction can be increased.

The output of the D / A converter 7 is for interpolating the intermediate value to be corrected by the output of the linear converter via the switch control circuit 8. In the present invention, when performing intermediate interpolation, FE
The on-resistance of the T switch is changed, and as a result, the CR time constant between the drain wiring 28 and GND is changed.

In FIG. 4, signals D ₀ , D ₁ , D ₂ , signals d ₀ ,
d ₁ and the signal D / u correspond to the outputs 33, 32 and 34 of FIG. The number of bits of the outputs 33 and 32 can be increased or decreased. In the figure, the crystal resonator 25 is connected between the gate and the drain of the oscillation amplifier 27. Further, the fixed wiring 23 and the capacitor array 20, 2
1 and 22 are connected, and the connection of the capacitor array to GND is turned on / off by a signal from the switch control circuit, thereby varying the capacitance value. The switching of the capacitor array is performed, for example, by combining the output of the decoder 4 with a 3-bit input and the output of the D / A converter 7. The output of the decoder 4 is input to the linear conversion circuit 5 and is converted according to the physical arrangement of the capacitor arrays 10 to 12 so that the boundary where the capacitor array is turned on / off is always one. That according to the state of the input D ₀ to D _2,
One of the outputs of the decoder 4 becomes "L", and the other becomes "H". When this is input to the linear converter 5, in the figure, with the capacitor array corresponding to where the output of the decoder 4 is "L" as a boundary, the capacitor array and the capacitor array on the left side thereof are turned on ( The capacitor array on the right is turned off.

As described above, the decoder 4 and the A / D converter 2
Is supplied from the temperature sensor circuit. That is, the output from the crystal unit or the semiconductor sensor is converted from an analog amount to a digital amount via a voltage-frequency converter or an A / D converter. A storage circuit (ROM) 3 in which upper bits of the converted digital information are stored with temperature correction information.
And the lower bit 32 is set to D / A
It is given as an input to the converter 7. This lower bit 32 is
Since the temperature characteristic of the crystal resonator draws a quadratic curve or a cubic curve, it is necessary to invert the order of the lower bits in order to perform a smooth correction at this inflection point. In order to realize this, the signals d ₀ and d ₁ are applied to a D / A converter 7 via an inversion circuit 6. The inversion control signal D / u of the inversion circuit 6 composed of the EX-ORs 61 and 62 is given as a result of calculating the output of the storage circuit 3 or the storage circuit.

In FIG. 4, the control circuit of the capacitor array is configured as a regular circuit unit as indicated by broken lines A, B and C. Hereinafter, the unit B will be described. The switch control circuit including the gates 84, 85, 86 and the transfer gates 184, 185, 186 receives the output of the linear control circuit including the decoder 42 and the gates 53, 54, and includes an N-channel MOS transistor. The gate potential of the FET switch 11 is controlled. The switch control circuit includes an off potential (GND) and an on potential (V _DD ) and an intermediate potential V _EE2 between the off potential and the on potential.
, And three gates for controlling the transfer and its gate control circuit. When the output of the decoder 42 is “L” (active), the intermediate potential V _EE2 , which is the output of the D / A converter, is transmitted. In the array A on the left side, the on-potential V _DD is transferred by the transfer gate 181. , Right array
In C ′, the transfer gate 188 transmits the off potential GND. Accordingly, in the present invention, the FET switches 10, 1
Since 1 and 12 function as variable resistors, the equivalent circuit of the capacitor array is as shown in FIG. In the figure
C _X is the parasitic capacitance, R _S is the resistance of the FET switch, C _A is the array capacitor, and the equivalent capacitance C viewed from the drain 28 is

[0012]

(Equation 1)

And the gate potential Vg of the FET switch
Against

[0014]

(Equation 2)

Therefore, there is a relationship shown in FIG. It should be noted here that the equivalent capacitance C changes abruptly near the threshold voltage V _{TH of the} FET switch. Therefore, if the FET switch is controlled by a simple time constant circuit, the equivalent capacitance C changes abruptly, and the potential of the drain 28 jumps, so that switching noise is generated at the output 28 due to capacitor coupling. Therefore, in the present invention, the gate voltage in the region where the equivalent capacitance changes abruptly as shown in FIG. 3 is generated using the D / A converter 7 in FIG. 4, the FET switch transistor same channel length MOS Bok transistor 161 have the same conductivity type and is constant current operation in the threshold voltage near uses that gate voltage as [nu ₀ potential slightly higher potential from [nu ₀ [nu ₁ , Ν ₂ are passive resistors 162 such as diffusion resistors or polysilicon resistors,
163 and a MOS resistor 164. The maximum potential ν ₃ is set to a potential close to the power supply V _DD . Potential ν _{0 to} ν ₃
Is selected by analog switches 171 to 178,
The intermediate potentials V _EE1 and V _EE2 are provided to the transfer gate. Since the potentials ν _{0 to} ν ₃ are generated through high resistance, they are given to the gate of the FET switch with a large time constant, and change the equivalent capacitance more smoothly. Meanwhile when the switching of the capacitor array is shifted next to the array, since the V _EE voltage changes greatly [nu ₀ from [nu ₃ or [nu ₃ from [nu _0, momentarily through the transfer gate 183,186,189 The gate potential of the FET switch may fluctuate significantly. In the present invention, in order to prevent this, two systems provided the V _EE1 and V _EE2 as the intermediate potential, the transfer gate 183,186,189
The logic of the decoder 71 is configured so that the potentials of ν ₀ and ν ₃ are changed when is turned off.

Incidentally, such a test of the switching circuit of the capacitor array cannot be sufficiently tested by a general LSI tester. Therefore, in the present invention, the transfer gates 91 to 96 which are turned on / off by the output of the linear control circuit and the test signal TEST are provided in each array, and the monitor terminal MO
To monitor the gate potential of the FET switch. As for the gate potential of the FET switch, only the unit in which the output of the decoder 4 is active is selectively output to the MO terminal. This makes it possible to reliably test the operation of the circuit that controls the FET switch, so that a highly reliable capacitor array can be obtained.

In the above description, the example in which the capacitor array is provided on the output side of the oscillation amplifier has been described, but it goes without saying that the capacitor array may be provided on the input side. Furthermore, the present invention is not limited to application to an oscillation circuit, but can be widely applied to an application using a time constant using a capacitor such as a filter or a tuning device, and an electronic circuit that needs to finely adjust a capacitor capacity in a programmable manner. is there.

[0018]

As described above, according to the present invention, the potential applied to the gate of one selected switch element can be monitored from the external monitor terminal, and the control circuit for the variable capacitor can be easily realized. You can know the operation of.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a variable capacitor according to the present invention.

FIG. 2 is a diagram showing an equivalent circuit of a capacitor array unit.

FIG. 3 is a diagram showing a change in equivalent capacitance with respect to a gate potential of a switch element.

FIG. 4 is a diagram showing a specific circuit example of FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Temperature sensor 2 ... A / D converter 3 ... Storage circuit 4 ... Decoder 5 ... Linear converter 6 ... Inverting circuit 7 ... D / A converter 8. ..Switch control circuits 10, 11, 12 ... switch element groups 20, 21, 22 ... capacitor groups

Continuation of the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H03B 5/30-5/42 H01G 7/00 H01L 21/00 H01L 27/00

Claims (3)

(57) [Claims] A capacitor group having a plurality of capacitors each having one electrode electrically connected in common; and a switch element connected between a power supply and the other electrode of each of the plurality of capacitors. Control means for controlling the conduction state of the plurality of switch elements, wherein the total capacitance is determined by the sum of the capacitors selected by the switch elements, corresponding to the plurality of capacitors A variable capacitance device for outputting a gate voltage of a selected one of the switch elements to an external monitor terminal. 2. The variable capacitor according to claim 1, wherein a gate voltage of the switch element to be output to the external monitor is output controlled by a monitor control signal (TEST) input from an external terminal. apparatus. 3. A crystal oscillator comprising the variable capacitance device according to claim 1.