JP3149463B2 - Effect adding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an effect adding device, and more particularly, to an effect adding device that changes an input sound signal into a metallic sound using a ring modulator.

[0002]

2. Description of the Related Art In a device for handling sounds such as an electronic stringed musical instrument (for example, a guitar), an electronic musical instrument such as an electronic organ and a synthesizer, and a musical sound output device for processing and outputting a sound generated by another sound source. An important issue is how to produce rich musical tones. As a means for producing such a rich sound, conventionally, an effect adding process of including many harmonic components in an electric signal of a sound generated by a sound source or the like has been performed. Particularly, an effect adding process for changing an input sound signal metallically is performed.
A so-called ring modulator has conventionally been used in such a metallically changing effect adding circuit. This ring modulator has two inputs and one output, multiplies the voltage applied to the inputs,
The result of the multiplication is output as an output signal. This ring
In an effect adding circuit using a modulator, an acoustic signal output from a musical instrument is input to one of the inputs, and an oscillation signal of a predetermined frequency output from an oscillator is input to the other input. The ring modulator multiplies the input acoustic signal by the oscillation signal and outputs the multiplied signal as an output signal.
The output signal that is the multiplied signal has, as its frequency, the sum and difference frequencies of the two input signals, and does not output the frequency of the original sound. In this case, the frequency of the sum and difference of the input signal, which is the frequency of the output signal, rarely has an overtone relationship with the frequency of the original sound, and thus the pitch obtained is dissonant. Therefore, the timbre of the input audio signal can be metallically changed, and irregular overtones can be obtained.

[0003]

However, in such a conventional effect adding circuit, the ring modulator used in the effect adding circuit uses, as an output signal, a signal of the sum of the frequencies of two input signals. Since only the difference signal is output, the frequency of the output signal has no harmonic relationship with the frequency of the input acoustic signal, and the frequency of the original sound cannot be recognized. Therefore, when a picking sound from an electronic stringed musical instrument or the like is input as an input acoustic signal, it is not possible to know which string was picked, so that a so-called picking feeling cannot be obtained, and the usability of the electronic stringed instrument or the like is poor. Was. That is, the string vibration caused by picking is now sinα, and the oscillation signal to be multiplied is sinβ
Then, the output waveform is shown as follows. sinα · sinβ = {cos (α−β) −cos (α + β)} Therefore, only the sum and difference frequencies of the two input waveforms appear as output waveforms, and the sum and difference frequencies of the input waveforms Has no harmonic relationship with the frequency of the original string vibration. As a result, no string frequency appears due to picking, and it is not possible to know which string was picked. Therefore, there was a problem that a feeling of picking could not be obtained, and the feeling of use of an electronic stringed instrument or the like was poor. Therefore, the present invention has improved the usability of an electronic stringed instrument or the like by allowing the original sound frequency to be recognized when a picking sound is input from an electronic stringed instrument or the like so that a picking feeling can be obtained. It is intended to provide an effect adding device.

[0004]

According to the first aspect of the present invention,
In order to achieve the above object, an envelope extracting means for extracting an envelope of an input sound signal converging from sound generation to mute, and an output signal obtained by subtracting an envelope signal from the envelope extracting means from a predetermined specific value and subtracting a subtraction result. Subtracting means for outputting an oscillation signal having a predetermined amplitude and a predetermined frequency, and an output of the oscillating means.
And an envelope signal from the envelope extraction means.
And outputs the multiplication result as a multiplication output signal.
Multiplication means, and a multiplication output output from the first multiplication means
Signal adding means for outputting the added output signal to sum adds the subtraction output signal outputted by the subtracting means,
A second operation of multiplying the addition output signal output by the addition means and the input audio signal and outputting a multiplication result as an output signal
And a multiplication means. The envelope extraction unit includes, for example, a full-wave rectification unit that performs full-wave rectification on the input acoustic signal, and a filter unit that performs low-pass filtering on an output from the full-wave rectification unit, as described in claim 2. , Is composed of The oscillating means may include, for example, a waveform signal generating means for generating a waveform signal containing a large number of harmonic components, and a filter for low-pass filtering the waveform signal generated by the waveform signal generating means. , And in this case, the waveform signal generating means generates a triangular wave signal, for example, as described in claim 4.

[0005]

According to the first aspect of the present invention, in the effect adding device, an input audio signal converging from its generation to silencing is input to the envelope extracting means, and the envelope extracting means extracts the envelope of the input audio signal. And outputs it to the subtraction means. Now, since the input acoustic signal converges from its generation to silence, the level of this envelope extraction signal gradually decreases over time. The subtraction means subtracts the envelope signal input from the envelope extraction means from a predetermined specific value, and outputs the result as a subtraction output signal to the addition means. As described above, since the level of the envelope extraction signal gradually decreases as time elapses as described above, the subtraction output signal gradually reaches a predetermined specific value as time elapses. On the other hand, the effect adding device includes an oscillating unit, which generates an oscillating signal with a predetermined amplitude and a predetermined frequency and outputs the oscillated signal to the first multiplying unit. No.
1 multiplication means, the oscillation signal output from the oscillating means and the front
The envelope signal from the envelope extraction means.
And outputs the multiplied output signal to the adding means. The addition means adds the multiplication output signal from the first multiplication means and the subtraction output signal output from the subtraction means, and outputs the result to the second multiplication means as an addition signal. The added output signal, as described above, with the passage of the subtraction output signal is time, gradually so to reach a particular value, it is this gradually signal oscillating signal is superimposed on the subtraction signal to reach a specific value, moreover this oscillation
Since the signal is multiplied by the envelope signal , it gradually decreases as the subtraction output signal approaches a specific value. An input audio signal is further input to the second multiplying means, and the second multiplying means multiplies the addition output signal input from the adding means with the input audio signal, and generates a harmonic component. The resulting multiplication result is output as an output signal. Therefore, the output signal is a signal obtained by multiplying an oscillation signal obtained by low-pass filtering a triangular wave or the like with an envelope on a subtraction output signal gradually reaching a specific value obtained by extracting the envelope of the input audio signal. The addition output signal is multiplied by the input audio signal. As described above, the oscillation signal of the addition output signal decreases as the subtraction output signal approaches a specific value. As a result, the output sound can be changed metallically, and the output signal is reduced only to the input sound as the original sound by reducing the influence of the oscillation signal as the subtraction output signal approaches the specific value. be able to. Therefore, for example, when a tone signal from an electronic stringed musical instrument is used as an input acoustic signal, a sound having the frequency of the picked string can be output, and it is possible to know which string was picked.
As a result, a feeling of picking can be obtained, and the feeling of use of the electronic stringed instrument can be improved. Furthermore, since the magnitude of the oscillation signal on the addition output signal multiplied by the input sound signal changes as the subtraction output signal approaches a specific value, the manner of generation of the harmonic component also gradually changes,
A variety of sounds can be obtained. In the invention according to claim 2, the envelope extracting means includes full-wave rectifying means for performing full-wave rectification on the input acoustic signal, and filter means for performing low-pass filtering on the output from the full-wave rectifying means. Thus, the envelope of the input audio signal can be finely extracted, and an appropriate effect can be added according to the change of the input audio signal. According to the third and fourth aspects of the present invention, a waveform signal containing a large number of harmonic components can be generated by the oscillating means, so that more effective harmonic components can be generated at low cost.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be specifically described based on embodiments. 1 to 25 are diagrams showing an embodiment of the effect adding device of the present invention. FIG. 1 is a schematic configuration diagram of an electronic stringed musical instrument 1 to which the effect adding apparatus of the present invention is applied. The electronic stringed musical instrument 1 includes a pickup 2, a volume 3, an effect circuit 4, a switch 5, an output terminal 6, and the like. .

The electronic stringed musical instrument 1 detects a string vibration with the pickup 2 and outputs it to the effect circuit 4 as an analog input sound signal. The level of the string vibration signal detected by the pickup 2 is adjusted by the volume 3, and the effect circuit 4 performs an effect adding process on the input string vibration signal as described later and outputs the signal as an output signal.
The output signal of the effect circuit 4 is output via the switch 5 and the output terminal 6. When the switch 5 is set to the ON side (ON), the output signal of the effect circuit 4 is output as the output signal of the electronic stringed instrument 1. Is output.
When the switch 5 is set to the off side (OFF), the string vibration signal detected by the pickup 2 is output as it is as an output signal.

The effect circuit 4 includes an A / D converter 11,
DSP (Digital Signal Processor: Digital Sign)
al Processor) 12, D / A converter 13, CPU (Cent
ralProcessing Unit) 14, ROM (Read Only Memory)
15 and a RAM (Random Access Memory) 16.

The string vibration signal (analog input sound signal) detected by the pickup 2 is input to the A / D converter 11, and the A / D converter 11 converts the analog input sound signal into a digital signal. Digital input sound signal WIN
Is output to the DSP 12.

The DSP 12 performs an effect adding process on the input audio signal WIN input from the A / D converter 11 and outputs the result to the D / A converter 13 as a digital output signal WRNG.

The D / A converter 13 converts the output signal WRNG from the DSP 12 into an analog signal and outputs it as an analog output signal to a tone generator or the like (not shown).

The ROM 15 stores a program as an effect circuit, other necessary data and coefficients, and the RAM 16 is used as a work area.

The CPU 14 transfers the program in the ROM 15 to the DSP 12 to cause the DSP 12 to perform an effect adding process, or controls each part of the effect circuit 4 to execute the process as the effect circuit 4.

The DSP 12 performs a full-wave rectification process, a low-pass filtering process, a multiplication process, a subtraction process, an addition process, an oscillation process, and the like, as shown in FIG.

That is, as shown in FIG. 3, the DSP 12 includes a full-wave rectification processing section 20, a low-pass filtering processing section 30, a multiplication processing section A40, a subtraction processing section 50, an addition processing section 60, a multiplication processing section B70, and a sawtooth wave. It includes a generation processing unit 80, a triangular wave generation processing unit 90, an offset processing unit 100, a low-pass filtering processing unit 110, and the like.

The full-wave rectification processing section 20 includes adders 21 and 2
2 and 23, a detector 24 and gates 25 and 26. The full-wave rectification processing unit 20 receives a digital input acoustic signal WIN. The full-wave rectification processing unit 20 performs full-wave rectification on the input acoustic signal WIN, and outputs a rectified signal WEPO to the low-pass filtering processing unit 30.

That is, the input audio signal WIN is input to the adder 21, and the adder 21
Detector 2 subtracts zero value WZRO, which is "0", from IN.
4 is output. Since the input acoustic signal WIN is due to the string vibration as described above, the rising at the time of occurrence thereof is steep as shown in FIG. 4 and thereafter converges to disappear. The detector 24 detects this subtraction result, and when the subtraction result is positive, opens the gate 25 and adds the zero value WZRO to the input audio signal WIN, that is, the input audio signal WIN
This is output as the rectified signal WEPO. When the subtraction result is negative, the detector 24 opens the gate 26 and subtracts the input sound signal WIN from the zero value WZRO,
That is, an inverted version of the input acoustic signal WIN is output as the rectified signal WEPO. Therefore, when the input acoustic signal WIN as shown in FIG. 4 is input, the full-wave rectification processing unit 20 inverts the waveform on the negative side, and outputs as a full-wave rectified rectified signal WEPO as shown in FIG. I do.

The low-pass filtering section 30 includes multipliers 31, 32, 33, adders 34, 35, and a delay element 36. The low-pass filtering section 30 performs full-wave rectification on the input acoustic signal WIN to perform full-wave rectification. The rectified input audio signal WIN is subjected to envelope processing. Therefore, the full-wave rectification processing unit 20 and the low-pass filtering processing unit 30 constitute an envelope extraction unit that extracts the envelope of the amplitude of the input audio signal WIN as a whole.

The multiplier 31 of the low-pass filtering section 30 includes a rectified signal W from the full-wave rectifying section 20.
EPO is input, and the multiplier 31 receives the input rectified signal WE.
PO is multiplied by a predetermined filter coefficient PCE0 (for example, 0.2) and output to the adder 34. The adder 34 multiplies the output of the multiplier 31 by the output of the multiplier 32 and outputs the result to the adder 35 and the delay element 36.
Thus, the output signal (LPF delay signal) WCL0 of the adder 34 delayed by one sampling is multiplied by the filter coefficient PCE1 and output to the adder 34. The adder 35 includes an adder 34
Is multiplied by the output of the multiplier 33, and the multiplication result is represented by L
The signal is output as the PF output signal WCL1 to the multiplication processing unit A40 and the subtraction processing unit 50. The multiplier 33 outputs the LPF delay signal W
CL0 is multiplied by a filter coefficient PCE2 and output to the adder 35.

Therefore, the low-pass filtering section 30 outputs the rectified signal WEPO output from the full-wave rectification section 20.
, And outputs an LPF output signal WCL1 which is an envelope extraction signal as shown in FIG. Further, as shown in FIG. 4, since the input acoustic signal WIN is due to the string vibration converging from its generation to disappearance, the LP obtained by envelope-extracting this input audio signal WIN is used.
The waveform of the F output signal WCL1 once rises and converges to "0" as shown in FIG.

On the other hand, the sawtooth wave generation processing unit 80 includes an adder 81
The sawtooth wave rate WLF1 is added to the adder 81.
Is entered. The adder 81 adds the sawtooth wave rate WLF1 to the sawtooth wave output signal WCC0, which is its own addition output, and
And generates a sawtooth wave, and outputs it as a sawtooth wave output signal WCC0 to the triangular wave generation processing unit 90.

The triangular wave generation processing section 90 includes adders 91 and 9
2, 93, a detector 94, and gates 95 and 96. The sawtooth wave generated by the sawtooth wave generation processing unit 80 is converted into a triangular wave.

That is, the sawtooth wave output signal WCC0 from the sawtooth wave generation processing unit 80 is input to the adder 91, and the adder 91 detects the sawtooth wave output signal WCC0 by subtracting it from the zero value WZRO. Output to the device 94. The detector 94 detects whether the subtraction result of the adder 91 is positive or negative. If the subtraction result is positive, the gate 95 is opened and the adder 92 adds the zero value WZRO to the sawtooth output signal WCC0. Is output to the offset processing unit 100 as a triangular wave output signal Wcc1. When the subtraction result is negative, the detector 94 opens the gate 96 and outputs the value obtained by subtracting the sawtooth output signal WCC0 from the zero value WZRO by the adder 93 to the offset processing unit 100 as a triangular output signal WCC1.

Therefore, the triangular wave generation processing unit 90 generates the triangular wave shown in FIG. 8 by inverting the negative side of the sawtooth wave shown in FIG. 7 and outputs the triangular wave to the offset processing unit 100 as a triangular wave output signal WCC1.

The offset processing unit 100 includes an adder 101
And performs an offset process on the triangular wave output signal Wcc1 input from the triangular wave generation processing unit 90.

That is, the adder 101 is supplied with the offset value W HAF, and the adder 101 subtracts the offset value W HAF from the triangular wave output signal W CC1 input from the triangular wave generation processing section 90 to obtain the triangular wave offset signal. WQPO.

Therefore, the offset processing unit 100
The triangular wave output signal WCC1 shown in FIG. 8 is subjected to offset processing as shown in FIG. 9, and is output to the low-pass filtering processing unit 110 as a triangular wave offset signal WQPO.

The low-pass filtering processing unit 110
Multipliers 111, 112, 113, adders 114, 115
And a delay element 116, and performs a low-pass filtering process on the triangular wave output from the offset processing unit 110 to make the triangular wave closer to a smooth sine wave.
The low-pass filtering section 110 performs the same processing as that of the low-pass filtering section 30, and the filter coefficients input to the multipliers 111, 112, and 113 are different.

That is, the filter coefficient PFL0 (for example, 0.2) is input to the multiplier 111, and the multiplier 111 multiplies the triangular wave offset signal WQPO input from the offset processing unit 100 by the filter coefficient PFL0. And outputs the result to the adder 114. The adder 114 is connected to the multiplier 11
1 and the output of the multiplier 112 are added to the delay element 1
16 and to the adder 115. The multiplier 112 includes:
The filter coefficient PFL1 and the sine wave delay signal WQL0 output from the delay element 116 are input.
By multiplying the sine wave delay signal WQL0 by the filter coefficient PFL1,
Output to the adder 114. The delay element 116 is the adder 1
The addition result of 14 is delayed by one sampling and output to the multipliers 112 and 113. The adder 115
The output of the multiplier 113 is added to the output of the adder 114 and output to the multiplication processing unit A40 as a sine wave output signal WQL1. The multiplier 113 receives the sine wave delay signal WQL0 and the filter coefficient PFL2 from the delay element 116, and the multiplier 113 multiplies the sine wave delay signal WQL0 by the filter coefficient PFL2 and adds the addition result to the adder. Output to 115.

Therefore, the low-pass filtering processing section 110 processes the triangular wave shown in FIG. 9 into a smooth sine wave as shown in FIG. 10, and outputs it to the multiplication processing section A40 as a sine wave output signal WQL1.

Therefore, the sawtooth wave generation processing section 80, the triangular wave generation processing section 90, the offset processing section 100, and the low-pass filtering processing section 110 as a whole have an oscillation signal (sine wave output signal WQL1) having a predetermined amplitude and a predetermined frequency.
Oscillating means 120 for generating the above.

The multiplication unit A40 is composed of a multiplier 41. The multiplier 41 multiplies the LPF output signal WCL1 from the low-pass filtering unit 30 by the sine wave output signal WQL1 from the low-pass filtering unit 110. Then, the signal is output to the addition processing unit 60 as the multiplication signal WLFE.

Therefore, the multiplication processing section A40 multiplies the envelope output waveform shown in FIG. 6 by the sine wave output waveform shown in FIG. 10, and the sine wave is gradually attenuated as shown in FIG. Resulting in a multiplied waveform.

The subtraction unit 50 comprises an adder 51. The LPF output signal WCL1 and the offset value WONE from the low-pass filtering unit 30 are input to the multiplier 51. The multiplier 51 subtracts the LPF output signal WCL1 from the offset value WONE, and outputs the subtraction result to the addition processing unit 60 as an inverted signal WSUB.

Therefore, the subtraction processing section 50 outputs the LPF output signal WCL1 from the low-pass filtering processing section 30.
Is inverted with reference to the offset value WONE, and as shown in FIG.
Is a subtracted waveform obtained by inverting the envelope output waveform shown in FIG.

The addition processing section 60 is composed of an adder 61, to which the multiplication signal WLFE from the multiplication processing section A40 and the inverted signal WSUB from the subtraction processing section 50 are input. The adder 61 performs an addition process on the multiplication signal WLFE and the inverted signal WSUB, and outputs the addition result to the multiplication processing unit B70 as an addition signal WADD.

Therefore, the addition processing section 60 adds the sine wave output waveform shown in FIG. 11 to the subtracted waveform shown in FIG. 12, and as shown in FIG. Will be output.

The multiplication unit B70 is composed of a multiplier 71, to which the addition signal WADD and the input audio signal WIN from the addition unit 60 are input. The adder 71 generates the addition signal WADD and the input sound signal WIN.
And multiply the result by the final output signal WRNG.
Output as

Therefore, the multiplication processing section 60 multiplies the addition waveform shown in FIG. 13 by the input waveform shown in FIG. 4, and as shown in FIG. The final output waveform multiplied by the attenuated oscillation signal is output.

FIG. 15 is a specific circuit configuration diagram of the DSP 12. The DSP 12 includes a program memory 201, a control circuit 202, an input register (PI) 203, a coefficient memory (P) 204, a work memory (W) 205, Output register (OR) 206, multiplication unit 300 and addition / subtraction unit 400
Etc. Each part of the DSP 12 is connected to the internal bus 2
07.

The program memory 201 stores a program as an effect adding device.
The data is written from the CPU 14 shown in FIG. An address counter (not shown) is connected to the program memory 201, and the program memory 201 sequentially supplies the program contents to the control circuit 202 according to the address designation of the address counter.

The control circuit 202 controls the program memory 20
The effect adding process is executed by controlling each unit of the DSP 12 according to the program in the program 1. The details of the process will be described later. The control circuit 202 receives a code flag from an addition / subtraction unit 400 described later,
2 controls processing of the addition / subtraction unit 400 and the multiplication unit 300 based on the sign flag.

An input audio signal WIN is input to the input register (PI) 203, and the input register (PI) 203
After temporarily storing the input audio signal WIN, the input audio signal WIN is transferred to each section of the DSP 12 via the internal bus 207.

A coefficient memory (P) 204 is a register for storing various coefficients required for effect addition processing by the DSP 14. These various coefficients are stored in the ROM 15 of FIG.
5 is read out and written into the coefficient memory (P) 204. As shown in FIG. 16 as a memory map of the coefficient memory (P) 204, a filter coefficient PCE
0 (0.2) has the filter coefficient PCE1
(0.5) has a filter coefficient PCE2
(0.5) has the filter coefficient PFL0 in the address 3.
(0.2) further has a filter coefficient P
FL1 (0.5) and a filter coefficient PFL2 at address 5 are set.

The work memory (W) 205 stores the input audio signal WIN input through the input register (PI) 203.
And a work memory for temporarily storing data of operation results in the multiplication unit 300 and the addition / subtraction unit 400, which will be described later, and a final output signal WRNG. This work memory (W) 20
For example, as shown in FIG. 17 as a memory map of the work memory (W) 205, an input audio signal as a data name WIN is stored at an address 0, and a data name WZRO is stored at an address 1 as shown in FIG. At the address 2, the rectified signal as the data name WEPO, at the address 3, the LPF delay signal as the data name WCL0, at the address 4, and L as the data name WCL1.
The PF output signal has the sawtooth wave rate at the address 5 as the data name WLF1, and the data name WCC0 at the address 6.
And a triangular wave output signal as a data name WCC1 at the address 7 thereof.
The offset value as the data name WHAF, the address 9, the triangular wave offset signal as the data name WQPO, the address 10, the sine wave output signal as the data name WQL1, the multiplication signal as the data name WLFE, and the like. Has an offset value in its address 12 as a data name WONE, and has an
The inverted signal is stored as SUB, the addition signal is stored as the data name WADD at the address 14, and the final output signal is stored as the data name WRNG at the address W.

The multiplication unit 300 includes gates 301 and 302,
Register (M0) 303, (M1) 304, gate 30
5, a multiplier 306 and a register (MR) 307, and outputs from the coefficient memory (P) 204, the work memory (W) 205, and the input register (PI) 203 are input to the gates 301 and 302. Is done.

The gates 301 and 302 are connected to the control circuit 2
02 controls its operation, and determines which data is input to the register (M0) 303 and the register (M1) 304.
Is output or not. Register (M0) 303
Temporarily stores data input through the gate 301, outputs the data to the multiplier 306, and feeds back the data to the gate 301. The register (M1) 304 temporarily stores data input through the gate 302, outputs the data to the multiplier 306 through the gate 305, and feeds back the data to the gate 302. In the gate 305,
The data from the addition / subtraction unit 400 described later is also input. The gate 305 operates under the control of the control circuit 202 to select the data from the register (M1) 304 and the addition / subtraction unit 400 and output the data to the multiplier 306. I do. Multiplier 30
6 is a register (M0) 303 and a register (M1) 3
The multiplication processing is performed on the data input from the block 04, and the calculation result is output to the register (MR) 307. Register (M
R) 307 temporarily stores the multiplication result of the multiplier 306, and then outputs the result to the gate 302 and the addition / subtraction unit 400.

The addition / subtraction unit 400 includes gates 401 and 40
2. Register (A0) 403, Register (A1) 40
4, gates 405 and 406, adder / subtractor 407, register (AR) 408, clipper 409, and register (S
R) 410 and the like, and the gates 401 and 402 have the coefficient memory (P) 204 and the work memory (W)
205 and an output from the input register (PI) 203 are input.

The gates 401 and 402 are connected to the control circuit 2
02 controls the operation of the register (A0) 403 and the register (A1) 404.
Is output or not. Register (A0) 403
Temporarily stores data input through the gate 401, outputs the data to the gate 405, and feeds back the data to the gate 401. The register (A1) 404 temporarily stores data input through the gate 402, outputs the data to the gate 406, and feeds back the data to the gate 402. The data from the register (MR) 307 of the multiplication unit 300 is also input to the gate 405.
The gate 405 operates under the control of the control circuit 202,
The data from the register (A0) 403 and the multiplier 300 are selected and output to the adder / subtractor 407. In the gate 406, in addition to the data from the register (A1) 404, the data of the operation result of the adder / subtractor 407 is stored in the register (AR) 40.
The gate 406 operates under the control of the control circuit 202 to select the input data and output it to the adder / subtractor 407.

The adder / subtractor 407 performs an addition process or a subtraction process on the input data, and outputs the operation result to the clipper 4.
09 and the gate 406, and outputs the maximum bit of the operation result to the control circuit 202 as a code flag F (AR) indicating code information. The clipper 409 is for preventing data overflow, and data passing through the clipper 409 is stored in a register (SR).
410. The output of the register (SR) 410 is output to the gate 305 of the multiplying unit 300, and is also supplied to the work memory (W) 205 via the internal bus 207 as an operation result of processing for a certain sound.

The operation results of the multiplication unit 300 and the addition / subtraction unit 400 are output from the addition / subtraction unit 400 to the work memory (W) 205 via the bus 207. ) 205 to an output register (OR) 206. The output register (OR) 206 outputs the input data as a final output signal WRNG to the D / A converter 13 shown in FIG.

Next, the operation will be described. Electronic stringed instrument 1
When the switch 5 is set to the ON side, the string vibration detected by the pickup 2 is input to the effect circuit 4 in a size corresponding to the adjustment of the volume 3, and the effect circuit 4 performs an effect adding process (effect process). And outputs it to a tone generator or the like (not shown) via the output terminal 6.

The effect adding process by the effect circuit 4 is performed by the DSP 12, and as shown in FIG. 18, a full-wave rectification process of the input acoustic signal WIN (Step S).
1), low-pass filtering processing (LPF processing) (step S2), oscillation processing (step S3), multiplication processing A
The processing is executed according to the procedures of (Step S4), subtraction processing (Step S5), addition processing (Step S6), and multiplication processing B (Step S7).

In order for the effect circuit 4 to cause the DSP 12 to perform each of these processes, first, the CPU 14
A program setting process and various data setting processes are performed on P12.

That is, in order for the DSP 12 to perform the effect processing, the program memory 201, the coefficient memory (P) 204, and the work memory are used to store a program necessary for performing the target effect processing and data used for executing the program. (W) 205 needs to be set.

Therefore, the CPU 14 reads necessary programs and data from the ROM 15 and sets them in the program memory 201, coefficient memory (P) 204 and work memory (W) 205. As shown in FIG. 16, the coefficient memory (P) 204 stores the filter coefficient PCE0, the filter coefficient PCE1, the filter coefficient PCE2, and the filter coefficient PFL.
0, a filter coefficient PFL1 and a filter coefficient PFL2 are set, and a zero value WZRO, a sawtooth wave rate WLF1, an offset value WHAF, and an offset value WONE are set in the work memory (W) 205 as shown in FIG. .

Hereinafter, each processing in the DSP 12 will be sequentially described. Full-wave rectification processing The full-wave rectification processing is to perform full-wave rectification of the input acoustic signal WIN so that low-pass filtering processing to be performed next can be accurately performed.

That is, as shown in FIG. 19, the input audio signal WIN input to the input register (PI) 203 is fetched into the address 0 of the work memory (W) 205 (step S101). As described above, the input acoustic signal WIN is detected by the pickup 2 in FIG. 1 and converted into a digital signal by the A / D converter 11 in FIG. Next, the zero value WZRO is read from the work memory (W) 205, transferred to the register (A0) 403 of the adder / subtractor 400, and set. The input sound signal WIN set in the work memory (W) 205 in step S101 is read. Work memory (W) 20
5, the register (A1) of the addition / subtraction unit 400
It is set to 404 (step S102). The zero value WZRO and the input audio signal WIN are transferred to the adder / subtractor 407 from the register (A0) 403 and the register (A1) 404, and the zero value WZRO is subtracted from the input audio signal WIN and transferred to the register (AR) 408. (Step S10
3). In parallel with this subtraction processing, the work memory (W) 2
05, the zero value WZRO and the input audio signal WIN are read, and the zero value WZRO is transferred to the register (A1) 404 and the input audio signal WIN is transferred to the register (A0) 403, and is set (step S103).

Next, whether the most significant bit of the register (AR) 408, that is, the sign flag F (AR) is 1, that is, whether it is negative or positive (the sign flag F (A
R) is 1 for negative, and sign flag F (AR) is 0 for positive) (step S104). When the sign flag F (AR) is 0, that is, when the subtraction result in step S103 is positive, it means that the input audio signal WIN is on the positive side in FIG.
0) The input acoustic signal WIN of 403 and the register (A1) 40
4 is transferred to the adder / subtractor 407, the input audio signal WIN is added to the zero value WZRO, and a register (A
R) 408 (step S105). When the sign flag F (AR) is 1 in step S104, that is, when the subtraction result in step S103 is negative, it means that the input audio signal WIN is on the negative side in FIG. ) 403 input sound signal WIN
And the zero value WZRO of the register (A1) 404 by the adder / subtractor 4
07, the input audio signal WIN is subtracted from the zero value WZRO, and then transferred to the register (AR) 408 (step S106). That is, when the input audio signal WIN is on the negative side with respect to the zero value WZRO, the input audio signal WIN is inverted.

The value of the sum of the zero value WZRO set in the register (AR) 408 and the input audio signal WIN or the value of the difference between the zero value WZRO and the input audio signal WIN is stored in the register (S
R) 410 (step S107), transferred from the register (SR) 410 to the work memory (W) 205, and stored as a rectified signal WEPO in the work memory (W) (step S108).

The above processing is performed for each input audio signal WIN, and the input audio signal WIN is subjected to full-wave rectification to obtain a rectified signal WEPO.
Output as LPF Processing Next, the LPF processing (low-pass filtering processing) will be described. The LPF process is a process of performing an envelope extraction by performing a low-pass filtering process on a rectified signal WEPO obtained by full-wave rectifying the input acoustic signal WIN, and is a process of the low-pass filtering unit 30 in FIG. This low-pass filtering is performed by DSP
12 performs processing by performing arithmetic processing according to the procedure shown in FIG.

That is, the DSP 12 first reads out the filter coefficient PCE0 from the coefficient memory (P) 204 and transfers it to the register (M0) 303 of the multiplication unit 300, and reads out the rectified signal WEPO from the work memory (W) and 3
00 (M1) 304 (step S
201). Register (M0) 303 and register (M
1) The filter coefficient PCE0 and the rectified signal WEPO transferred to 304 are transferred to the multiplier 306, and a multiplication process (PCE0 × WEP) is performed.
O), and transfers the multiplication result to the register (MR) 307 (step S202). During this multiplication process, the LPF delay signal WCL0 is read from the work memory (W) and transferred to the register (M1) 304, and the coefficient memory (P) 2
04, the filter coefficient PCE1 is read out and the register (M
0) 303 (step S202). The multiplication result (PCE0 × WEPO) transferred to the register (MR) 307 is transferred to the register (AR) 408 of the addition / subtraction unit 400, the filter coefficient PCE1 transferred to the register (M0) 303, and the LPF transferred to the register (M1) 304. Delay signal WCL
0 is transferred to the multiplier 306 for multiplication processing (PCE1 × W
CL0). The multiplication result is transferred to the register (MR) 307 (step S203), and at the same time as the multiplication processing, the LPF delay signal WCL0 is read out from the work memory (W) and transferred to the register (M1) 304, and the coefficient memory ( P) 204 to read out the filter coefficient PCE2 and transfer it to the register (M0) 303 (step S20).
3).

Next, the register (AR) of the addition / subtraction unit 400
The multiplication result (PCE0 × WEPO) transferred to 408 and the multiplication result (PCE1 × WCL0) transferred to the register (MR) 307
Is transferred to the adder / subtractor 407 and the addition processing ((PCE0 × WE
PO) + (PCE1 × WCL0)) and register the addition result in the register (A
R) 408 (step S204). Further, the filter coefficient PCE2 set in the register (M0) 303 and the LPF delay signal WCL0 set in the register (M1) 304 are transferred to the multiplier 306 in step S203.
The multiplication process is performed, and the multiplication result (PCE2 × WCL0) is stored in a register (M
R) 307 (step S204). Addition result in step S204 ((PCE0 × WEPO) + (PCE1 ×
WCL0)) from the register (AR) 408 to the register (S
R) 410, and to the adder 407 via the gate 406.
Is transferred to the adder 407, and the result of addition ((PCE0 × WEPO) + (PCE1 × WCL0))
And multiplication result (PCE2 × WCL0) addition processing {((PCE0 ×
(WEPO) + (PCE1 × WCL0)) + (PCE2 × WCL0)} is performed (step S205). In step S205, the addition result ((PCE0 ×
(WEPO) + (PCE1 × WCL0)) to work memory (W) 2
05 as the LPF delay signal WCL0,
The addition result ｛((PCE0
× WEPO) + (PCE1 × WCL0)) + (PCE2 × WCL0)｝
From the register (AR) 408 to the register (SR) 410
LPF output signal W to work memory (W) 205 via
Write as CL1 (steps S206, S207).

By the above processing, the low-pass filtering processing has been completed for the input audio signal WIN at one sampling timing, and the above processing is sequentially repeated for each input audio signal WIN input at each sampling timing. It is possible to perform a low-pass filtering process on the input audio signal WIN, that is, an envelope extraction process.

Oscillation Processing Next, the oscillation processing will be described. The oscillating process corresponds to the process of the oscillating means 120 in FIG. 3, and is performed by sequentially performing a sawtooth wave generating process, a triangular wave generating process, an offset process, and a low-pass filtering process.
This oscillation process is a process for generating an oscillation signal as a harmonic component to be added to the input acoustic signal WIN.

That is, as shown in FIG. 21, the DSP 12 performs a sawtooth wave generation process in steps S301 to S305, and performs a triangular wave generation process in steps S306 to S315. In addition, the DSP 12 performs steps S316 to S3.
Offset processing is performed in the processing up to 20, and step S
A low-pass filtering process is performed in the processes from 321 to step S327.

First, the sawtooth wave generation processing will be described. The sawtooth generation processing corresponds to the processing in the sawtooth generation processing unit 80 in FIG. In the sawtooth wave generation processing, first, the work memory (W)
The saw-tooth wave rate WLF1 is read out from the
The data is transferred and set to the register (A0) 403 of 0 (step S301). Next, the saw-tooth wave output signal WCC0 is read from the work memory (W) 205, transferred to the register (A1) 404 of the addition / subtraction unit 400, and set (step S302). Register (A0) 403 and register (A
1) From 404, sawtooth rate WLF1 and sawtooth output signal WCC0
To the adder / subtractor 407, subtracts the sawtooth wave rate WLF1 from the sawtooth wave output signal WCC0 (WCC0-WLF1), and transfers the subtraction result to the register (AR) 408 (step S).
303). The subtraction result (WCC0-WLF1) is transferred from the register (AR) 408 to the work memory (W) via the register (SR) 410, and written as a sawtooth output signal WCC0 (steps S304 and S305).

By sequentially performing the above processing on the sawtooth output signal WCC0, a sawtooth wave can be generated.

Triangular Wave Generation Processing The triangular wave generation processing is processing for generating a triangular wave from the sawtooth wave signal (saw wave output signal WCC0) generated by the sawtooth wave generation processing unit 80. The triangular wave generation processing unit 90 in FIG. This corresponds to the processing of.

That is, as shown in FIG. 21, the DSP 12 outputs the sawtooth output signal Wcc from the work memory (W) 205.
0 is read, transferred to the register (A1) 404 and set (step S306), and the work memory (W) 2
Read the zero value WZRO from 05 and register (A0) 4
03 and set (step S307). The sawtooth wave output signal WCC0 set in the register (A1) 404 and the zero value WZRO set in the register (A0) 403 are transferred to the adder / subtractor 407, and the zero value WZRO is subtracted from the sawtooth wave output signal WCC0 (WCC0-WZRO). Then, the result of the subtraction is transferred to the register (AR) 408 and set (step S308).

Next, similarly, the work memory (W) 205
Read the sawtooth output signal WCC0 and the zero value WZRO from
It is set in the register (A0) 403 and the register (A1) 404 (steps S309 and S310), and the most significant bit of the register (AR) 408 set in the above step S308, that is, whether the sign flag F (AR) indicating the sign is 0 or not. Whether it is negative or positive (negative when the sign flag F (AR) is 1, and 0 when the sign flag F (AR) is 0).
Is true) is checked (step S311). When the sign flag F (AR) is 0, that is, in step S30
8 is positive, the sawtooth output signal WCC0 of the register (A0) 403 and the zero value WZRO of the register (A1) 404 are transferred to the adder / subtractor 407 to output the sawtooth output signal WCC0. And the zero value WZRO are added (W
(CC0 + WZRO), and transfers the addition result to the register (AR) 408 and sets it (step S312). On the other hand, if the code flag F (AR) is not 0 in step S311, that is, if the subtraction result (WCC0-
When (WZRO) is negative, the sawtooth output signal WCC0 of the register (A0) 403 and the zero value WZRO of the register (A1) 404 are transferred to the adder / subtractor 407, and the sawtooth output signal WCC0 is subtracted from the zero value WZRO ( (WZRO-WCC0), and the subtraction result is transferred to the register (AR) 408 and set (step S313).

The addition result (WCC0 + WZR) of sawtooth output signal WCC0 transferred to register (AR) 408 and zero value WZRO
O) or the subtraction result (WZRO-WCC0) is stored in the register (S
R) 410 to the work memory (W) 205 and writes it to the work memory (W) as a triangular wave output signal Wcc1 (steps S314, S315). That is,
As shown in FIGS. 7 and 8, a triangular wave is generated by inverting a negative portion of the sawtooth wave generated in the sawtooth wave generation process.

Offset Process Next, the offset process offsets the triangular wave generated in the triangular wave generation process by half the amplitude. This offset processing is performed by the offset processing unit 100 in FIG.
This corresponds to the processing of.

That is, as shown in FIG. 21, the DSP 12 outputs the triangular wave output signal Wcc1 generated by the triangular wave generation processing.
Is read from the work memory (W) 205, transferred to the register (A1) 404, and set (step S31).
6). Next, the offset value WHAF is read from the work memory (W) 205 and set in the register (A0) 403 (step S317). This register (A1) 4
04 and the register (A
0) The offset value W HAF set in 403 is transferred to the adder / subtractor 407, the offset value W HAF is subtracted from the triangular wave output signal W CC1, and the subtraction result (W CC1-W HAF) is transferred to the register (AR) 408 and set ( Step S
318). The subtraction result set in the register (AR) 408 is transferred to the work memory (W) 205 via the register (SR) 410, and written into the work memory (W) 205 as a triangular wave offset signal WQPO (step S).
319, S320).

By performing the above processing on the sequentially generated triangular wave output signal Wcc1, the triangular wave shown in FIG. 8 is offset, and the triangular wave offset signal Wcc shown in FIG.
You can get QPO.

Next, a sine wave is generated by subjecting the triangular wave offset by the offset process to low-pass filtering, and corresponds to the process of the low-pass filtering unit 110 in FIG.

That is, as shown in FIG. 21, the DSP 12 stores the filter coefficient PCE2 from the coefficient memory (P) 204.
Is read out and transferred to the register (M0) 303, and the triangular wave offset signal WQPO generated by the offset processing is read out from the work memory (W) 205 to read out the register (M1).
Transfer to step 304 (step S321). The filter coefficient PCE2 of this register (M0) 303 and the register (M
1) The multiplier 30 multiplies the triangular wave offset signal WQPO of 304
6 and performs a multiplication process (PFL0 × WQPO), and transfers and sets the multiplication result to a register (MR) 307 (step S322). This multiplication process corresponds to the multiplication process in the multiplier 111 of FIG.

At the same time as the multiplication process, the triangular wave offset signal WQPO is read from the work memory (W) 205 and set in the register (M1) 304, and the filter coefficient PFL1 is read from the coefficient memory (P) 204 and stored in the register (M0). ) 303 (step S32)
2). The multiplication result (PFL0 × WQPO) set in the register (MR) 307 is transferred to the register (AR) 408 (step S323), and the triangular wave offset signal WQPO of the register (M1) 304 and the filter coefficient PFL1 of the register (M0) 303 are stored. The result is transferred to the multiplier 306, multiplied (WQPO × PFL1), and the result of the multiplication is stored in a register (M
R) 307 (step S323). This multiplication process corresponds to the multiplication process of the multiplier 112 in FIG. At the same time as the multiplication result (WQPO × PFL1), the triangular wave offset signal WQPO is read from the work memory (W) 205 and transferred to the register (M1) 304, and the filter coefficient PFL2 is read from the coefficient memory (P) 204 and read from the register (M0). ) 303 (step S323).
The multiplication result (WQP) transferred to the register (MR) 307
O × PFL1) and the multiplication result (PFL0 × WQPO) transferred to the register (AR) 408 are transferred to the adder / subtractor 407 for addition processing ((WQPO × PFL1) + (PFL0 × WQPO)), and the addition result is stored in the register. (AR) 408 and set (step S324). This addition processing is performed by the adder 1 shown in FIG.
This corresponds to the addition processing of No. 14.

At the same time as the addition processing, the register (M1)
The triangular wave offset signal WQPO set in 304 and the filter coefficient PFL2 set in the register (M0) 303 are transferred to the multiplier 306 and multiplied (WQPO × PFL2).
Then, the multiplication result is transferred to the register (MR) 307 and set (step S324). This multiplication process corresponds to the multiplication process of the multiplier 113 in FIG.

The addition result ((WQPO × PFL1) + (PFL0 × WQPO)) set in step S324 is left in the register (AR) 408 and the register (S
R) 410 and the addition result ((WQPO × PFL1) + (PFL0 × WQ) remaining in the register (AR) 408.
PO)) and the result of multiplication of the register (MR) 307 (WQPO ×
PFL2) to the adder / subtractor 407 for addition processing 加 算 ((WQ
PO × PFL1) + (PFL0 × WQPO)) + (WQPO × PFL
2) Perform｝ (step S325). This addition result is transferred to the register (SR) 410 and set (step S)
325). Further, in step S325, the register (S
R) Addition result set in 410 ((WQPO × PFL1) +
(PFL0 × WQPO) is transferred to the work memory (W) 205 and written as a triangular wave offset signal WQPO, and the addition result of the register (AR) 408 ｛((WQPO × PF
L1) + (PFL0 × WQPO)) + (WQPO × PFL2)} is transferred to the register (SR) 410 and set (step S)
326). Addition result set in this register (SR) 410 ｛((WQPO × PFL1) + (PFL0 × WQPO)) +
(WQPO × PFL2)} is transferred to the work memory (W) 205 and the work memory (W) 2 is output as the sine wave output signal WQL1.
05 (step S327). This addition processing corresponds to the addition processing by the adder 115 in FIG.
The addition result of 5 is output to the multiplier 40 of FIG. 3 as a sine wave output signal WQL1. Therefore, the triangular wave (see FIG. 9) offset by the offset processing is converted into a sine wave as shown in FIG.

By sequentially and repeatedly executing the sawtooth wave generation processing, the triangular wave generation processing, the offset processing, and the low-pass filtering processing, it is possible to generate an oscillation signal of a harmonic component added in the effect addition processing.

The multiplication process A is a process of multiplying the input sound signal WIN (LPF output signal WCL1) subjected to the low-pass filtering by the LPF process and the sine wave output signal WQL1 subjected to the low-pass filtering by the LPF process. This corresponds to the processing in the multiplication processing unit A40 in FIG.

That is, the DSP 12 outputs the sine wave output signal W from the work memory (W) 205 as shown in FIG.
QL1 is read, transferred to the register (M1) 304, and set (step S401). Also, the LPF output signal WCL1 is read from the work memory (W) 205, transferred to the register (M1) 304, and set (step S402). The sine wave output signal WQL1 set in the register (M1) 304 and the LPF output signal WCL1 set in the register (M0) 303 are transferred to the multiplier 306, and the sine wave output signal WQL1 and the LPF output signal WCL1 are multiplied. Register the multiplication result (WQL1 × WCL1) in the register (MR)
307 (step S403). Further, the work memory (W) 205 is transferred from the register (MR) 307 via the register (AR) 408 and the register (SR) 410.
(Steps S404, S405, S406),
The multiplication signal WLFE is written to the work memory (W) 205 (step S406).

Therefore, the LPF output signal W shown in FIG.
The waveform of CL1 is multiplied by the waveform of sine wave output signal WQL1 in FIG. 10, and as shown in FIG. 11, the waveform of multiplied signal WLFE as an oscillating signal that gradually attenuates can be obtained.

Subtraction process This subtraction process is the LPF process of FIG. 18 (step S2).
Subtracts the low-pass filtering processing result (LPF output signal WCL1) of the input audio signal WIN processed by the above from a specific value (offset value WONE), which corresponds to the processing in the subtraction processing unit 50 in FIG. .

That is, as shown in FIG. 23, the DSP 12 transfers the offset value WONE from the work memory (W) 205.
Is read, transferred to the register (A1) 404, and set (step S501). Work memory (W) 2
05, the LPF output signal WCL1 is read, transferred to the register (A0) 403 and set (step S50).
2). Offset value WONE set in register (A1) 404 and LPF set in register (A0) 403
The output signal WCL1 is transferred to the adder / subtractor 407, and the LPF output signal WCL1 is subtracted from the offset value WONE by a subtraction processing result (WONE-WCL1).
(Step S503). The register (A
R) 408 to the work memory (W) 205 via the register (SR) 410 (steps S504, S5)
05), and write the inverted signal WSUB to the work memory (W) 205 (step S505). By repeatedly performing the above process for each input LPF output signal WCL1, the LPF output signal WCL1 can be inverted.

Therefore, the inverted signal WSUB obtained by inverting the waveform of the LPF output signal WCL1 shown in FIG. 6 with reference to a specific value (offset value WONE) as shown in FIG.
Output as

Addition processing In this addition processing, a multiplication signal WLFE which is a processing result of the multiplication processing A and an inverted signal WS which is a processing result of the subtraction processing are described.
This is a process of adding UB and corresponds to the process of the addition processing unit 60 in FIG.

That is, as shown in FIG. 24, the DSP 12 reads the inverted signal WSUB from the work memory (W) 205, transfers it to the register (A1) 404, and sets it (step S601). Work memory (W) 20
5, the multiplication signal WLFE is read from the register (A0) 4
03 and set (step S602). The inverted signal WSUB set in the register (A1) 404 and the multiplied signal WLFE set in the register (A0) 403 are transferred to the adder / subtractor 407, and the inverted signal WSUB and the multiplied signal WLFE are added (WSUB + WLFE) and added. The result is transferred to the register (AR) 408 (step S603).
Furthermore, from the register (AR) 408 to the register (SR) 4
10 and transferred to the work memory (W) 205 (steps S604, S605), and the work memory (W) 205
As an addition signal WADD (step S60).
5). By repeating the above processing for each of the input inverted signal WSUB and the multiplied signal WLFE, the inverted signal WS
The multiplication signal WLFE can be added to UB.

Therefore, the inverted signal WSU shown in FIG.
A signal obtained by multiplying the waveform B by the multiplication signal WLFE shown in FIG. 11 can be generated. As shown in FIG. 13, an addition signal WADD as an oscillation signal that gradually converges to a specific value can be output.

Multiplication process B This multiplication process B is a process of multiplying the added signal WADD generated by the above-mentioned addition process by the input audio signal WIN, and corresponds to the process in the multiplication processing unit B70 in FIG.

That is, as shown in FIG. 25, the DSP 12 receives the input audio signal WIN from the work memory (W) 205.
Is read, transferred to the register (M1) 304, and set (step S701). Work memory (W) 2
05, read the addition signal WADD, and register (M1)
The data is transferred to and set in step 304 (step S702). The input audio signal WIN set in the register (M1) 304 and the addition signal WADD set in the register (M0) 303 are transferred to the multiplier 306, and the input audio signal WIN and the addition signal W
ADD is multiplied (WIN × WADD), and the multiplication result is transferred to the register (MR) 307 (step S70).
3). Further, the register (A) is transferred from the register (MR) 307 to the register (A).
R) 408 and the register (SR) 410 to the work memory (W) 205 (steps S704 and S7).
05, S706), and writes it as an output signal WRNG in the work memory (W) 205 (step S706).

Therefore, the addition signal WADD shown in FIG.
Is multiplied by the waveform of the input sound signal WIN of FIG. 4 to obtain the waveform of the output signal WRNG shown in FIG.

The output signal WRNG is obtained by multiplying the input acoustic signal WIN by the sine wave output signal WQL1 generated by the oscillating means 120, and outputs the sine wave output signal WQL1.
QL1 converts the input audio signal WI into an inverted signal WSUB obtained by inverting the envelope value of the input audio signal WIN based on a specific value.
The multiplication signal WLFE obtained by multiplying the envelope value of N by the sine wave output signal WQL1 generated by the oscillator 120 is added. Therefore, the oscillating means 12
The sine wave output signal WQL1 generated at 0 can be superimposed thereon, and a dissonant output signal WRNG which is an effect as a so-called ring modulator can be generated to change the input sound like a metal sound.

Further, as shown in FIG. 12, the inverted signal WSUB gradually becoming a specific value (1 in the embodiment) is added to FIG.
As shown in FIG. 1, the multiplication signal WLF whose amplitude gradually decreases
E is added to generate an addition signal WADD as shown in FIG. 13, and this addition signal is multiplied by the input audio signal WIN. Therefore, when the amplitude of the input audio signal WIN is large, the input audio signal WIN An output signal WRNG obtained by adding a ring modulator effect to the input audio signal W can be obtained.
Since the inverted signal WSUB gradually approaches a specific value as the amplitude of IN decreases, the sine wave output signal WQL1 generated by the oscillating means 120 has no effect, and only the input acoustic signal WIN is output as the output signal WRNG. As a result, a sound of the frequency of the picked string can be output, and it is possible to know which string was picked. as a result,
The feeling of picking can be obtained, and the feeling of use of the electronic stringed instrument can be improved. Furthermore, since the magnitude of the transmission signal on the addition output signal multiplied by the input sound signal changes as the subtraction output signal approaches a specific value, the manner in which the harmonic components are generated also gradually changes, and A rich tone can be obtained.

According to the first aspect of the present invention, the output signal is obtained by converting the output signal to the subtracted output signal which gradually reaches the specific value.
Output signal with the oscillation signal multiplied by the loop signal
Furthermore, the input audio signal has been multiplied,
This subtraction output signal is a signal that gradually approaches a specific value. Therefore, by adding the ring modulator effect on the output signal, the output signal it is possible to vary metallically, the output signal, to reduce the influence of the oscillation signal in accordance with the subtraction output signal is close to a specific value, Finally, only the input sound that is the original sound can be obtained. Therefore,
If the tone signal of the electronic string instrument is applied as the input acoustic signal, the sound of the frequency of the picked string can be output,
You can know which string was picked. As a result, a feeling of picking can be obtained, and the feeling of use of the electronic stringed instrument can be improved. In addition, since the magnitude of the oscillation signal on the addition output signal multiplied by the input sound signal changes as the subtraction output signal approaches a specific value, the manner of generation of the harmonic component also gradually changes, and A rich tone can be obtained.

According to the second aspect of the present invention, the envelope extracting means includes full-wave rectifying means for full-wave rectifying the input acoustic signal, and filter means for low-pass filtering the output from the full-wave rectifying means. Because it is composed,
Envelope extraction of an input audio signal can be performed finely, and an appropriate effect can be added according to a change in the input audio signal.

According to the third and fourth aspects of the present invention, since an oscillation signal is created by low-pass filtering a waveform signal containing a large number of harmonic components, if the filter characteristics of this low-pass filtering are varied. Therefore, it is possible to more easily generate various waveform signals having different ratios including harmonic components.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of an electronic stringed instrument as one embodiment of an effect adding device according to the present invention.

FIG. 2 is a block diagram of the effect circuit shown in FIG. 1;

3 is a full-wave rectification process, an envelope extraction process, a multiplication process A, a subtraction process, an addition process, and a multiplication process B of the DSP of FIG.
And a configuration diagram schematically showing oscillation processing.

FIG. 4 is a waveform diagram of an input acoustic signal.

FIG. 5 shows an input acoustic signal WIN in the full-wave rectification processing unit 20 of FIG. 3;
FIG. 3 is a waveform diagram of a full-wave rectified signal obtained by full-wave rectification of FIG.

FIG. 6 is a waveform diagram of an envelope signal obtained by performing envelope extraction on a full-wave rectified signal by the low-pass filtering processing unit 30 of FIG. 3;

FIG. 7 is a waveform diagram of a sawtooth wave generated by the sawtooth wave generation processing unit 80 of FIG. 3;

8 is a waveform diagram of a triangular wave generated by a triangular wave generation processing unit 90 in FIG.

9 is a waveform chart in which a triangular wave generated by the offset processing unit 100 in FIG. 3 is offset.

FIG. 10 shows a low-pass filtering processing unit 110 shown in FIG. 3;
FIG. 3 is a waveform diagram of a sine wave generated in FIG.

FIG. 11 is a waveform diagram of a multiplication signal generated by a multiplication processing unit A40 in FIG. 3;

FIG. 12 is a waveform chart of an inverted signal generated by a subtraction processing unit 50 of FIG. 3;

FIG. 13 is a waveform diagram of an addition signal generated by the addition processing unit 60 in FIG. 3;

FIG. 14 is a waveform diagram of an output signal generated by a multiplication processing unit B70 in FIG. 3;

FIG. 15 is a detailed circuit configuration diagram of the DSP of FIG. 2;

FIG. 16 is a diagram showing filter coefficients stored in a coefficient memory (P) in FIG. 15;

FIG. 17 is a view showing various data stored in a work memory (W) in FIG. 15;

FIG. 18 is a flowchart showing a basic processing flow of an effect adding process in the DSP.

FIG. 19 is a flowchart showing the detailed processing contents of the full-wave rectification processing of FIG. 18;

FIG. 20 is a flowchart showing the detailed processing contents of the oscillation processing of FIG. 18;

FIG. 21 is a flowchart showing the detailed processing contents of the LPF processing in FIG. 18;

FIG. 22 is a flowchart showing the details of multiplication processing A in FIG. 18;

FIG. 23 is a flowchart showing the details of the subtraction process of FIG. 18;

FIG. 24 is a flowchart showing the detailed processing contents of the addition processing of FIG. 18;

FIG. 25 is a flowchart showing the details of multiplication processing B in FIG. 18;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 electronic string instrument 2 pickup 4 effect circuit 11 A / D converter 12 DSP 13 D / A converter 14 CPU 15 ROM 16 RAM 20 full-wave rectification processing unit 30 low-pass filtering processing unit 40 multiplication processing unit 50 subtraction processing unit 60 addition processing Unit 70 multiplication processing unit 80 sawtooth generation processing unit 90 triangular wave generation processing unit 100 offset processing unit 110 low-pass filtering processing unit 201 program memory 202 control circuit 203 input register (PI) 204 coefficient memory (P) 205 work memory (W) 206 Output register (OR) 300 Multiplication unit 400 Addition / subtraction unit

Claims (4)

(57) [Claims] 1. An envelope extracting means for extracting an envelope of an input audio signal converging from a sound generation to a mute, and subtracting an envelope signal from the envelope extracting means from a predetermined specific value to output a subtraction result as a subtraction output signal. Subtracting means, an oscillating means for generating an oscillating signal having a predetermined amplitude and a predetermined frequency, an output of the oscillating means and a signal from the envelope extracting means.
Multiplies the result by multiplying the envelope signal and the output signal
First multiplication means for outputting the result of the first multiplication , addition means for adding the multiplication output signal output from the first multiplication means and the subtraction output signal output from the subtraction means, and outputting an addition result as an addition output signal; A second operation of multiplying the addition output signal output by the addition means and the input audio signal and outputting a multiplication result as an output signal
Effect adding apparatus comprising: the multiplication means. 2. The method according to claim 1, wherein the envelope extracting unit includes: a full-wave rectifying unit that performs full-wave rectification on the input acoustic signal; and a filter unit that performs low-pass filtering on an output from the full-wave rectifying unit. The effect adding device according to claim 1. 3. The oscillating means comprises: a waveform signal generating means for generating a waveform signal containing a large number of harmonic components; and a filter means for low-pass filtering the waveform signal generated by the waveform signal generating means. 2. The effect adding device according to claim 1, wherein: 4. The effect adding apparatus according to claim 3, wherein said waveform signal generating means generates a triangular wave signal.