JP3148809B2 - Module synthesis equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a CMOS LSI.
The present invention relates to a technique for synthesizing a layout module of a data path circuit used for such a circuit.

[0002]

2. Description of the Related Art As a conventional module synthesizing apparatus, cells whose design rules are parameterized are arranged in accordance with bits in the vertical direction and in accordance with functions in the horizontal direction. There was something to do wiring. Some have a function of optimizing the driving capability of the cell on a cell-by-cell basis.

In addition, some layout modules have a plurality of circuit candidates corresponding to each function, and some have a function of automatically selecting an optimum one from among them.

[0004]

However, the conventional module synthesizing apparatus has the following problems.

[0005] In recent years, the degree of integration and clock frequency of LSIs have been steadily increasing.
transistor number per m ² reached 18 million, the clock frequency is also predicted that it becomes 500MHz (SRC, "National Technology Roadmap for Semiconduct
or ", 1997).

[0006] Against this background, in the manufacture of LSIs, the era of the deep sub-micron has arrived, and as a result, LSI designs have become more and more complicated. For example,
Since the wiring interval is extremely small, about 0.1 μm, the delay and the power consumption depend more on the wiring load than on the gate capacitance.
It has become extremely difficult to evaluate power consumption and clock skew on the upstream side (functional level, RTL level) of the design. Also, as the wiring interval becomes smaller, it becomes necessary to reflect the influence of the coupling capacitance between the wirings on a wiring model for estimating the wiring delay. It is almost impossible to estimate with

For this reason, on the downstream side (logic level, transistor level) of the design, the function of correcting the design result on the upstream side becomes very important. That is, by making the evaluation function on the upstream side of the design and the correction function on the downstream side of the design cooperate well, it is possible to reduce rework in the LSI design, thereby reducing the design cost and improving the quality of the LSI. The design can be realized.

In order to make the upstream and downstream sides of the design cooperate well, it is necessary to provide accurate information on the performance and area of the module required by the upstream side from the downstream side of the design in a short time. In other words, in order for the synthesis tool of the upstream design to search the design space when optimizing the allocation and binding of the module,
The module synthesis device on the downstream side is required to have a function that can immediately estimate a synthesis result for a plurality of conditions.
However, the conventional module synthesizing apparatus does not have such a function, and only synthesizes layout modules under one condition. For this reason, when trying to estimate the performance and area of a module under a plurality of conditions, there is no other way than to actually synthesize the module each time, and there is a problem that a great deal of processing time is required.

Further, in the conventional module synthesizing apparatus, since there is almost no freedom in cell shape, a dead area is likely to be generated between cells when, for example, a cell having an optimum drive capacity is selected. That is, there is a problem that the shape of the layout module cannot be optimized with high accuracy.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has been described as a module synthesizing device for a data path circuit.
It is an object to improve user convenience so that a module having excellent delay performance can be synthesized.

[0011]

Means for Solving the Problems In order to solve the above-mentioned problems, a solution taken by the invention of claim 1 is a module synthesizing apparatus for synthesizing a layout module of a data path circuit. A function characteristic estimating unit for estimating the delay of the function, a function characteristic display unit for displaying the delay of each function estimated by the function characteristic estimating unit, and displaying the data path diagram,
The data path diagram includes a data path diagram display correction unit that corrects the arrangement of registers in the data path diagram according to an instruction given from outside the module synthesizing apparatus.

According to the first aspect of the present invention, the user can interactively correct the register arrangement in the data path diagram by the data path diagram display correction unit while watching the delay of the function displayed by the function characteristic display unit. . For this reason, the processing time imbalance between the time slots can be easily eliminated, and a module having better delay performance than the conventional one can be synthesized.

According to the second aspect of the present invention, the function characteristic display section in the module synthesizing apparatus according to the first aspect displays the delay of each function collectively for each time slot, and displays the delay of each function for each time slot. Is displayed as the processing time of the time slot.

According to the second aspect of the present invention, since the processing time of each time slot is displayed, the user can easily change the arrangement of the registers for eliminating the imbalance in the processing time between the time slots. .

Further, in the invention according to claim 3, the function characteristic display section in the module synthesizing device according to claim 2 displays a time slot in which the processing time is maximum as a time slot for determining a clock cycle.

According to the third aspect of the present invention, the time slot that determines the clock cycle of the data path circuit and has the longest processing time is displayed, so that the user can eliminate the imbalance in the processing time between the time slots. Can be more easily changed.

According to the fourth aspect of the present invention, in the first aspect,
The function characteristic estimating unit in the module synthesizing device includes means for determining a specific delay and output stage drive capability of each function, means for estimating a delay time of a signal required for control of each function, and virtual wiring between the functions. Means for estimating the delay of one function, the intrinsic delay of the one function, the delay time of a signal required for controlling the one function, and the output of the one function among virtual wirings between the functions. Means for obtaining the sum by adding the wiring delay when the wiring driven by the stage is driven by the output stage drive capability of the one function.

According to the fourth aspect of the present invention, the delay of a function is determined in consideration of the delay time of a signal such as a carry required for control, so that the delay of each function can be estimated more accurately.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the module synthesizing apparatus according to the present embodiment. The module synthesizing apparatus according to the present embodiment shown in FIG. 1 has a function level processing unit 1 for converting a data path diagram 1 into logic circuit information 2.
1. A logic level processing unit 12 for specifying a cell in a data path circuit based on the logic circuit information 2 input from the function level processing unit 11 or from outside, and a data path based on the logic circuit information for which the cell is specified. A synthesis processing unit 13 for synthesizing the layout module 3 of the circuit, a characteristic display unit 20 for displaying characteristics of functions and cells, a characteristic estimating unit 30 for estimating characteristics of functions and cells, and an optimal layout module to be synthesized Optimization processing unit 35 that performs various kinds of processing so that
It has. Further, the module synthesizing apparatus according to the present embodiment further includes a monitor 61 and input means 62 such as a keyboard and a mouse.

The function level processing section 11 has a data path diagram display correction section 11a. The data path diagram display correction section 11a displays the data path diagram 1 on the monitor 61, and displays the displayed data path diagram 1 Is modified (moving, inserting or deleting a register) in accordance with an instruction externally provided via the input means 62. The logic level processing unit 12 displays the logic circuit diagram information 2 on the monitor 61 and corrects the range of each cell in the logic circuit diagram information 2 according to an instruction given from the outside via the input means 62. A correction unit 12a is provided.
The synthesis processing unit 13 has a layout display correction unit 13a. The layout display correction unit 13a displays on the monitor 61 the floor plan of the module input from the outside via the input unit 62, and displays the displayed floor. The plan is modified according to an instruction given from the outside via the input means 62.

The characteristic display section 20 includes a function characteristic display section 21 for reading out the delay time and other characteristics of each function of the data path diagram 1 from the library 50 and displaying them. The characteristic estimating unit 30 includes a function characteristic estimating unit 31 for estimating delay time and other characteristics of each function of the data path diagram 1 and a cell characteristic estimating unit 32 for estimating characteristics such as cell area.

The optimization processing section 35 includes a circuit clustering processing section 36, a gate level drive capacity optimization section 37, a transistor level drive capacity optimization section 38, and a module internal wiring processing section 39. The library 50 includes a logic circuit library 51, a transistor circuit library 52, and a technology library 53.

The module synthesizing apparatus according to the present embodiment outputs the layout module 3 which is a result of synthesizing the module, and the shape function 4 of the layout module parameterized by delay as module estimation data. Alternatively, one of the layout module 3 and the shape function 4 is output as module estimation data.

FIG. 2 shows an example of the data path diagram 1 displayed on the monitor 61 by the data path diagram display correcting section 11a. 2, I1 to I4 are input terminals, F1 to F4 are functions, E1 to E9 are data flows, R1 to R6 are registers, and O1 is an output terminal. The data path diagram 1 handled by the module synthesizing apparatus according to the present embodiment allows modification of register arrangement and change of module binding (selection of an actual circuit assigned to the function).
On the other hand, resource sharing is not allowed.

According to the module synthesizing apparatus according to the present embodiment, the user can modify the arrangement of registers in the data path diagram 1 by an interactive operation.

The delay time of each function and the insertion position of the register affect the clock cycle of the LSI. Normally, resource sharing and module binding are performed in the upstream design process, and the register insertion position in the data path diagram is determined, and the module synthesizer performs the data path diagram given these conditions in the upstream design process. Synthesize the layout module. However, when the process technology changes, it is necessary to reuse and re-optimize the layout module by making maximum use of information in the upstream design process. In such a case, in module synthesis, it is preferable to allow the register to be moved within a range that does not change the operation specification determined in the upstream design process. By using the module synthesizing apparatus according to the present embodiment, it is possible to interactively designate the insertion position of the register related to the pipeline processing, so that the layout module can be reused and re-optimized.

That is, one of the features of the module synthesizing apparatus according to the present embodiment is that the module synthesizing apparatus has a function of making it possible to modify the arrangement of registers in a data path diagram by an interactive operation in module synthesizing.

FIG. 3 is an example of a screen displayed on the monitor 61 by the function characteristic display section 21 corresponding to the data path diagram 1 shown in FIG. As shown in FIG.
On the display screen of the function characteristic display unit 21, characteristics such as delay of each function are collectively displayed for each time slot.

The delay of each function is obtained by the function characteristic estimating unit 31. The delay of each function obtained by the function characteristic estimation unit 31 is stored in the logic circuit library 51, and the area and power consumption are also stored in the logic circuit library 51. The function characteristic display unit 21 reads the delay, area, and power consumption of each function from the logic circuit library 51 and displays them on the monitor 61 as shown in FIG.

In the data path diagram shown in FIG.
In time slot 1, functions F2 (addition) and F3 (multiplication) are sequentially performed. In this case, the delay (10) of the function F2 and the function F3
(50) with the delay (40) is the processing time of time slot 1. On the display screen of the function characteristic display section 21, in order to display the processing time of each time slot together with the delay of each function, for example, as shown in FIG. 3, the delay of each function is displayed in a black band, and the time slot of each time slot is displayed. The processing time is indicated by a hatched band.

The operation of each time slot needs to be processed within one clock cycle. Therefore, the factor that determines the clock cycle is time slot 1
This is the maximum processing time per unit. In FIG. 3, the processing time (50) of time slot 1 corresponds to this. That is, the clock cycle can be shortened by increasing the processing speed of the function assigned to the time slot 1. To show this to the user, for example, FIG.
As shown in (1), "*" is displayed in the time slot where the processing time is the maximum.

The functions assigned to the time slots other than the time slot in which the processing time is maximized have a larger delay until the processing time of the time slot reaches the maximum processing time per one time slot. Can be replaced by In order to indicate this, for example, as shown in FIG. 3, in each time slot, a maximum processing time per one time slot, that is, a clock cycle is displayed by a white frame. The delay margin represented by the parts other than the black band in this white frame,
Called slack.

Since the conventional module synthesizing apparatus does not have a function of correcting the register arrangement in the data path diagram, even if there is an imbalance in the processing time between the time slots, it cannot be solved. For this reason, a module having excellent delay performance could not be synthesized. Further, the register insertion position for pipeline processing is fixed, and the register position cannot be modified so as to improve the performance of the module. It is also difficult for the user to grasp the characteristics of each function and optimize the performance of the module.
That is, the conventional module synthesizing apparatus does not have a function of displaying a characteristic of each function or a portion which is critical in terms of module performance, and can obtain only characteristic information on a synthesis result. Complicated work required complicated work, and it took time for module development.

However, in the module synthesizing apparatus according to the present embodiment, the user can correct the register arrangement in the data path diagram by looking at the display screen of the function characteristic display section 21 as shown in FIG. For this reason, the processing time imbalance between the time slots can be eliminated, and a module having better delay performance than the conventional one can be synthesized.

FIG. 4 shows an example of a logic circuit representing a data path circuit displayed on the monitor 61 by the logic circuit diagram display correction section 12a. In FIG. 4, 101 is a register, 102 is a cell, and 103 is a register string. Cell 102 is obtained by grouping one or more logic circuits.

In this specification, a cell is a concept representing a set of circuits having a group of functions. The specific implementation of the cell depends on the design phase. That is, at the beginning of the design, the cell is represented by functional information, when the logic design is completed, the cell is represented by a set of logic circuits, when the circuit design is completed, the cell is represented by a transistor-level circuit, and the layout design is completed. Upon completion, the cell is represented by the layout diagram. The cell may be called a function cell or a function cell.
A cell for performing an operation is called an operation cell, and a cell for storing data is called a storage cell.

In the upstream design, since cells correspond to functions, the function level processing unit 11 arranges operation cell columns and storage cell columns (register cell columns) along the data flow according to the data path diagram 1. The data path diagram 1 is converted into logic circuit information 2 by reading and assigning logic circuits corresponding to each function from the logic circuit library 51. The logic circuit diagram display correction unit 12a displays the logic circuit information 2 input to the logic level processing unit 12 on a monitor 61 in the form of a logic circuit diagram on a screen, and also displays the range of each cell in the logic circuit diagram from the outside. The correction is made according to the instruction given via the input means 62.

Therefore, in the module synthesizing apparatus according to the present embodiment, the set of logic circuits included in the cell is changed by the user's interactive operation,
It is possible to change the arrangement of cell columns.

FIG. 5 shows an example of a layout module floor plan displayed on the screen of the monitor 61 by the layout display correcting section 13a. In FIG. 5, reference numeral 111 denotes a register cell row, and 112 denotes an operation cell row. Combination processing unit 13
Is externally input means 6 in accordance with the cell connection information as shown in FIG.
2 creates a floor plan of the layout module in accordance with the instruction given through Step 2. Note that it is possible to select a two-tiered stack of cells or the like as the floor plan of the layout module by user's designation or automatic optimization processing.

The data of the library 50 is also displayed on the screen by the characteristic display unit 20.

FIG. 6 is an example of a screen display of the data of the logic circuit library 51, and is a diagram showing data of the area, delay, and power consumption for the adder. Logic circuit library 5
In 1, data of each function such as an adder is stored in a form in which the area, delay, and power consumption are parameterized. These data are calculated by the function characteristic estimating unit 31. In FIG. 6, a hatched portion indicates a circuit currently selected for this function (adder). The user interactively optimizes by, for example, finding a function whose delay is to be improved by looking at the function characteristics shown in FIG. 3 and selecting an optimum circuit for this function from the display shown in FIG. It can be performed.

FIG. 7 is an example of a screen display of data of the transistor circuit library 52, and is a diagram showing a transistor circuit for an inverter. The transistor circuit library 52 stores the data of the transistor circuit corresponding to each logic circuit. In FIG. 7, a hatched portion indicates a transistor circuit currently selected for this logic circuit (inverter).

The technology library 53 includes design rules, constraints, and the like of the technology currently used.
Circuit parameters and the like are stored, and are mainly referred to by the optimization processing unit 35.

The cell characteristic estimating unit 32 obtains a shape function parameterized by delay for a cell having a transistor-level circuit configuration. FIG. 8 is a graph showing an example of the cell shape function parameterized by the delay. As shown in FIG. 8, the cell shape function parameterized by the delay is a set of cell shape functions obtained respectively for a plurality of delay requests, and each shape function is one delay request. And the relationship between the height (Y) and the width (X) of the cell satisfying the following condition, and expresses the degree of freedom of the cell shape. The cell shape function parameterized by the delay is used to minimize the dead area between cells in the module and improve the degree of integration of the module when the module is synthesized by the synthesis processing unit 13.

When a transistor-level circuit configuration for a cell is given, the cell characteristic estimating unit 32 sets a plurality of delay requests for the cell, and performs the following <cell shape function estimation processing> for each delay request. By doing so, the cell shape function parameterized by the delay as shown in FIG. 8 is obtained. Note that an upper limit and a lower limit of the cell height are given. <Cell Shape Function Estimation Process> (Step E1) One delay request is set for the cell. (Step E2) Optimize the gate width of each transistor (eg, Fishburn et. Al, "TILOS: A Po
synomial Programming Approach to Transistor Sizin
g ", ICCAD85, pp. 326-328, 1985.) (Step E3) Among the transistors constituting the cell, those in which the transistors connected in series are diffused and shared As a group.

FIG. 9 is a diagram showing an example of a transistor circuit constituting a cell. In FIG. 9, VDD is a power supply, G
ND is ground, TPA to TPD are P-type transistors,
TNA to TND are N-type transistors. P-type transistors TPA and TPB and P-type transistor TP
C and TPD are respectively connected in series. The transistors connected in series are grouped as being shared by diffusion, whereby the transistor groups G1 to G1 are connected.
G6 is determined. (Step E4) According to the structure definition of the cell, possible candidates for the cell height are obtained.

Here, it is assumed that the cell is a CMOS cell in which a P-channel region and an N-channel region are vertically stacked, and the upper and lower limits of the heights of the P-channel region and the N-channel region are given. I do. In each transistor group, a transistor whose gate width is larger than the lower limit of the height of the channel region to which the transistor group belongs is folded, and a shape function in the case of the folding is obtained.

In the transistor circuit shown in FIG.
Assume that the gate width of the transistor group G1 in the channel region is 12 and the height of the P channel region is limited to between 4 and 8.

FIG. 10 is a diagram showing a change in the shape of the transistor group G1 when the folded form is changed. As shown in FIGS. 10A to 10E, the shape of the rectangle surrounding the transistor group G1 changes by changing the number of folding steps. For example, without folding (a)
Then, the width is 6, the height is 12, and the one-stage folded (b),
In (c), the width is 10, the height is 8 and the width is 1 respectively.
In (d) and (e), which are 0, the height is 6, and the two-stage folding is performed, the width is 14;

As a result, the shape function of the transistor group G1 becomes a graph as shown in FIG. In FIG. 11, points 120a to 120e on the graph correspond to those in FIG.
The layouts correspond to the layouts (a) to (e), respectively. Due to the height limitation of the P-channel region, only the shape function of the unhatched portion can be actually laid out. The shape function can be similarly obtained for the other transistor groups.

From the shape function of each transistor group obtained as described above, the area of a transistor that can be obtained when the heights of the P-channel region and the N-channel region are given can be known. Since the efficiency of the transistor area is highest at the point where the width of the transistor changes in each shape function, such points are listed as candidates for the heights of the P-channel region and the N-channel region.

Since the transistor group in the P-channel region and the transistor group in the N-channel region are vertically stacked in the cell, it is necessary to secure an interval Dd for the PN isolation region and the wiring therebetween. For this reason,
A table in which the interval Dd is statistically given from the wiring net is prepared, and the interval Dd given by this table is added to the height candidates of the P-channel region and the N-channel region, thereby obtaining cell height candidates. (Step E5) For each cell height candidate, add the transistor area and the wiring area based on the expected wiring length based on the number of fanouts of each net, and further diffuse and share by the number of output nets, power supply nets, and ground nets. Is performed, the cell area is estimated by reducing the area reduction due to the diffusion sharing of these nets. Thereafter, a value obtained by dividing the estimated cell area by the cell height candidate is set as a cell width corresponding to the cell height candidate. Here, the relationship between the number of fan-outs and the wiring length is given in advance by a table. (Step E6) Obtained in Step E5,
Based on the combination of each cell height candidate and the corresponding cell width, a cell shape function for one delay request set in step E1 is obtained.

In the conventional module synthesizing apparatus, since there is not much freedom in cell shape, there is a problem that a dead area is easily generated between cells when, for example, a cell having an optimum driving capacity is selected. That is, there is no function for realizing a desired cell shape or a function for estimating possible cell shape candidates in a short time, and the cell shape has to be selected from those prepared in advance. There is a problem that the layout module shape is likely to be generated, and therefore the layout module shape cannot be optimized with high accuracy.

On the other hand, in the module synthesizing apparatus according to this embodiment, since the shape function is obtained for the cell, the shape of the layout module can be optimized with high accuracy.

The function characteristic estimating unit 31 calculates the function delay as follows. First, the inherent delay of the function and the drive capability of the output stage are read from the logic circuit library 51, and the virtual wiring between the functions is read from the synthesis processing unit 13. Here, the terminal 11 relating to the wiring net as shown in FIG.
A half circumference of the rectangle 114 including all three is the length of the virtual wiring. Further, based on the distance between cells for the same function and different bits, a control wiring length such as a carry inside the function is estimated. next,
A wiring delay is calculated when virtual wiring for flowing data between functions is driven by the output stage drive capability of the function. Finally, the sum of the intrinsic delay of this function, the delay time of a signal that controls this function, and the calculated wiring delay is determined as the delay of this function.

The function characteristic estimating unit 31
The power consumption of the function is obtained as follows.

The logic circuit library 51 stores a propagation equation for calculating the number of changes in the output signal from the number of changes in the input signal for each function. The number of changes of the data signal and the control signal of this module, which is obtained from a test pattern for evaluating power under the use condition of the entire chip, is given. If there is no test pattern as described above, the number of changes in the data signal of this module can be given by a statistical method, for example, by the method disclosed in Japanese Patent Application Laid-Open No. Hei 8-6980. The function characteristic estimating unit 31 has means for inputting the number of changes of the data signal and the control signal of the module, stores the use condition of the module in a database, and can evaluate the power consumption of each function based on this. I do.

First, the function characteristic estimating unit 31 inputs, from an external system, the number of changes of the data signal and the control signal of the module under the use condition of the whole chip. Next, the process of obtaining the number of changes of the output signal is repeatedly performed sequentially from the input side of the data path circuit using the propagation formula defined for each function.
Next, the power consumption of each function is calculated from the load of each signal line and the number of signal changes. The calculated power consumption of each function is stored in the logic circuit library 51.
As a method for obtaining the propagation equation from the operation description of the function, for example, a method disclosed in JP-A-8-6980 may be used.

Next, the optimization processing unit 35 will be described.

The circuit clustering processing unit 36
In the logic circuit diagram as shown in FIG. 1, a cell is specified by grouping circuit elements. A circuit clustering processing method by the circuit clustering processing unit 36 will be described with reference to FIG.

FIG. 13A is a diagram showing a circuit included in a 1-bit netlist, and FIG. 13B is a diagram showing an example in which circuit elements are assigned to cells in FIG. 13A. 131A to 131F are circuit elements, 132A
132C is the cell to be created, 133A-1
33F is a wiring. In FIG. 13B, the estimated area values are described for the circuit elements 131A to 131F, respectively, and the limit values of the areas are respectively attached to the cells 132A to 132C.

First, a wiring on the delay critical path is found, and this wiring is weighted. Next, an upper limit of the cell area is given by an external designation. The replacement of the circuit elements included in each cell is performed so that the total area of the circuit elements included in each cell when the diffusion sharing is performed is equal to or less than the upper limit value, and the number of cuts of the weighted wiring is minimized. By repeating, a set of circuit elements included in each cell is determined. Here, the sum of the areas of the circuit elements included in each cell is calculated by the above-described cell characteristic estimating unit 32.

Finally, for each circuit element included in the netlist of other bits, grouping as a cell is determined based on the correspondence with the circuit element included in the netlist of the bit processed first.

Gate level drive capacity optimization unit 37
In the data displayed by the characteristic display unit 20, a function or cell in which slack is present is repeatedly replaced with a circuit having a lower output stage drive capability and a smaller area, thereby reducing the output stage of each cell. Optimize drive capacity.

When the transistor size of the output stage of each cell is given, the transistor level drivability optimizing unit 38 controls each transistor in the cell so that the area becomes minimum when the delay time of this cell is given. Optimize the size of For example, Fishburnet. Al, "TILOS: A Posynom
ial Programming Approach to Transistor Sizing ", ICCA
D85, pp. 326-328, 1985.

The module internal wiring processing section 39 performs wiring between cells. For example, J. Cong, B. Preas, and
CLLin, "General models and algorithms for over-th
e-cell routing in standard cell design ", Proc.of DA
C, pp. 709-715, June 1990.

The synthesis processing unit 13 outputs, as module estimation data, the layout module 3 which is the synthesis result of the module, and the module shape function 4 parameterized by the delay. FIG. 14 is a graph showing an example of the module shape function 4 parameterized by the delay.

The module synthesizing process by the module synthesizing apparatus shown in FIG. 1 will be described. FIG. 15 is a flowchart showing the flow of module synthesis processing by the module synthesis device shown in FIG.

First, in step ST 1, the data path diagram 1 is input to the function level processing section 11, and the user views the characteristics such as delay of each function displayed on the screen by the function characteristic display section 21 so that the user can modify the data path diagram display correction section. 11a, or automatically by the function level processing unit 11 under the evaluation index of delay optimization,
In, the register arrangement is corrected.

Next, in step ST2, step S
With respect to the data path diagram input at T1 and the register arrangement of which has been corrected, the function level processing unit 11 reads a logic circuit corresponding to each function from the logic circuit library 51 and assigns the logic circuit information 2, thereby generating logic circuit information 2. Input to the logic level processing unit 12. The logic circuit information 2 here expresses only the logic of the circuit, and does not express the transistor circuit corresponding to the logic. The logic circuit information 2 may be directly input from the outside via input means 62 such as a schema editor. That is, in the module synthesizing apparatus of the present embodiment, any input of the data path diagram 1 expressed at the abstract level or the logic circuit information 2 expressed at the logical level is possible.

Next, in step ST3, step S
The logic circuit input at T2 is roughly arranged on the block.

Next, in step ST4, step S
The virtual wiring length between the logic circuits is obtained based on the schematic arrangement by T3.

Next, in step ST5, a corresponding transistor circuit is read from the transistor circuit library 52 and assigned to each logic circuit. In the transistor circuit library section 52, several transistor circuit candidates are prepared for each logic circuit, and by selecting an optimal candidate from these according to the expected value of the fan-out number and the delay time, the logic circuit is selected. Assignment of circuits to transistor circuits is performed.

Next, in step ST6, the gate level drive capacity optimization unit 35 optimizes the drive capacity of the output stage gate of each logic circuit based on the virtual wiring length between the logic circuits, the purpose of delay, and the delay constraint. .

Next, in step ST7, circuit clustering is performed. Here, the circuit is grouped by a user giving an instruction to the logic circuit diagram display correcting unit 12a or by automatic processing by the circuit clustering processing unit 35, and thereby the cell is specified.

Next, in step ST8, step S
For each cell obtained at T7, the transistor level drive capacity optimizing unit 38 performs the cell internal drive capacity optimization and cell layout synthesis for the purpose of minimizing the cell internal delay and the area.

Next, in step ST9, wiring between cells is performed by the module internal wiring processing unit 39.

Finally, in step ST10, module estimation data is generated.

Step ST10 will be described in detail. Here, it is limited to the case where cells are arranged in a slicing structure, and it is assumed that the floor plan of the module is externally given to the synthesis processing unit 13.

First, the clock cycle is externally set.
Next, an output stage drive capability and a delay request in the cell are given to each cell between the registers so that data transfer between the registers can be performed during the set clock cycle. Based on the given output stage drive capability of each cell and the required intra-cell delay, the cell characteristic estimator 32 obtains a shape function parameterized by the delay of each cell.

Next, a plurality of delay requests are set for the module, and the following <module shape function estimation processing> is performed for each delay request, thereby obtaining the module shape function. <Module Shape Function Estimation Processing> (Step F1) The set delay requirement is satisfied, and
The delay requirement of each cell is determined so as to minimize the module area. This processing will be described later. (Step F2) For each cell constituting the module, refer to the delay function determined in Step F1 and the delay-parameterized shape function already obtained by the cell characteristic estimating unit 32 to obtain one shape function. Decide. (Step F3) The shape function of the module is obtained from the shape function of each cell determined in step F2 and the floor plan of the module.

The processing in step F3 will be described with reference to FIG. 16 (L. Stockmayer, "Optimal Orientations
f Cells in Slicing Floorplan Designs ", Information
and Control, Vol. 59, pp. 91-101, 1983). 16A shows a shape function of the cell A, FIG. 16B shows a shape function of the cell B, and FIG. 16C shows a rectangular shape function surrounding the vertically adjacent cells A and B, respectively. The shape function shown in (c) is obtained by adding the shape function shown in (a) and the shape function shown in (b) in the Y direction. That is, a rectangular shape function surrounding cells adjacent in the vertical direction can be obtained by adding the shape function of each cell in the Y direction. Similarly, a rectangular shape function surrounding cells adjacent in the horizontal direction can be obtained by adding the shape function of each cell in the X direction. Therefore, by adding the shape function of each cell in each of the X and Y directions based on the adjacency relation of the cells represented by the slicing structure,
The shape function of the whole module can be obtained. Then, a shape function of the module is obtained by adding an area corresponding to the inter-cell wiring to the obtained shape function of the entire module.

The processing in step F1 will be described in detail. In step F1, an objective function for determining a delay requirement of each cell is determined as in the following equation (1).

Objective function = (module area) * p (1) Here, p is a penalty constant, and is 1 when the module satisfies the delay requirement, and 2 when the module does not satisfy the delay requirement.

Then, the delay requirement of each cell is obtained by a successive improvement method or the like so that the value of the objective function shown in the equation (1) is minimized. Specifically, first, an initial value is given as the delay of each cell, and the delay of each cell is changed while obtaining the objective function.
This may be determined according to the cell shape function parameterized by the delay, which has already been determined by the above), and the delay of each cell when the objective function is minimized is determined as a delay request.

The module area in the objective function of the equation (1) is given by the minimum area in the module shape function. Also, the shape function of the module here is
Similar to the step F3, it is obtained from the shape function of each cell determined from the cell delay and the floor plan of the module.

Whether the module satisfies the delay requirement is determined by estimating the module delay and comparing the module delay with the delay requirement.

The delay of a module is defined by the delay of each path from the input terminal to the output terminal of this module, that is, either the maximum value or the average value of the path delay.
The path delay is obtained by the sum of the delay of each cell constituting the path and the wiring delay estimated based on the wiring function estimated from the shape function of the module and the floor plan.

A supplementary description will be given of the module synthesizing procedure according to the present embodiment.

The data path diagram as shown in FIG. 2 expresses the flow of data flowing through a function before the insertion position of the register or the insertion position of the wiring is determined. By determining the insertion position, an inter-register path is defined, which can be defined as a problem that gives the processing order of the operation of the inter-register path.

The optimization of the module at the level of the data path diagram includes (1) optimization of the insertion position of the register, (2) optimization of the circuit timing between the registers,
(3) It is realized by optimizing the internal delay of the circuit between the registers.

Regarding (1), the module synthesizing apparatus according to this embodiment has a function of displaying a data path diagram and a function of correcting the insertion position of a register according to an external instruction. The scheduling information can be reflected in module synthesis by the user instructing the register insertion position for pipeline processing.

The method (2) can be realized by finding between registers serving as critical paths in the entire circuit and repeatedly increasing the drive capability of the circuit related to the critical path uniformly. The logic circuit corresponding to each function is obtained by referring to the logic circuit library 51.

Regarding (3), the area and the delay time can be optimized by generating a transistor circuit corresponding to each function and changing the setting of the gate width of each transistor of the generated transistor circuit.
In the present embodiment, the logic circuit library 51 has instance information using the area and the delay time as parameters, and by optimizing these parameters, sets the internal delay of the circuit between the registers to a desired value. The instance information included in the logic circuit library 51 is generated by the cell characteristic estimating unit 32.

[0096]

As described above, according to the present invention, the user can easily cancel the imbalance of the processing time between the time slots in the data path diagram. Can be synthesized.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a module synthesizing apparatus according to an embodiment of the present invention.

FIG. 2 is an example of a data path diagram, and is an example of a screen displayed by a data path diagram display correction unit 11a.

FIG. 3 is an example of a screen displayed by a function characteristic display unit 21 corresponding to the data path diagram shown in FIG.

FIG. 4 is an example of a logic circuit diagram expressing a data path circuit at a logic level, and is an example of a screen displayed by a logic circuit diagram display correction unit 12a.

FIG. 5 is an example of a screen displayed by a layout display correction unit 13;

FIG. 6 is a screen display example of data of a logic circuit library 51, and is a diagram illustrating data of an area, a delay, and power consumption for an adder.

FIG. 7 is a screen display example of data of a transistor circuit library 52, and is a diagram showing a transistor circuit for an inverter.

FIG. 8 is a graph showing an example of a cell shape function obtained by a cell characteristic estimating unit 32;

FIG. 9 is a diagram illustrating an example of a transistor circuit forming a cell.

10 (a) to 10 (e) are diagrams showing a change in the shape of the transistor group G1 shown in FIG. 9 when the folded form is changed.

11 is a graph showing a shape function of the transistor group G1 shown in FIG.

FIG. 12 is a diagram for explaining the length of a virtual wiring.

13A and 13B are diagrams for explaining a circuit clustering processing method, in which FIG. 13A illustrates a circuit included in a 1-bit netlist, and FIG. 13B illustrates the assignment of circuit elements to cells in FIG. FIG.

FIG. 14 is a graph illustrating an example of a shape function indicating module estimation data, that is, a relationship between a height and a width of a layout module.

FIG. 15 is a flowchart illustrating a flow of a module synthesis process according to the embodiment.

16A and 16B are diagrams showing a method of obtaining a shape function of a module, FIG. 16A is a diagram showing a shape function of a cell A, FIG. 16B is a diagram showing a shape function of a cell B, and FIG. FIG. 3 is a diagram showing a rectangular shape function surrounding adjacent cells A and B.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Data path diagram 2 Logic circuit information 3 Layout module 4 Shape function 11 Function level processing part 11a Data path diagram display correction part 12 Logic level processing part 12a Logic circuit diagram display correction part 13 Synthesis processing part 21 Function characteristic display part 31 Function characteristic Estimation unit 32 Cell characteristics estimation unit F1 to F4 Function R1 to R6 Register 102 Cell G1 to G6 Transistor group

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 17/50 H01L 21/82

Claims (4)

(57) [Claims] 1. A module synthesizing apparatus for synthesizing a layout module of a data path circuit, comprising: a function characteristic estimating unit for estimating a delay of each function of a data path diagram; A function characteristic display section for displaying a delay, and a data path diagram display correction section for displaying the data path diagram and correcting the arrangement of registers in the data path diagram according to an instruction given from outside the module synthesizing apparatus. A module synthesizing apparatus, comprising: 2. The module synthesizing device according to claim 1, wherein the function characteristic display unit collectively displays delays of each function for each time slot, and displays a sum of delays of each function for each time slot. A module synthesizing device for displaying as a processing time of a time slot. 3. The module synthesizing device according to claim 2, wherein the function characteristic display unit displays a time slot in which a processing time is maximum as a time slot for determining a clock cycle. Module synthesis device. 4. The module synthesizing apparatus according to claim 1, wherein the function characteristic estimating unit estimates a characteristic delay and an output stage drive capability of each function, and estimates a delay time of a signal required for control of each function. Means for estimating virtual wiring between the functions; delay of one function; inherent delay of the one function; delay time of a signal required for control of the one function; Means for determining a wiring driven by the output stage of the one function of the virtual wiring by summing a wiring delay when the wiring is driven by the output stage drive capability of the one function. Module synthesis device to do.