JP2872990B2 - Integrated circuit layout design apparatus, transistor size determination apparatus, circuit characteristic evaluation method, and transistor size determination method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout design of a semiconductor integrated circuit, and more particularly to a technique for determining an optimum transistor size in a layout design.

[0002]

2. Description of the Related Art In a conventional layout design of a semiconductor integrated circuit, the size of each transistor constituting the integrated circuit is determined before the layout design is performed, and the arrangement of the transistors and the wiring between the transistors are determined based on the determined transistor size. The method of doing was adopted.

On the other hand, when arranging transistors, a so-called diffusion sharing method for sharing diffusion regions of transistors having the same potential is generally used in order to reduce the diffusion capacitance and the area. When there is a transistor whose gate size is larger than that of the arrangement region, the transistor is divided into several smaller transistors. In this case, the diffusion region is usually shared. This is called transistor folding.

As a method of determining the transistor size, the transistor size is determined by a simple formula, assuming that the area and diffusion capacity of the transistor are proportional to the transistor size (Fishburn et.al, "TILOS: A Posynom
ial Programming Approach to Transistor Sizing ", ICCA
D85, pp. 326-328, 1985.) and repeatedly determining transistor size and compaction using actual capacitance after layout as diffusion capacitance (Yamada et.al, "Syn.
ergistic Power / Area Optimization with Transistor S
izing and Wire Length Minimization ", IEICE Trans. E
Electron., VOL. E78-C, NO. 4, pp. 441-446, 1995).

[0005]

However, in the conventional layout design, it has not been possible to optimize the number of folding steps of the transistor using the characteristics of the circuit such as the area and the delay performance as an index. For this reason, conventionally, layout is performed using the transistor size and the number of folding steps that are not optimized, or in order to optimize the transistor size and the number of folding steps, once the transistors are arranged, the transistor size is determined again. I only had to start over.

Further, in the conventional method of determining the transistor size, the reduction of the area and the diffusion capacity due to the diffusion sharing due to the series connection or folding of the transistors is not taken into account, so that the transistor size can be optimized accurately. Did not. For example, in the method of Fishburn, the transistor size can be determined in a relatively short time, but it does not consider the diffusion sharing of the transistor at the time of layout at all, and therefore the transistor size is accurately optimized. I can't say. In addition, Yamada's method is a combination of the conventional compaction and Fishburn's method, and although diffusion sharing is taken into account, the transistor size determination and compaction must be repeated many times. Time is enormous. further,
Neither can the transistor size and the number of folding steps be optimized together.

In view of the above problems, an object of the present invention is to make it possible to optimize the size of each transistor and the number of folding steps in a layout design of an integrated circuit without redetermining the transistor size.

Another object of the present invention is to optimize the transistor size more accurately and in a shorter time than before in deciding the transistor size when designing the layout of an integrated circuit.

It is a further object of the present invention to provide a method for evaluating circuit characteristics in which transistor size can be optimized more accurately and in a shorter time than before.

[0010]

Means for Solving the Problems To solve the above problems, the invention according to claim 1 is a technology for representing circuit data representing a configuration of an integrated circuit to be designed and information representing information relating to a semiconductor manufacturing process. As an integrated circuit layout design apparatus that receives data as input and designs the layout of the integrated circuit, based on the circuit data and the technology data, the size and the number of folding stages of each transistor that constitutes the integrated circuit are determined. Based on the transistor size and the circuit data and the technology data, and the transistor size and the number of folding stages determined by the transistor size determining unit. Determine the wiring between the integrated circuits, In which and a layout unit for generating layouts.

According to the first aspect of the present invention, the transistor size determining means estimates and evaluates the size and the number of folding steps of each transistor constituting the integrated circuit to be designed before generating a layout. Therefore, the size of each transistor and the number of folding stages can be optimized without redetermining the transistor size.

According to a second aspect of the present invention, in the integrated circuit layout designing apparatus according to the first aspect, the transistor size determining means uses the given transistor size candidate based on the circuit data. Diffusion sharing estimating means for estimating a location where diffusion sharing is performed in the circuit layout; and the given transistor size based on the circuit data and technology data and information on the diffusion sharing location estimated by the diffusion sharing estimation means. Circuit characteristic evaluation means for estimating and evaluating the characteristics of the integrated circuit when using the candidate, and providing the transistor size candidate of the integrated circuit to the diffusion sharing estimating means and the circuit characteristic evaluation means; Based on the estimation evaluation result by the circuit characteristic evaluation means, It is assumed that a transistor size optimization means for selecting the register size.

According to the second aspect of the present invention, when a transistor size candidate is given by the transistor size optimizing means, a location where diffusion sharing is performed is estimated by the diffusion sharing estimation means, and the diffusion sharing means is estimated by the circuit characteristic evaluation means. The characteristics of the integrated circuit are estimated and evaluated in consideration of the information of the diffusion sharing location estimated by the above. Therefore, various transistor size candidates are given by the transistor size optimizing means, and the transistor size is selected from the given transistor size candidates based on the estimation and evaluation by the circuit characteristic evaluation means. Since the size can be determined, and there is no need to repeat the transistor size determination and compaction as in the conventional case, the transistor size can be optimized more accurately and in a shorter time than in the conventional case.

According to a third aspect of the present invention, in the integrated circuit layout designing apparatus according to the second aspect, the circuit characteristic evaluation means includes the circuit data and the technology data as well as the diffusion shared portion estimated by the diffusion shared estimation means. An area estimating means for estimating an area of the integrated circuit when the given transistor size candidate is used as an evaluation index of the characteristic based on the information is provided.

[0015] According to the invention of claim 4, the above-mentioned claim 2 is provided.
The circuit characteristic evaluation means in the integrated circuit layout design apparatus of the present invention uses the given transistor size candidate based on the circuit data and technology data and the information of the diffusion sharing portion estimated by the diffusion sharing estimation means. And a delay estimating means for estimating the delay of the integrated circuit as an evaluation index of its characteristic.

According to a fifth aspect of the present invention, in the integrated circuit layout designing apparatus according to the second aspect, the circuit characteristic evaluation means includes the circuit data and the technology data, and the spread shared portion estimated by the spread shared estimation means. A power consumption estimating means for estimating the power consumption of the integrated circuit when the given transistor size candidate is used as an evaluation index of the characteristic based on the information is provided.

According to a sixth aspect of the present invention, there is provided a means for receiving circuit data representing a configuration of an integrated circuit to be designed and technology data representing information relating to a semiconductor manufacturing process as inputs, As a transistor size determining device for determining a size, based on the circuit data, diffusion sharing estimating means for estimating a location where diffusion sharing is performed in a layout of the integrated circuit when a given transistor size candidate is used,
Circuit characteristic evaluation means for estimating and evaluating the characteristics of the integrated circuit when the given transistor size candidate is used, based on the circuit data and the technology data and the information on the diffusion sharing part estimated by the diffusion sharing estimation means. And providing the transistor size candidate of the integrated circuit to the diffusion sharing estimation means and the circuit characteristic evaluation means,
And a transistor size optimizing means for selecting one transistor size from the given transistor size candidates based on the estimation evaluation result by the circuit characteristic evaluation means.

According to the sixth aspect of the present invention, when a transistor size candidate is given by the transistor size optimizing means, a location where diffusion sharing is performed is estimated by the diffusion sharing estimating means, and the diffusion sharing means is estimated by the circuit characteristic evaluation means. The characteristics of the integrated circuit are estimated and evaluated in consideration of the information of the diffusion sharing location estimated by the above. Therefore, various transistor size candidates are given by the transistor size optimizing means, and the transistor size is selected from the given transistor size candidates based on the estimation and evaluation by the circuit characteristic evaluation means. Since the size can be determined, and there is no need to repeat the transistor size determination and compaction as in the conventional case, the transistor size can be optimized more accurately and in a shorter time than in the conventional case.

According to a seventh aspect of the present invention, the diffusion sharing estimating means in the transistor size determining apparatus according to the sixth aspect is connected including two diffusion regions and branches of the transistors connected in series, which are connected to each other. It is assumed that at least one of the two diffusion regions connected to each other and one of the diffusion regions of the transistor whose folding is presumed is assumed to be a portion where diffusion sharing is performed.

[0020] According to the invention of claim 8, according to claim 6,
The circuit characteristic evaluation means in the transistor size determination device of the above, based on the circuit data and technology data and information of the diffusion sharing location estimated by the diffusion sharing estimation means, when using the given transistor size candidate, It is assumed that an area estimating means for estimating the area of the integrated circuit as an evaluation index of its characteristics is provided.

According to the ninth aspect of the present invention, in the sixth aspect,
The circuit characteristic evaluation means in the transistor size determination device of the above, based on the circuit data and technology data and information of the diffusion sharing location estimated by the diffusion sharing estimation means, when using the given transistor size candidate, It is assumed that the apparatus is provided with delay estimating means for estimating and calculating the delay of the integrated circuit as an evaluation index of its characteristic.

According to the tenth aspect of the present invention, the circuit characteristic evaluation means in the transistor size determining apparatus according to the sixth aspect includes the circuit data and the technology data and the information of the diffusion common portion estimated by the diffusion common estimating means. And a power consumption estimating means for estimating the power consumption of the integrated circuit when the given transistor size candidate is used as an evaluation index of its characteristic.

According to another aspect of the present invention, there is provided a circuit characteristic evaluation method for estimating and evaluating characteristics of an integrated circuit to be designed based on circuit data representing a configuration of the integrated circuit. Diffusion sharing estimating step for estimating a location where diffusion sharing is performed in the layout of the integrated circuit when the transistor size is used, technology data representing the circuit data and information relating to a semiconductor manufacturing process, and the diffusion sharing estimation step And a circuit characteristic evaluation step of estimating and evaluating the characteristics of the integrated circuit when the given transistor size is used, based on the information on the diffusion shared portion estimated by the above.

According to the eleventh aspect of the present invention, when the transistor size is given, the location where diffusion sharing is performed is estimated by the diffusion sharing estimation step, and the diffusion sharing estimated by the diffusion sharing estimation step is estimated by the circuit characteristic evaluation step. The characteristics of the integrated circuit in consideration of the location information are estimated and evaluated. For this reason, the circuit characteristic evaluation method is performed on a plurality of types of transistor size candidates, and the optimum transistor size is determined based on the estimation and evaluation results obtained by the circuit characteristic evaluation step, so that the transistor size is determined in consideration of diffusion sharing. It can be performed. Moreover, since it is not necessary to repeat the determination of the transistor size and the compaction as in the conventional case, the optimization of the transistor size can be realized more accurately and in a shorter time than in the conventional case.

According to a twelfth aspect of the present invention, the diffusion sharing estimation step in the circuit characteristic evaluation method according to the eleventh aspect includes connecting two diffusion regions and branches of the transistors connected in series, which are connected to each other. Of two diffusion regions connected to each other of the transistor and one diffusion region of the transistor whose folding is presumed,
It is assumed that at least one is estimated as a place where diffusion sharing is performed.

Further, in the invention of claim 13, the diffusion sharing estimation step in the circuit characteristic evaluation method of claim 11 calculates a probability that diffusion sharing is performed on a net connecting a plurality of diffusion regions. It is assumed that the probability is estimated as the probability that each diffusion region belonging to the net is diffusion-shared.

According to a fourteenth aspect of the present invention, in the circuit characteristic evaluation method according to the eleventh aspect, the circuit characteristic evaluation step includes:
An area estimating step of estimating a layout area of the integrated circuit as an evaluation index of the characteristic, wherein the area estimating step calculates a first area of the transistor estimated not to involve diffusion sharing in the diffusion sharing estimation step; And a second step of calculating the area of the transistor estimated to be accompanied by diffusion sharing in the diffusion sharing estimation step in consideration of a decrease in the transistor area due to diffusion sharing, wherein the first and second steps are performed. The area of the integrated circuit is determined using the area of each transistor calculated in the process.

According to a fifteenth aspect of the present invention, the area estimating step in the circuit characteristic evaluation method according to the fourteenth aspect includes the step of calculating the area of the integrated circuit assuming that the transistors are arranged one-dimensionally. A third layout area, which is calculated as one layout area, and wherein the first layout area and a second layout area, which is the sum of the areas of the respective transistors calculated in the first and second steps, are calculated. Based on this, it is assumed that the layout area of the integrated circuit is estimated.

According to a sixteenth aspect of the present invention, in the circuit characteristic evaluation method of the eleventh aspect, the circuit characteristic evaluation step comprises:
A delay estimating step of estimating a delay of the integrated circuit as an evaluation index of a characteristic thereof, wherein the delay estimating step calculates a capacity of a diffusion region estimated not to involve diffusion sharing in the diffusion sharing estimation step. And a second step of calculating a capacity of the diffusion region estimated to be accompanied by the diffusion sharing in the diffusion sharing estimation step in consideration of a decrease in the diffusion region area due to the diffusion sharing, wherein the first and second steps are performed. It is assumed that the delay of the integrated circuit is obtained by using the capacitance of the diffusion region calculated in the step.

According to a seventeenth aspect of the present invention, in the circuit characteristic evaluation method according to the eleventh aspect, the circuit characteristic evaluation step comprises:
A power consumption estimating step of estimating power consumption of the integrated circuit as an evaluation index of the characteristic, wherein the power consumption estimating step calculates a capacity of the diffusion region estimated not to involve diffusion sharing in the diffusion sharing estimation step. A first step of calculating a capacity of the diffusion region estimated to be accompanied by the diffusion sharing in the diffusion sharing estimation step in consideration of a reduction in the diffusion region area due to the diffusion sharing; The power consumption of the integrated circuit is obtained using the capacitance of the diffusion region calculated in the second step.

A solution according to the invention of claim 18 is a circuit size determining method for determining the size of each transistor when designing a layout of an integrated circuit to be designed. Based on the data, a diffusion sharing estimation step of estimating a location where diffusion sharing is performed in the layout of the integrated circuit when a given transistor size candidate is used, and the circuit data and information related to a semiconductor manufacturing process. A circuit characteristic evaluation step of estimating and evaluating the characteristic of the integrated circuit when the given transistor size candidate is used, based on the technology data and the information on the diffusion sharing part estimated by the diffusion sharing estimation step. And performing the diffusion sharing estimation step and the circuit characteristic evaluation step by using a plurality of types of transistor sizes. Performed for the candidate, based on the estimation result of evaluation by said circuit characterization step, is to determine one of the transistor size.

According to the eighteenth aspect of the present invention, when a transistor size candidate is given, a location where diffusion sharing is performed is estimated by the diffusion sharing estimation step, and the diffusion estimated by the diffusion sharing estimation step is estimated by the circuit characteristic evaluation step. The characteristics of the integrated circuit in consideration of the information on the common part are estimated and evaluated. Therefore, the diffusion sharing estimation step and the circuit characteristic evaluation step are performed for a plurality of types of transistor size candidates, and one transistor size is determined based on the estimation evaluation result obtained by the circuit characteristic evaluation step.
It is possible to determine the transistor size in consideration of diffusion sharing. Moreover, there is no need to repeat the transistor size determination and compaction as in the past,
Optimization of the transistor size can be realized more accurately and in a shorter time than before.

According to a nineteenth aspect of the present invention, in the transistor size determining method according to the eighteenth aspect, the diffusion sharing estimation step and the circuit characteristic evaluation step are performed in such a manner that a predetermined evaluation index is optimized while changing the setting of a transistor size candidate. The transistor size candidate is set and changed with a predetermined change width, and the change width is variable according to a change in the predetermined evaluation index.

[0034]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an integrated circuit layout design apparatus according to one embodiment of the present invention.
In FIG. 1, reference numeral 31 denotes a transistor which constitutes an integrated circuit to be designed, external terminals, and circuit data indicating a connection relationship between them, and 32 denotes information relating to a semiconductor manufacturing process such as a resistance value of the transistor and design constraints. The technology data 10 represents transistor size determination means for optimizing the size and the number of folding steps of each transistor constituting the integrated circuit to be designed from the circuit data 31 and the technology data 32, and 33 is generated by the transistor size determination means 10. Transistor size information representing the size of each transistor constituting the integrated circuit;
Numeral 34 denotes folding step number information indicating the number of folding steps of each transistor constituting the integrated circuit, generated by the transistor size determining means 10, 21 denotes circuit data 31 and technology data 32, and transistors generated by the transistor size determining means 10. An arrangement determining means for arranging the transistors based on the size information 33 and the number-of-folding-stages information 34;
1 and transistor data 3
1 and the technology data 32, a wiring determining means for performing wiring between transistors, 23 is an arrangement determining means 2
1 is an output unit that generates and outputs a layout 35 of the integrated circuit based on the placement and routing result determined by the wiring determination unit 22. Arrangement determining means 21, wiring determining means 2
2 and the output unit 23 constitute a layout unit 20.

FIG. 2 is a block diagram showing the configuration of the transistor size determining means 10 in the integrated circuit layout designing apparatus according to the present embodiment shown in FIG. In FIG. 2, reference numeral 11 denotes circuit data 31 and technology data 32.
A diffusion sharing estimating means for estimating the location of the diffusion sharing due to the turning-back of the transistor, series connection, etc., based on the estimation result of the diffusion sharing estimating means 11 and the circuit data 31 and the technology data 32, the characteristics such as the area of the integrated circuit. And 13 is a transistor size optimizing means for determining an optimum transistor size and the number of folding stages based on the evaluation result of the circuit characteristic evaluating means 12. The circuit characteristic evaluation means 12 includes an area estimation calculation means 12a for estimating and calculating the area of the integrated circuit, a delay estimation calculation means 12b for estimating and calculating the delay of the integrated circuit, and a power consumption estimation calculation means for estimating and calculating the power consumption of the integrated circuit. 12c.

The operation of the layout design apparatus for an integrated circuit according to this embodiment shown in FIG. 1 will be described.

First, based on the circuit data 31 and the technology data 32, the transistor size determining means 10 determines the optimal size and the number of folding stages of each transistor of the integrated circuit.

FIG. 3 is a circuit diagram showing an example of the circuit data 31 and is a diagram used for explaining the present embodiment.
In FIG. 3, tr1 and tr2 are P-type transistors, t1
r3 and tr4 are N-type transistors, A and B are input pins,
C is an output pin. The source of the transistor tr3 is connected to the drain of the transistor tr4, the sources of the transistors tr1 and tr2 are connected to the power supply line Vdd, and the source of the transistor tr4 is connected to the ground line Gnd. Input pin A is connected to transistors tr1 and tr4
And the input pin B is connected to the transistor t
The output pin C is connected to the gates of r2 and tr3, and the output pin C is connected to the drains of the transistors tr1, tr2 and tr3.

FIG. 4 is a diagram showing an example of the technology data 32, and is a diagram used for explaining the present embodiment. In FIG. 4, R0 is the gate resistance per unit length of the transistor, C0 is the diffusion capacitance per unit area, H
p is the height of the P-type well and Hn is the height of the N-type well. Lt is a reference transistor length which is the length of a transistor without diffusion sharing, Ld is a reference diffusion region length which is a length of a diffusion region without diffusion sharing, and S is a diffusion region length with diffusion sharing by serial connection. F is a decrease in diffusion region length due to diffusion sharing due to transistor folding, and P is a decrease in diffusion region length due to diffusion sharing due to connection including branching.

FIG. 5 is a plan view showing a layout of a transistor.
It is a figure for explaining Ld, S, F, and P. In the figure,
(A) is a layout in which diffusion sharing is performed by connection including transistor folding or branching, (b) is a layout in which diffusion sharing is not performed, and (c) is a layout in which diffusion sharing is performed by series connection. Reference numeral 41 denotes a gate of the transistor, 42 denotes a diffusion region of the transistor, 43 denotes an aluminum wiring, and 44 denotes a contact for connecting the diffusion region 42 of the transistor and the aluminum wiring 43.

As shown in FIG. 5C, assuming that the minimum gate length, minimum contact width, minimum gate interval, diffusion region-contact overlap minimum width, and gate-contact minimum interval are given as design constraints. , Each parameter Lt, Ld, S, F,
P is defined as follows. Lt = (minimum gate length) + {(minimum contact width) + (minimum gate-contact distance) + (diffusion region-contact overlap width)} × 2 Ld = (minimum contact width) + (minimum gate-contact distance) + (Diffusion area-contact minimum width) S = Ld- (minimum gate interval) / 2 = (minimum contact width) + (gate-contact minimum interval) + (diffusion area-contact minimum width)-(minimum gate) (Interval) / 2 F, P = Ld-{(minimum contact width) / 2 + (minimum gate-contact distance)} = (minimum contact width) / 2 + (minimum width of diffusion region-contact overlap)

In FIG. 5B, W is the gate width of the transistor.
Shall be represented by

FIG. 6 is a flowchart showing the operation of the transistor size determining means 10 shown in FIG. In FIG. 6, S11 is a step of detecting a transistor that needs to be turned back, a series connection of the transistor, and a connection including a branch from the given transistor size candidate and the circuit data 31 to estimate a diffusion sharing point. A step of performing an estimation calculation of the area of the integrated circuit from the information of the candidate and the diffusion sharing position estimated in step S11; and step S13, a step of calculating from the technology data 32, the transistor size candidate and the information of the diffusion sharing position estimated in step S11. The step of performing an operation of estimating the delay of the integrated circuit, and the step of performing an operation of estimating the power consumption of the integrated circuit from the technology data 32, the candidate transistor size, and the information of the diffusion common portion estimated in step S11. Step S11 constitutes the diffusion sharing estimation step, and step S12
Steps S14 to S14 constitute a circuit characteristic evaluation step. The diffusion sharing estimation step and the circuit characteristic evaluation step constitute a circuit characteristic evaluation method.

There are various optimization methods. In this embodiment, the initial values of the transistor size candidates are appropriately given (step S10), and the values are changed at random (step S17). It is assumed that the transistor size is determined based on the method of trying the improvement. The optimization index is the delay of the critical path, and the transistor size and the number of folding stages are optimized so that the delay of the critical path is minimized.

(Diffusion sharing estimation step) First, step S11
In the above, the diffusion sharing estimation unit 11 estimates a diffusion sharing location between transistors based on circuit data 31 as shown in FIG. 3 and technology data 32 as shown in FIG. Then, at the end of step S11, the diffusion sharing estimating means 11 outputs the information on the number of turn-back steps of the transistor and the diffusion sharing information by connection.

FIG. 7 is a flowchart showing the flow of processing in the diffusion sharing estimation step S11. In FIG.
S11a is a step of estimating a diffusion sharing point by series connection, S11b is a step of estimating a diffusion sharing point by loopback, and S11c is a step of estimating a diffusion sharing point by connection including branching.

For example, in the circuit indicated by the circuit data shown in FIG. 3, diffusion sharing is estimated at the following points.

(1) Series connection of transistors tr3 and tr4 From the connection information of the circuit, the source of transistor tr3 and the drain of transistor tr4 are connected, and the source of transistor tr3 and the transistor tr4
It can be seen that the net connecting to the drain of FIG. 5 has no connection to other transistors or terminals. In this case, in the layout, the source of the transistor tr3 and the drain of the transistor tr4 can be shared by diffusion without contact, and even in an actual layout, the possibility of diffusion sharing without contact is very high. Therefore,
In step S11a, a connection portion between the source of the transistor tr3 and the drain of the transistor tr4 is estimated as a diffusion-shared portion by series connection.

(2) Connection including branch between transistors tr1 and tr2 From the connection information of the circuit, the drain of transistor tr1 is connected to the drain of transistor tr2, and the drain of transistor tr1 is connected to the transistor tr.
It can be seen that the net connecting the drain of No. 2 is connected to the N-type transistor and the terminal, but not to the drain or source of the other P-type transistor. In this case, in the layout, the drain of the transistor tr1 and the drain of the transistor tr2 can be diffused and shared with a contact, and in an actual layout, the possibility of diffusion sharing with a contact is very high. Therefore, in step S11c, the connection between the drains of the transistors tr1 and tr2 is estimated as the location of diffusion sharing by connection including branching.

FIG. 8 shows an example in which the circuit of FIG. 3 is laid out. In FIG. 8, the transistor tr3 and the transistor tr4 involve diffusion sharing without contact, and the transistor tr1 and the transistor tr2 involve diffusion sharing with contact.

FIG. 9 shows another example of the circuit data.
2 shows a circuit having the function of D. In FIG. 9, t
p3, tp4, tp5 are P-type transistors, tn3, t
n4 and tn5 are N-type transistors, A, B and C are input terminals, and Y is an output terminal. In FIG. 9, diffusion sharing is estimated at the following points.

(1) Transistors tp3, tp4, tp
From the connection information of the connection circuit including the branch of 5, the transistors tp3, tp4, t
It can be seen that the drains of p5 are connected.
In this case, in the layout, the transistors tp3 and tp3
Two of the drains of tp4 and tp5 can be diffused and shared with a contact. In an actual layout,
It is very likely that two of the drains of the transistors tp3, tp4 and tp5 are contacted and diffused and shared. Therefore, in step S11c, any two of the transistors tp3, tp4, and tp5 are selected, and the connection between the drains of the selected two transistors is estimated as the location of diffusion sharing by connection including branching. In the actual layout, even if diffusion sharing is performed for a drain different from the drain selected here, a large error does not occur in estimating the diffusion area.

The set of diffusion regions in which diffusion sharing is presumed to be performed may be selected, for example, in descending order of transistor size. This is because the effect of diffusion sharing increases as the transistor size increases.

(2) Transistors tn3, tn4, tn
5, the transistor tn3 and the transistor tn4 and the transistor tn4 and the transistor tn5 are connected in series, respectively, like the transistors tr3 and tr4 in FIG. 3, so that the connection between the transistors tn3 and tn4 and the transistor tn4 It is considered that diffusion sharing without contact is performed at the connection between tn5. Therefore, in step S11a, the connection between the transistors tn3 and tn4 and the connection between the transistors tn4 and tn5 are estimated as the points of diffusion sharing by series connection.

(3) Transistors tn3, tn4, tn
Return of 5 For example, while the arrangement region (N-well) of the N-type transistor has a height of 50, the transistors tn3, tn4,
Assume that the transistor sizes of tn5 are all 80. As in this case, when the transistor size exceeds the height of the well, it is assumed that the transistor is turned back in step S11b.

FIG. 10 is an example in which the circuit of FIG. 9 is laid out. In FIG. 10, transistors tn3, tn4,
tn5 involves diffusion sharing without contact, transistors tp4 and tp5 involve diffusion sharing with contact,
Further, the transistors tn3, tn4 and tn5 are folded back.

FIG. 11 shows an example of the initial value of the transistor size candidate set in step S10, which is for the circuit data shown in FIG. FIG. 11 shows that the size of the transistors tr1, tr3, and tr4 shown in FIG. 3 is 3.0, and the size of the transistor tr2 is 5.0.

In this case, the size of the transistor tr2 is 5.0, and the P well height Hp (= 4.
Since it is longer than 8), it can be estimated that two-stage folding is performed on the transistor tr2. Further, since the transistors tr3 and tr4 are connected in series and there is no branch from the connection point, it can be estimated that the area and the diffusion capacitance can be largely reduced by diffusion sharing. Accordingly, the diffusion sharing estimating means 11 outputs the information on the number of transistor turn-back stages as shown in FIG. 12 and the diffusion sharing information by connection as shown in FIG.

The information on the number of transistor turn-back stages in FIG. 12 indicates that two-stage turn-back is performed on the transistor tr2 and that no turn-on is performed on the transistors tr1, tr3, and tr4. The diffusion sharing information by connection indicates the names of two transistors to which one diffusion sharing is performed and which of the source (S) / drain (D) of each transistor is diffusion shared. Indicates that it is estimated that diffusion sharing is performed between the source of the transistor tr3 and the drain of the transistor tr4.

(Area Estimation) Next, in step S12, the area estimation calculating means 12a uses the transistor size information as shown in FIG. 11, the transistor turn-down information as shown in FIG. 12, and the connection as shown in FIG. An estimation operation of the area of the integrated circuit is performed based on the diffusion sharing information.

FIG. 14 is a flowchart showing the flow of the process of step S12, that is, the method of estimating and calculating the area of the integrated circuit according to the present embodiment. In FIG. 14, S21 is a step of calculating the area of the transistor without diffusion sharing, S22 is a step of calculating the area of the transistor with diffusion sharing due to the folding of the transistor, S2.
3 is a step of calculating the area of the transistor with diffusion sharing by series connection; S24 is a step of calculating the area of the transistor with diffusion sharing by connection including branching;
S25 is a step of calculating the total area of the transistor.

The area occupied by the integrated circuit can be approximated by the sum of the area of the transistor and the area of the wiring. Here, assuming that the area of the wiring is substantially constant, the area of the entire circuit can be evaluated by the sum of the transistor areas. Therefore, in the present embodiment, the transistor tr1 in the circuit data shown in FIG.
Assuming that the areas of tr to tr4 are A1 to A4, respectively, the integrated circuit is evaluated by regarding the total transistor area A represented by A = A1 + A2 + A3 + A4 (1) as the circuit area.

Assuming that the gate width of the transistor i is Wi, the area Ai of the transistor i can be calculated by the following equation when diffusion sharing is not performed. Ai = Lt × Wi (2) On the other hand, when diffusion sharing is performed, the following formulas can be used for the case of series connection, the case of transistor folding, and the case of branch connection. it can. Ai = (Lt−S) × Wi (3) Ai = (Lt−F) × Wi (4) Ai = (Lt−P) × Wi (5)

First, in step S21, the area of the transistor without diffusion sharing, ie, the transistor tr1, is calculated. The area A1 of the transistor tr1 is as follows according to the equation (2). A1 = Lt × W1 = 1.3 × 3.0 = 3.9

Next, in step S22, the area of the transistor tr2, which is assumed to be a two-stage folded transistor, that is, a transistor with diffusion sharing by folding is calculated.
The area A2 of the transistor tr2 is as follows according to the equation (4). A2 = (Lt−F) × W2 = (1.3−0.3) × 5.0 = 5.0

Next, in step S23, the area of the transistors with diffusion sharing by serial connection, ie, the transistors tr3 and tr4, is calculated. Transistor tr
Areas A3 and A4 of 3, tr4 are as follows according to equation (3). A3 = (Lt−S) × W3 = (1.3−0.4) × 3.0 = 2.7 A4 = (Lt−S) × W4 = (1.3−0.4) × 3.0 = 2.7

Next, in step S24, the area of the transistor accompanied by the diffusion sharing by the connection including the branch is calculated. According to the diffusion sharing information by the connection shown in FIG. 13, there is no transistor associated with the diffusion sharing by the connection including the branch. Proceed to the next step.

Finally, in step S25, the total area of the transistors is calculated. The total area A of the transistor can be calculated as A = A1 + A2 + A3 + A4 = 3.9 + 5.0 + 2.7 + 2.7 = 14.3 by equation (1). FIG. 15 shows area calculation result data obtained by the above calculation.

The feature of the area estimation calculation method according to the present embodiment is that an accurate area calculation can be performed in consideration of the reduction of the diffusion region due to diffusion sharing. If here
When the total area A of the transistor is calculated without considering the diffusion sharing at all, A = 1.3 × (3.0 + 5.0 + 3.0 + 3.0) = 18.2, and the diffusion sharing is performed as in the present embodiment. , An area of about 30% is extra-estimated as compared with the case in which is considered.

(Delay Estimation) Next, in step S13, the delay estimation calculating means 12b uses the transistor size information as shown in FIG. 11, the transistor turn-up stage information as shown in FIG. 12, and the diffusion by connection as shown in FIG. A delay estimation operation in the integrated circuit is performed based on the shared information.

FIG. 16 is a flow chart showing the flow of the process in step S13, that is, the method for estimating the delay of the integrated circuit according to the present embodiment. In FIG. 16, S31 is a step of calculating the capacitance of the diffusion region without diffusion sharing, S32 is a step of calculating the capacitance of the diffusion region with diffusion sharing by turning back the transistor, and S33 is diffusion sharing by serial connection of transistors. , A step of calculating the capacitance of the diffusion region accompanied by diffusion sharing by connection including branching of the transistor, and S35 is a step of calculating a delay.

In the circuit data shown in FIG. 3, the delay to be calculated is determined as follows. Da / f: from input (A, B) = (rise, 1) to output C = fall Db / f: from input (A, B) = (1, rise) to output C = fall Da / r: input ( A, B) = (fall, 1) to output C = rise Db / r ... from input (A, B) = (1, fall) to output C = rise

The delay of the circuit can be approximated by the sum of RC products.
Assuming that the output capacitance is 0 and the input drive capability is ∞ for simplicity, and the wiring capacitance and wiring resistance can be ignored, then Da / f = R4 × (C3s + C4d) + (R4 + R3)
× (C1d + C2d + C3d) Db / f = (R4 + R3) × (C1d + C2d + C3
d) Da / r = R1 × (C1d + C2d + C3d) Db / r = R2 × (C1d + C2d + C3d) Here, C3s is the source capacitance of the transistor tr3, C1d, C2d, C3d, and C4d are the drain capacitances of the transistors tr1, tr2, tr3, and tr4, respectively, and R1, R2, R3, and R4 are the transistors tr1, tr2, tr3, and tr4, respectively. This is the gate resistance.

First, in step S31, a diffusion region without diffusion sharing, that is, transistors tr1 and tr3
Calculation of the drain capacitance of. Since the value of the diffusion capacitance C0 per unit area is 1.0 from the technology data of FIG. 4, the drain capacitance C0 of the transistors tr1 and tr3
1d and C3d are respectively C1d = C0 × Ld × W1 = 1.0 × 0.6 × 3.0 = 1.8 C3d = C0 × Ld × W3 = 1.0 × 0.6 × 3.0 = 1 .8.

Next, in step S 32, calculation of the diffusion region with diffusion sharing due to the turning back of the transistor, that is, the capacitance of the drain of the transistor tr 2 is performed. The drain capacitance C2d of the transistor tr2 is as follows: C2d = C0 × (Ld−F) × W2 = 1.0 × (0.6−0.3) × 5.0 = 1.5

Next, in step S33, the capacity of the diffusion region associated with the diffusion sharing due to the series connection of the transistors, ie, the capacitance of the source of the transistor tr3 and the drain of the transistor tr4 is calculated. The source capacitance C3s of the transistor tr3 and the drain capacitance C4d of the transistor tr4 are as follows: C4d = C0 × (Ld−S) × W4 = 1.0 × (0.6−0.4) × 3.0 = 0.6 C3s = C0 × (Ld−S) × W3 = 1.0 × (0.6−0.4) × 3.0 = 0.6.

Next, in step S34, the capacity of the diffusion region accompanied by the diffusion sharing by the connection including the branch of the transistor is calculated. According to the diffusion sharing information shown in FIG. No, go to the next step.

Finally, in step S35, the delay of the circuit is calculated. Since the value of the gate resistance R0 per unit length is 30 from the technology data of FIG. 4, the gate resistances R1 to R4 are: R1 = R0 / W1 = 30 / 3.0 = 10 R2 = R0 / W2 = 30 / 5.0 = 6 R3 = R0 / W3 = 30 / 3.0 = 10 R4 = R0 / W4 = 30 / 3.0 = 10 Therefore, the circuit delay is obtained as follows. Da / f = 10 × (0.6 + 0.6) + (10 + 10) × (1.8 + 1.5 + 1.8) = 114 Db / f = (10 + 10) × (1.8 + 1.5 + 1.8) = 102 Da /R=10×(1.8+1.5+1.8)=51 Db / r = 6 × (1.8 + 1.5 + 1.8) = 30.6 FIG. 17 shows delay calculation result data obtained by the above calculation. FIG. 17 shows that the value of the delay of the critical path is 114.

A feature of the delay estimation calculation method according to the present embodiment is that accurate delay calculation can be performed in consideration of the amount of reduction in the diffusion capacity due to diffusion sharing.

Here, if the calculation is performed without considering the diffusion sharing at all, the drain capacitance C2 of the transistor tr2 is calculated.
d, the drain capacitance C4d of the transistor tr4, and the source capacitance C3s of the transistor tr3, respectively, C2d = C0 × Ld × W2 = 1.0 × 0.6 × 5.0 = 3.0 C4d = C0 × Ld × W4 = 1.0 × 0.6 × 3.0 = 1.8 C3s = C0 × Ld × W3 = 1.0 × 0.6 × 3.0 = 1.8 Therefore, the value of each delay is Da / f = 10 × (1.8 + 1.8) + (10 + 10) × (1.8 + 3.0 + 1.8) = 168 Db / f = (10 + 10) × (1.8 + 3.0 + 1.8) = 132 Da / r = 10 × (1.8 + 3.0 + 1.8) = 66 Db / r = 6 × (1.8 + 3.0 + 1.8) = 39.6, as compared with the case where diffusion sharing is considered as in the present embodiment. An extra 30% to 50% extra delay will be estimated.

(Estimation of Power Consumption) Next, in step S14, the power consumption estimation calculation means 12c estimates and calculates the power consumption of the entire circuit.

FIG. 18 is a flowchart showing the flow of the process in step S14, that is, the method for estimating and calculating the power consumption of the integrated circuit according to the present embodiment. In FIG. 18, S4
1 is a step of calculating the capacitance of the diffusion region without diffusion sharing, S42 is a step of calculating the capacitance of the diffusion region with diffusion sharing by turning back the transistor, S43.
Is a step of calculating the capacity of the diffusion region accompanied by diffusion sharing by series connection of the transistors, S44 is a step of calculating the capacity of the diffusion region accompanied by diffusion sharing by the drain connection of the transistor, and S45 is the charge / discharge of each diffusion region. The step of calculating the probability, S46, is a step of calculating the average power consumption of the entire circuit. Steps S41 to S
Step S44 in the delay estimating calculation shown in FIG.
This is the same processing as 31 to S34. That is, step S
In steps S41 to S44, the capacity of each diffusion region is calculated. In step S45, the charge / discharge probability of each diffusion region is calculated. In step S46, the average consumption of the entire circuit is calculated using the capacity and charge / discharge probability of each diffusion region. Calculate the power.

Returning to FIG. 6, in step S15, the optimum transistor size and the number of folding steps are selected. However, since only the initial value has been evaluated here, steps S17 through S16 are performed.
And the transistor size optimizing means 13
A new transistor size candidate is set. In the present embodiment, it is assumed that the setting of the transistor size candidates is performed at random.

FIG. 19 is a diagram showing newly set transistor size information. The transistors tr1 and tr
The sizes of 2, 2, tr3, and tr4 are 4.4, 4,.
5, 3.0, and 3.0.

Next, in step S11, step S
Based on the transistor size candidate set in step 17, the diffusion sharing estimating means 11 estimates the number of transistor folding stages and the location of diffusion sharing in the integrated circuit.

In this case, since the size of each transistor is shorter than the P well height Hp (= 4.8), it is presumed that there is no transistor to be folded. Although the transistors tr1 and tr2 are not connected in series, since the drains are connected to each other and there is no other transistor that can perform diffusion sharing, it can be estimated that the area and the diffusion capacitance can be reduced by the diffusion sharing. Therefore, the diffusion sharing means 11 outputs the information on the number of transistor turn-back stages as shown in FIG. 20 and the diffusion sharing information by connection as shown in FIG.

The information on the number of transistor turn-around stages shown in FIG. 20 indicates that no turn-back is performed on the transistors tr1 to tr4. The diffusion sharing information by the connection shown in FIG. 21 indicates that it is estimated that diffusion sharing is performed between the source of the transistor tr3 and the drain of the transistor tr4, and between the drain of the transistor tr1 and the drain of the transistor tr2.

Next, in step S12, the area estimating means 12a outputs the transistor size information shown in FIG. 19, the transistor folding stage number information shown in FIG.
Based on the diffusion sharing information shown in FIG. 21, an estimation calculation of the area of the integrated circuit is performed.

Since it is presumed that the transistors tr1 and tr2 perform diffusion sharing of the drain, the areas A1 and A2 of the transistors tr1 and tr2 are as follows according to the equation (5).

A1 = (Lt−P) × W1 = (1.3−0.3) × 4.4 = 4.4 A2 = (Lt−P) × W2 = (1.3−0.3) × 4.5 = 4.5 Since it is estimated that the transistors tr3 and tr4 perform diffusion sharing by series connection, the areas A3 and A4 of the transistors tr3 and tr4 are as follows according to the equation (3). A3 = (Lt−S) × W3 = (1.3−0.4) × 3.0 = 2.7 A4 = (Lt−S) × W4 = (1.3−0.4) × 3.0 = 2.7 Therefore, the total area A of the transistor can be calculated as A = A1 + A2 + A3 + A4 = 4.4 + 4.5 + 2.7 + 2.7 = 14.3 by equation (1). FIG. 22 shows the area calculation result data obtained as described above.

Next, at step S13, the delay estimation calculating means 12b uses the transistor size information shown in FIG. 19, the transistor turn-up stage information shown in FIG.
The delay is calculated based on the spread sharing information shown in FIG.

Since the diffusion capacitance C0 per unit area is 1.0 from the technology data of FIG. 4, the drain capacitance C3d of the transistor tr3 without diffusion sharing is as follows. C3d = C0 × Ld × W3 = 1.0 × 0.6 × 3.0 = 1.8

Since it is estimated that the drains of the transistors tr1 and tr2 share the diffusion, the drain capacitances C1d and C2d of the transistors tr1 and tr2 are as follows. C1d = C0 × (Ld−P) × W1 = 1.0 × (0.6−0.3) × 4.4 = 1.32 C2d = C0 × (Ld−P) × W2 = 1.0 × ( 0.6−0.3) × 4.5 = 1.35

Since it is presumed that the transistors tr3 and tr4 perform diffusion sharing by series connection, the source capacitance C3s of the transistor tr3 and the drain capacitance C4d of the transistor tr4 are as follows.

C4d = C0 × (Ld−S) × W4 = 1.0 × (0.6−0.4) × 3.0 = 0.6 C3s = C0 × (Ld−S) × W3 = 1. 0 × (0.6−0.4) × 3.0 = 0.6

Since the gate resistance R0 per unit length is 30 from the technology data of FIG. 4, the gate resistance R1
R1 = R0 / W1 = 30 / 4.4 = 6.82 R2 = R0 / W2 = 30 / 4.5 = 6.67 R3 = R0 / W3 = 30 / 3.0 = 10 R4 = R0 /W4=30/3.0=10. Therefore, the circuit delay is obtained as follows. Da / f = 10 × (0.6 + 0.6) + (10 + 10) × (1.32 + 1.35 + 1.8) = 101.4 Db / f = (10 + 10) × (1.32 + 1.35 + 1.8) = 89.4 Da / r = 6.82 × (1.32 + 1.35 + 1.8) = 30.5 Db / r = 6.67 × (1.32 + 1.35 + 1.8) = 29.8 FIG. This is delay calculation result data obtained by such calculation. FIG. 23 shows that the critical path delay value is 10
1.4.

A comparison between FIG. 17 and FIG. 23 shows that FIG. 23 has a smaller critical path delay value. That is, focusing only on the critical path, the transistor size candidates shown in FIG. 19 are more suitable for the integrated circuit of FIG. 3 than the transistor size candidates shown in FIG. Therefore, in step S15, the transistor size shown in FIG. 19 and the number of folding steps shown in FIG. 20 are selected as the optimal solution up to the present.

By repeating the same processing, it is possible to obtain a further optimal transistor size and the number of folding steps.

According to the method described above, the transistor size determining means 10 determines the optimum size and the number of folding stages of each transistor of the integrated circuit, and generates the transistor size information 33 and the number of folding stages 34.

The feature of the transistor size determination method according to the present embodiment is that the evaluation of the characteristics of the integrated circuit in consideration of the diffusion sharing, that is, the estimation of the area, the delay, and the power consumption is carried out, whereby the size of the transistor and the number of folding stages are obtained. Can be optimized with higher accuracy.

Next, based on the transistor size information 33 and the folding stage number information 34 thus generated,
Layout 35 of integrated circuit by layout means 20
Generate First, the transistors are arranged by the arrangement determining means 21. This can be performed using the method disclosed in Japanese Patent Application Laid-Open No. 9-298243. Next, wiring between transistors is performed by the wiring determining means 22. this is,
It can be performed by using the method disclosed in JP-A-8-83302. Finally, the output unit 23 generates and outputs the layout 35 based on the placement and routing results.

FIG. 24 is a diagram showing an example of a layout generated by the layout means 20. The circuit data shown in FIG. 3 is laid out based on the transistor size information shown in FIG. 11 and the number of transistor folding stages shown in FIG. FIG. In FIG. 24, tr1, tr2, tr3, and tr4 are transistors, A and B are input terminals, and C is an output terminal.

As described above, according to the layout design apparatus for an integrated circuit according to the present embodiment, the transistor size and the number of folding stages can be optimized before the layout is performed. An excellent layout result can be generated in a short time.

(Modification of Spread-Sharing Estimation) In the spread-sharing estimation, when estimating the spread-sharing due to the connection including the branch, the estimation may be performed in consideration of the probability of the spread-sharing.

First, the number of unshared diffusion regions in which diffusion sharing by serial connection or return sharing is not estimated, which can be shared by connection including branching, is estimated. Since diffusion sharing is performed in a one-dimensional direction, the number of diffusion sharing portions does not exceed the number of diffusion islands, which are clusters of diffusion regions. Therefore, assuming that the number of unshared diffusion regions is ネ ッ ト Nends and the number of diffusion islands to which the unshared diffusion regions belong is ΣNtr in a net connecting the diffusion regions, the number of diffusion regions Nshare that can be diffusion-shared satisfies the following equation. The largest even number. Nshare ≦ Nends Nshare ≦ 2 (ΣNtr−1)

The number N of diffusion regions that can be shared by diffusion obtained by the above equation
From the share, the probability Pshare that diffusion sharing occurs for each unshared diffusion region can be calculated by the following equation. Pshare = Nshare / ΣNends

When the above-mentioned probability Pshare is used for an evaluation function of a circuit such as an area and a capacitance, assuming that the evaluation function when the diffusion sharing is performed is Ea and the evaluation function when the diffusion sharing is not performed is Eb, the following is obtained. By the formula
What is necessary is just to calculate the evaluation function Ec using a probability. Ec = Ea · Pshare + Eb · (1-Psha
e)

FIG. 25 shows an example of a layout having a connection including a branch. FIG.
(B) shows the state after diffusion sharing. With respect to the net Na in FIG. 25, five connected diffusion regions D1
Since the diffusion region D5 among the diffusion regions D5 to D5 has already been diffused and shared, the number of unshared diffusion regions ΣNends is 4. Further, since the number of diffusion islands ｔNtr is 3, Nshare ≦ ΣNends = 4 Nshare ≦ 2 (ΣNtr−1) = 2 (3-1) = 4, and the value of Nshare is 4 as the largest even number that satisfies the above equation. become. That is, in this case, the probability Pshar
e is: Pshare = Nshare / ΣNends = 4/4 =
1 and the unshared diffusion regions D1 to D4 of the net Na are always diffused and shared. As a result of the diffusion sharing, the layout becomes, for example, as shown in FIG.

FIGS. 26A and 26B show another example of a layout having a connection including a branch. FIG. 26A shows the layout before the diffusion sharing, and FIG. 26B shows the layout after the diffusion sharing. Regarding the net Nb in FIG. 26, the four connected diffusion regions D6 to D9 are not all diffusion-shared, so the number of unshared diffusion regions / Nends is 4. Also, since the number of diffusion islands ΣNtr is 2, Nshare ≦ ΣNends = 4 Nshare ≦ 2 (ΣNtr−1) = 2 (2-1) = 2, and the value of Nshare is 2 as the largest even number that satisfies the above equation. Become. That is, in this case, the probability Pshar
e is: Pshare = Nshare / ΣNends = 2/4 =
0.5, and the probability that each of the diffusion regions D6 to D9 of the net Nb is shared by diffusion is 0.5. As a result of the diffusion sharing, the layout becomes, for example, as shown in FIG.

(Modification of Area Estimation) When designing the layout of an integrated circuit, if the number of transistors included in the integrated circuit is sufficiently large and the arrangement region is sufficiently wide in the vertical and horizontal directions, the transistors can be freely arranged two-dimensionally. It is arranged to be spread. On the other hand, when the arrangement region is not so high with respect to the transistor size, the transistors are arranged almost one-dimensionally.

In the present modification, in consideration of the above, an area estimation model assuming that transistors are arranged one-dimensionally and an area estimation model assuming that transistors are arranged two-dimensionally are combined. Then, the layout area of the integrated circuit is estimated.

FIG. 27 is a flowchart showing an area estimation step according to this modification. In the area estimating process according to the present modification shown in FIG. 27, steps S26 and S27 are executed as a preceding process, and step S28 is executed as a post process, with respect to step S12 which is the area estimating process according to the present embodiment shown in FIG. Execute

FIG. 28 is a diagram showing an area estimation model in a one-dimensional transistor arrangement according to this modification. FIG.
, Tr1 to tr5 are transistors, 1 is an arrangement region, 2 is a diffusion region, 3 is a gate of the transistor, and 4 is a contact. The transistor tr1 is folded back and shared in two steps, and the transistor tr4 is folded back and shared in three steps.
r3 is connected in series and shared by diffusion. As shown in FIG. 28, when the arrangement region height H0 is not so large as compared to the transistor size, most transistors are arranged one-dimensionally. In an actual integrated circuit layout, transistors are often arranged as shown in FIG.

In the area estimation model shown in FIG. 28, layout area A1 (first layout area) of the integrated circuit
Is obtained by the following equation. A1 = H0ΣLtr (11) or A1 = H0ΣNtr (12) where Ltr is the diffusion region length of each transistor, Nt
r is the number of folding stages of each transistor. FIG. 28 shows the number of turns Ntr and the length Ltr of the diffusion region for the transistors tr1 to tr5.

In equation (11), the product of the wiring region height H0 and the sum of the diffusion region lengths Ltr calculated for each transistor is estimated as the layout area A1. Equation (12)
Then, the product of the wiring region height H0 and the sum of the number Ntr of folding steps of each transistor is estimated as the layout area A1.

In such an area estimation model, the layout area A
1 is increased. Therefore, when the transistor size is optimized using this model, there is a high possibility that a large number of transistors having the same size as the arrangement region height H0 will be generated. Gaps can be minimized.

In this modification, in step S26,
The length of the diffusion region is estimated in consideration of the diffusion sharing, and in step S27, the layout area when a one-dimensional arrangement is assumed is estimated using the diffusion region length obtained in step S26.

On the other hand, in the model assuming that the transistors are arranged two-dimensionally, the layout area A of the integrated circuit
2 (second layout area) can be estimated by the sum of the transistor area and the wiring area. The sum of the transistor areas in consideration of the diffusion sharing is calculated in step S
Required by 12.

The layout area A of the actual integrated circuit and 1
The following relationship holds between the estimated area A1 in the two-dimensional arrangement model and the estimated area A1 in the two-dimensional arrangement model. A2 ≦ A ≦ A1 That is, the layout area A is equal to the area A2 when the transistors can be arranged without gaps, and equal to the area A1 when the transistors are arranged one-dimensionally without the gaps.

Therefore, in this modification, step S2
8, in order to reflect the characteristics of both the one-dimensional arrangement and the two-dimensional arrangement in the estimation of the layout area, the layout area A is determined by the following equation. A = (1−α) · A1 + α · A2 (0 ≦ α ≦ 1) Here, α sets the degree of reflection of the estimated area A1 in the one-dimensional layout model and the estimated area A2 in the two-dimensional layout model on the layout area A. Parameter, and here, an empirical value is used. As a result, the layout area of the actual integrated circuit can be better approximated.

Note that, depending on design conditions, step S2
6, only S27 may be executed and the estimated area in the one-dimensional arrangement model may be used as it is as the layout area.

(Modification of Transistor Size Optimization) In the evaluation of the circuit characteristics according to the present embodiment, the evaluation index such as the delay sometimes changes discontinuously due to the occurrence of the folding of the transistor due to the change in the transistor size. is there. For this reason, the relationship between the transistor size and the evaluation index is not always a continuous function, and each transistor size candidate is initially set to the minimum size, as in the related art.
After that, in the method of gradually increasing the number, a local solution may be generated at a discontinuous point. Therefore,
It is not always possible to determine the optimal transistor size.

Therefore, in this modification, the generation of the local solution is avoided by making the range of setting change of the transistor size candidate variable. FIG. 29 is a graph schematically showing a transistor size optimization algorithm according to this modification. In FIG. 29, the vertical axis represents delay, and the horizontal axis represents transistor size. The transistor size optimizing algorithm according to the present modification will be described with reference to FIG.

First, a transistor size candidate is set to the minimum size W0 allowed by design constraints. Next, the ratio of the delay decrease to the increase when the transistor size candidate is increased by a predetermined value, that is, the delay reduction coefficient (corresponding to the arrow V0) is obtained. When this delay reduction coefficient is positive (that is, the delay decreases). ), The transistor size candidates are increased by the predetermined value. Such processing is repeated until the delay reduction coefficient becomes negative.

When the delay reduction coefficient becomes negative, a plurality of values for increasing the transistor size candidates are further set as change width candidates, and the delay reduction coefficients are obtained for each set value. , And the maximum set value is determined as the change width of the transistor size candidate. For example, as shown in FIG. 29, when the delay is minimized due to the occurrence of aliasing in the transistor size candidate Wa, the delay reduction coefficient (corresponding to the arrow Va) becomes negative, so that the values ΔW1, ΔW2, and ΔW3 are candidates for the change width. Set. Of the delay reduction coefficients (corresponding to arrows V1, V2, and V3, respectively) corresponding to the respective set values ΔW1, ΔW2, and ΔW3, the largest value corresponds to the value ΔW2, and thus the change width of the transistor size candidate is Select the value ΔW2.

The above processing is continuously performed until the delay constraint is satisfied or the area limit is reached.

As described above, according to the optimization algorithm according to the present modification, by making the setting change width of the transistor size candidate variable, it is possible to avoid the occurrence of a local solution. can do.

The present invention as described above determines the optimal transistor size in an integrated circuit, and minimizes the area and power consumption in accordance with the operating frequency of the integrated circuit, and delays in accordance with the area. Performance can be optimized. Therefore, the present invention has a great merit especially for library development.

The frequency of development of libraries such as standard cells and function macros has increased due to rapid progress in processes, and the diversification of designs has led to the development of low-power consumption or high-performance libraries. The need for libraries is also growing. However, it is important to develop a library based on a new process in a short period of time in order to start designing an integrated circuit based on a new process at an early stage. Therefore, reducing the number of library development steps has become a major issue. I have.

According to the present invention, it is possible to optimize the transistor size which largely affects the cell area and performance, so that it is possible to reduce the number of library development steps and to improve the performance of the library. it can.

[0132]

As described above, according to the integrated circuit layout designing apparatus of the present invention, the optimum transistor size and the number of folding stages can be optimized before the layout is performed. The result can be obtained in a short time.

Further, according to the apparatus and method for determining the transistor size of the present invention, the transistor size can be determined in consideration of diffusion sharing, so that a more accurate transistor optimization than before can be realized. Further, even without layout, it is possible to estimate the area of the integrated circuit in consideration of the reduction in transistor area due to diffusion sharing, and to estimate the delay and power consumption in consideration of the reduction in diffusion capacitance due to diffusion sharing. In addition, optimization of the transistor size can be realized in a shorter time than before.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an integrated circuit layout design apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a transistor size determining unit 10 in the layout design apparatus for an integrated circuit according to one embodiment of the present invention, that is, a transistor size determining apparatus according to one embodiment of the present invention.

FIG. 3 is a circuit diagram showing an example of circuit data.

FIG. 4 is a diagram showing an example of technology data.

FIG. 5 is a plan view showing a layout of a transistor and a diagram for explaining parameters of technology data. FIG. 5 (a) shows a layout in the case of performing transistor sharing or diffusion sharing by drain connection.
(B) Layout without diffusion sharing, (c)
Is a layout when diffusion sharing is performed by series connection.

FIG. 6 is a flowchart showing an operation of the transistor size determining means 10 shown in FIG. 2, that is, a transistor size determining method according to an embodiment of the present invention.

FIG. 7 is a flowchart showing a process flow of a diffusion sharing estimation step in the transistor size determination method shown in FIG. 6;

FIG. 8 is an example of a circuit layout indicated by the circuit data in FIG. 3;

FIG. 9 illustrates another example of circuit data, which is a circuit having a NAND function.

10 is an example of a circuit layout indicated by the circuit data in FIG. 9;

FIG. 11 is a diagram showing initial values of transistor size candidates for the circuit data shown in FIG. 3;

FIG. 12 is an example of transistor folding stage number information.

FIG. 13 is an example of spread sharing information by connection.

FIG. 14 is a flowchart illustrating a method for estimating the area of an integrated circuit according to an embodiment of the present invention.

FIG. 15 shows calculation result data obtained by the method for estimating and calculating the area of the integrated circuit shown in FIG. 14;

FIG. 16 is a flowchart illustrating a method of estimating delay of an integrated circuit according to an embodiment of the present invention.

FIG. 17 shows calculation result data obtained by the calculation method for estimating delay of the integrated circuit shown in FIG. 16;

FIG. 18 is a flowchart illustrating a method for estimating and calculating power consumption of an integrated circuit according to an embodiment of the present invention.

FIG. 19 is a diagram showing transistor size candidates newly set for the circuit data shown in FIG. 3;

FIG. 20 is a diagram illustrating changed information on the number of transistor folding stages.

FIG. 21 is a diagram showing an example of spread sharing information by connection.

FIG. 22 shows calculation result data obtained by the calculation method for estimating the area of the integrated circuit shown in FIG. 14;

FIG. 23 shows calculation result data obtained by the calculation method for estimating delay of the integrated circuit shown in FIG. 16;

24 is a diagram showing an example of a layout generated by the layout means 20. FIG. 24 shows a result of layout performed on the circuit data of FIG. 3 based on the transistor size information shown in FIG. FIG.

FIG. 25 is a diagram for explaining spread sharing estimation according to a modification of the present invention, and is an example of a layout having a connection including a branch, in which (a) is a diagram before spread sharing; , (B) show the result after diffusion sharing.

FIG. 26 is a diagram for explaining diffusion sharing estimation according to a modification of the present invention, and is an example of a layout having a connection including a branch, in which FIG. , (B) show the result after diffusion sharing.

FIG. 27 is a flowchart showing area estimation according to a modification of the present invention.

28 is a diagram showing an area estimation model assuming a one-dimensional arrangement in the area estimation shown in FIG. 27;

FIG. 29 is a graph schematically showing a transistor size optimization algorithm according to a modification of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Transistor size determination means 11 Diffusion sharing estimation means 12 Circuit characteristic evaluation means 12a Area estimation calculation means 12b Delay estimation calculation means 12c Power consumption estimation calculation means 13 Transistor size optimization means 20 Layout means 31 Circuit data 32 Technology data 33 Transistor size information 34 Folding step number information 35 Layout

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 27/04 G06F 17/50 H01L 21/82 H01L 21/822

Claims (19)

(57) [Claims] 1. An integrated circuit layout designing apparatus for inputting circuit data representing a configuration of an integrated circuit to be designed and technology data representing information relating to a semiconductor manufacturing process, and designing a layout of the integrated circuit. Based on circuit data and technology data, the size and the number of folding stages of each transistor constituting the integrated circuit are estimated and evaluated while estimating the characteristics of the integrated circuit.
A transistor size determining means to be determined; circuit data and technology data; and a transistor size and the number of folding steps determined by the transistor size determining means. A layout means for generating a layout of the integrated circuit. 2. The integrated circuit layout designing apparatus according to claim 1, wherein said transistor size determining means diffuses in a layout of said integrated circuit when a given transistor size candidate is used based on said circuit data. When using the given transistor size candidate based on diffusion sharing estimating means for estimating a location where sharing is performed, and the circuit data and technology data and information on the diffusion sharing location estimated by the diffusion sharing estimating means Circuit characteristic estimating means for estimating and evaluating the characteristics of the integrated circuit; and a transistor size candidate for the integrated circuit provided to the diffusion sharing estimating means and the circuit characteristic evaluating means, and the circuit characteristic estimating means is selected from the given transistor size candidates One transistor size based on the estimation Layout designing apparatus for an integrated circuit, characterized in that it comprises a transistor size optimization means. 3. The integrated circuit layout designing apparatus according to claim 2, wherein the circuit characteristic evaluation unit is configured to perform the following on the basis of the circuit data and the technology data and the information of the diffusion sharing location estimated by the diffusion sharing estimation unit. An integrated circuit layout designing apparatus, comprising: an area estimating means for estimating an area of the integrated circuit when the given transistor size candidate is used as an evaluation index of its characteristic. 4. The integrated circuit layout designing apparatus according to claim 2, wherein the circuit characteristic evaluation unit is configured to perform the following based on the circuit data and the technology data and information on the diffusion sharing location estimated by the diffusion sharing estimation unit. An integrated circuit layout designing apparatus, comprising: delay estimation calculating means for estimating and calculating a delay of the integrated circuit when the given transistor size candidate is used as an evaluation index of its characteristic. 5. The integrated circuit layout designing apparatus according to claim 2, wherein the circuit characteristic evaluation unit is configured to perform the following based on the circuit data and the technology data and information on the diffusion sharing location estimated by the diffusion sharing estimation unit. An integrated circuit layout designing apparatus, comprising: a power consumption estimating means for estimating the power consumption of the integrated circuit when the given transistor size candidate is used as an evaluation index of the characteristic. 6. A transistor size determining device which receives circuit data representing a configuration of an integrated circuit to be designed and technology data representing information relating to a semiconductor manufacturing process and determines the size of each transistor of said integrated circuit. Diffusion sharing estimating means for estimating a location where diffusion sharing is performed in a layout of the integrated circuit when a given transistor size candidate is used based on the circuit data; and the circuit data and technology data and the diffusion sharing Circuit characteristic evaluation means for estimating and evaluating the characteristics of the integrated circuit when the given transistor size candidate is used, based on the information on the diffusion sharing portion estimated by the estimation means, and a transistor size candidate for the integrated circuit. Given to the diffusion sharing estimation means and the circuit characteristic evaluation means, A transistor size optimizing means for selecting one transistor size from the transistor size candidates based on the estimation evaluation result by the circuit characteristic evaluation means. 7. The transistor determining apparatus according to claim 6, wherein the diffusion sharing estimation means includes: a transistor connected in series with two diffusion regions connected to each other;
A transistor size determining device for estimating at least one of two diffusion regions connected to each other and one diffusion region of a transistor whose folding is estimated as a portion where diffusion sharing is performed. 8. The transistor size determining apparatus according to claim 6, wherein said circuit characteristic evaluation means is configured to provide said circuit characteristic based on said circuit data and technology data and information on a diffusion sharing position estimated by said diffusion sharing estimation means. A transistor size determining device, comprising: an area estimating operation means for estimating and calculating an area of the integrated circuit when the obtained transistor size candidate is used as an evaluation index of its characteristic. 9. The transistor size determination device according to claim 6, wherein said circuit characteristic evaluation means is configured to provide said circuit characteristic evaluation means based on said circuit data and technology data and information on a diffusion sharing position estimated by said diffusion sharing estimation means. A transistor size determining device for estimating a delay of the integrated circuit when the obtained transistor size candidate is used as an evaluation index of the characteristic thereof. 10. The transistor size determining apparatus according to claim 6, wherein said circuit characteristic evaluation means is configured to provide said circuit characteristic based on said circuit data and technology data and information on a diffusion sharing position estimated by said diffusion sharing estimation means. And a power consumption estimating means for estimating the power consumption of the integrated circuit when the obtained transistor size candidate is used as an evaluation index of the characteristic of the integrated circuit. 11. A circuit characteristic evaluation method for estimating and evaluating characteristics of an integrated circuit to be designed, the method comprising: using a given transistor size based on circuit data representing a configuration of the integrated circuit; A diffusion sharing estimation step of estimating a location where diffusion sharing is performed in the layout of the integrated circuit; and technology data representing the circuit data and information relating to the semiconductor manufacturing process and information of the diffusion sharing location estimated by the diffusion sharing estimation step. And estimating and evaluating the characteristics of the integrated circuit based on the given transistor size based on the given transistor size. 12. The circuit characteristic evaluation method according to claim 11, wherein the step of estimating the shared diffusion includes the steps of: connecting two diffusion regions connected to each other and a transistor connected including a branch;
A circuit characteristic evaluation, wherein at least one of two diffusion regions connected to each other and one diffusion region of a transistor whose folding is estimated is estimated as a portion where diffusion sharing is performed. Method. 13. The circuit characteristic evaluation method according to claim 11, wherein the diffusion sharing estimation step calculates a probability that diffusion sharing is performed for a net connecting a plurality of diffusion regions, and calculates the probability of the network sharing. A circuit area evaluation method for estimating the probability that each diffusion region belonging to the group is shared by diffusion. 14. The circuit characteristic evaluation method according to claim 11, wherein the circuit characteristic evaluation step includes an area estimation step of estimating a layout area of the integrated circuit as an evaluation index of the characteristic. A first step of calculating an area of a transistor estimated not to involve diffusion sharing in the diffusion sharing estimation step; and a transistor area estimated by diffusion sharing in the diffusion sharing estimation step. And calculating the area of the integrated circuit using the area of each transistor calculated in the first and second steps. Circuit characteristic evaluation method. 15. The circuit characteristic evaluation method according to claim 14, wherein, in the area estimating step, an area of the integrated circuit assuming that the transistors are arranged one-dimensionally is defined as a first layout area. A third layout area for calculating, and based on the first layout area and a second layout area which is a sum of areas of the respective transistors calculated in the first and second steps. A circuit characteristic evaluation method for estimating a layout area of an integrated circuit. 16. The circuit characteristic evaluation method according to claim 11, wherein the circuit characteristic evaluation step includes a delay estimation step of estimating a delay of the integrated circuit as an evaluation index of the characteristic, and the delay estimation step includes: A first step of calculating a capacity of the diffusion area estimated not to involve the diffusion sharing in the diffusion sharing estimation step; and a capacity of the diffusion area estimated to involve the diffusion sharing in the diffusion sharing estimation step. And calculating a delay of the integrated circuit using the capacitance of the diffusion region calculated in the first and second steps. Circuit characteristics evaluation method. 17. The circuit characteristic evaluation method according to claim 11, wherein the circuit characteristic evaluation step includes a power consumption estimation step of estimating power consumption of the integrated circuit as an evaluation index of the characteristic. A first step of calculating a capacity of the diffusion area estimated not to involve the diffusion sharing in the diffusion sharing estimation step; and a capacity of the diffusion area estimated to be accompanied by the diffusion sharing in the diffusion sharing estimation step. And a second step of calculating in anticipation of a reduction in the area of the diffusion region due to the above. The power consumption of the integrated circuit is obtained by using the capacitance of the diffusion region calculated in the first and second steps. A circuit characteristic evaluation method, characterized in that: 18. A transistor size determining method for determining the size of each transistor when designing a layout of an integrated circuit to be designed, wherein a given transistor is provided based on circuit data indicating a configuration of the integrated circuit. A diffusion sharing estimation step of estimating a location where diffusion sharing is performed in the layout of the integrated circuit when a size candidate is used; technology data representing information relating to the circuit data and the semiconductor manufacturing process; and the diffusion sharing estimation step. A circuit property evaluation step of estimating and evaluating the characteristics of the integrated circuit when the given transistor size candidate is used, based on the estimated information on the diffusion sharing location, An evaluation step is performed for a plurality of types of transistor size candidates to evaluate the circuit characteristics. A transistor size determination method, wherein one transistor size is determined based on an estimated evaluation result in a process. 19. The transistor size determination method according to claim 18, wherein the diffusion sharing estimation step and the circuit characteristic evaluation step are repeatedly performed such that a predetermined evaluation index becomes an optimum value while changing the setting of the transistor size candidate. Wherein the setting of the candidate transistor size is changed with a predetermined change width, and the change width is variable in accordance with a change in the predetermined evaluation index.