JP3144484B2 - Flash memory and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a flash-type nonvolatile semiconductor memory device, that is, a flash memory, and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIGS. 15 (plan view) and 16 (A in FIG. 15)
FIGS. 17A and 17B (cross-sectional views taken along the line BB 'in FIG. 15) show the structure of a conventional flash memory. In this structure, a buried diffusion layer 123 (123) formed of an impurity diffusion layer in the lateral direction of FIG.
d, 123s) are provided in common for a plurality of memory cells, and are used as bit lines and source lines. On the channel region sandwiched between the buried diffusion layer 123d (drain region) and the buried diffusion layer 123s (source region), the floating gate 115
And a control gate 116 used as a word line in a stripe shape covering the source-side channel region and the floating gate 115 is provided in the vertical direction in FIG. 15 (plan view). I have.

Data is written by injecting hot electrons into the floating gate, and data is erased by extracting electrons from the floating gate to the erase gate 117 by FN tunnel current. The erase gate 117 is provided in a stripe shape in the same direction as the control gate 116 in the vertical direction of FIG. 15, and one erase gate is adjacent to two adjacent gates as shown in FIG. It is provided in common for one floating gate.

FIG. 1 shows a method of manufacturing this flash memory.
5 will be described with reference to FIGS.

First, an impurity such as arsenic is implanted using a silicon substrate as the semiconductor substrate 111 and an appropriate mask having an opening at a position where the buried diffusion layer 123 shown in FIG. 123 are formed (not shown in FIG. 18).

Next, as shown in FIG. 18A, a silicon oxide film is deposited on this surface and then patterned,
The element isolation film 114 is formed in a stripe shape in a plan view. Further, the surface of the semiconductor substrate which is not covered with the element isolation film 114 is oxidized to form a gate insulating film 118.

Next, as shown in FIG. 18B, a polysilicon film 124 for a floating gate is deposited. Although not shown in the cross-sectional view of FIG. The polysilicon film 124 is patterned. Floating gate-control gate insulating film 125 (FG-CG insulating film 125)
To form

Next, as shown in FIG. 18C, after a control gate polysilicon film 126 is deposited, the control gate-erase gate insulating film 12 is formed on the surface thereof.
A silicon oxide film is formed as 7 (CG-EG insulating film).

Next, as shown in FIG. 19D, using a pattern of a photoresist 128, a control gate-erasing gate insulating film 127 and a control gate polysilicon film 126 are formed in a vertical stripe of FIG. Then, the control gate 116 is formed.

Next, as shown in FIG. 19E, after removing the photoresist 128, a silicon oxide film is formed on the entire surface, and subsequently, a sidewall insulating film 129 is formed by etching back.

Next, using the stripe-shaped control gate 116 provided with the stripe-shaped control gate-erase gate insulating film 127 and the side wall insulating film 129 as a mask, the floating gate polysilicon film 124 is formed.
And the floating gate-control gate insulating film 125 is patterned to form the floating gate 11.
5 is made island-shaped. Further, the floating gate-erase gate insulating film 130 (FG-EG insulating film 13) is formed on the exposed surface of the floating gate 115 by thermal oxidation.
0) is formed to complete the structure up to FIG.

Next, as shown in FIG. 2G, after an erase gate polysilicon film 131 is deposited, a photoresist 132 is used to erase the polysilicon film 131.
Is patterned as shown in FIG.
5, erase gate 1 in the form of a vertical stripe
17 is formed.

Thereafter, as shown in FIG. 21 (i), an interlayer insulating film 133 is formed, and necessary contacts and the like are formed to complete a flash memory.

In recent years, as the memory capacity has increased, the area occupied by one memory cell has been gradually reduced, and the width between the control gates and the distance between the control gates have also been reduced. Then Figure 20
The groove between the control gates denoted by reference numeral 140 in (f) is a groove having a small width and a large aspect ratio. In a typical structure of a current flash memory, for example, the height of the element isolation film 114 is 0.3 μm, and the thickness of the floating gate polysilicon film 124 stacked on the element isolation film in FIG. The thickness of the control gate polysilicon film is 0.15 μm,
The thickness of the inter-EG insulating film is 0.25 μm. In addition, the width and the interval of the control gate are both set to 0.1 in a typical structure.
The thickness is about 36 μm to 0.4 μm, and the thickness of the sidewall insulating film is 0.1 μm to 0.12 μm. Therefore, the groove 140
Has a depth of about 0.6 μm and a width of 0.15 μm to 0.2
It becomes about μm.

If the groove between the control gates has such a high aspect ratio, the polysilicon film 131 for the erase gate is etched in a stripe shape in the steps from FIG. 20 (g) to FIG. 21 (h) in the manufacturing process. And erase gate 11
When separating 7 is formed, it is difficult to completely remove the polysilicon from the groove 140, and the polysilicon may remain. However, if polysilicon remains in the trench, adjacent floating gates are capacitively coupled through a thin insulating film, and when an erase signal is input, they are electrically coupled to the floating gate that does not erase. As a result, there was a problem that the reliability of data was lost.

Also, it is necessary to form a circuit such as a sense amplifier for measuring a current around the memory cell, and it is required to form these peripheral circuits in as few steps as possible. At the same time as depositing and patterning polysilicon for use, a gate of a transistor of a peripheral circuit is formed. However, groove 1
When the aspect ratio of 40 becomes large, the etching amount of the polysilicon in the groove becomes extremely large as compared with the etching amount of the portion deposited on the flat portion. In some cases, the underlying oxide film acting as an etching stopper is etched by etching, and erodes up to the source / drain regions and may not function as a transistor.

Such a problem becomes more prominent when the integration is further advanced and the aspect ratio is further increased.

[0018]

SUMMARY OF THE INVENTION The present invention has been made in view of such conventional problems, and a flash memory having high data reliability even in the case of miniaturization and high integration has been developed. The purpose is to provide.

Another object of the present invention is to provide a method for manufacturing such a highly reliable flash memory with high productivity.

[0020]

SUMMARY OF THE INVENTION The present invention provides a buried diffusion layer which is a source / drain region provided on a surface of a semiconductor substrate, a stripe-shaped inter-element separation film for partitioning the surface of the semiconductor substrate, and the element separation film. A channel region provided in a region defined by the above, an island-like floating gate covering at least a part of the channel region, and a stripe-like shape in the same direction as the inter-element isolation film above the floating gate via an insulating film. And an erase gate provided in a stripe shape in the same direction as the inter-element isolation film via the floating gate and the control gate and an insulating film, and erasing data from the floating gate. In a flash memory performed by electron extraction to an erase gate, the stripe Control gate, the distance X
1 and a distance X2 (where X1> X2), and the erase gate is provided so as to fill a gap corresponding to the wider distance X1. Regarding memory.

According to the present invention, there is further provided a buried diffusion layer which is a source / drain region provided on a surface of a semiconductor substrate;
A channel region provided in a region partitioned by the element isolation film, an island-shaped floating gate covering at least a part of the channel region, and an insulating film above the floating gate and the inter-element isolation film interposed therebetween. A control gate provided in a stripe pattern in a direction, and an erase gate provided in a stripe pattern in the same direction as the inter-element separation film via the floating gate and the control gate and an insulating film. In a method for manufacturing a flash memory performed by extracting electrons from a floating gate to the erase gate,
Forming the control gates in the form of stripes alternately spaced from each other by a distance X1 and a distance X2 (where X1>X2); and forming the control gates on a side separated by a distance X1 from an adjacent control gate. Forming a sidewall insulating film on the side wall of the control gate and filling a gap between the control gates separated by a distance X2 with the same material as that of the sidewall insulating film.

[0022]

1 (plan view) and FIG. 2 (A in FIG. 1).
The present invention will be described with reference to an example of a flash memory of the present invention using 1-A1 'cross-sectional view and FIG.

As shown in FIG. 1, a buried diffusion layer 14 (14s, 14d) is provided on a semiconductor substrate 1 in a stripe shape in a horizontal direction in the plan view of FIG. . This impurity diffusion layer is used as a bit line and a source line. When attention is paid to the central floating gate 12a in FIG. 3, the drain represented by 14d becomes a drain, and the drain represented by 14s is used. It becomes a source and is used as a source line (ground line). This structure has one structure for the source region and the drain region.
It is called a contactless array configuration because contacts are not taken one-to-one, and among them, a bit line is used as both a source and a drain, so it is called a virtual ground array configuration.

In FIG. 3, when the left floating gate 12b is selected, the buried diffusion layer 14s indicated by 14s in FIG. 3 becomes a drain and is used as a bit line. At this time, an impurity diffusion layer (not shown) existing on the left side of the floating gate 12b on the left side in the figure serves as a source and has a ground potential. At the same time, the floating gate 12a is in a non-selected state, and the buried diffusion layer 14d is also at the ground potential.

On the drain side of the channel region between the buried diffusion layers 14s and 14d, an island-shaped floating gate 12 is provided via a gate insulating film 3.
As shown in FIG.
A control gate 11 having a stripe shape in the vertical direction is provided. In this example, the control gate has a split gate type in which the channel region that is not covered by the floating gate is covered via an insulating film, and the channel region can be controlled by the control gate.

In the present invention, the control gate is
The intervals between the adjacent control gates are alternately different, the distance X1 is set between the control gates 11a and 11b in FIG. 1, the distance X2 is set between 11b and 11c, and the distance X1 is set as 11c and 11d. Has been repeated.

As shown in FIGS. 1 and 2, an erase gate 13 is provided between a wide portion (X1) between the control gates, and an insulating film 21 (hereinafter referred to as a control gate) is provided between a narrow portion (X2). An inter-layer insulating film (inter-CG insulating film)) is formed. The distance X2 is a distance enough to be filled with the insulating material when depositing the insulating material for forming the sidewall insulating film 9, and is usually 0.2 μm or less, preferably 0.15 to 0.18 μm.

That is, in the manufacturing method of the present invention, the inter-CG insulating film 21 is preferably formed of the same material as the side wall insulating film 9 simultaneously with the formation of the side wall insulating film. According to such a manufacturing method, the trench between the narrower control gates (interval X2) is already filled with the insulating film at the time of depositing the polysilicon for the erase gate. Silicon can be prevented from entering and a highly reliable flash memory can be formed.

It should be noted that the distance X1 is such that the gap between the sidewall insulating films is not buried when the sidewall insulating film is formed as in the prior art and an erase gate can be formed, and is usually set to about 0.4 to 0.5 μm. .

One stripe-shaped erase gate 13 is provided commonly to two columns of floating gates in the vertical direction (as viewed in FIG. 1) adjacent to each other, and one floating gate has one erase gate. 13 correspond. That is, every other erase gate is provided between the rows of the floating gates when viewed in a plan view.

Note that the present invention is not limited to such a configuration, and a non-split gate type non-split gate type may be used as long as the channel width is determined by the distance between the element isolation films. Alternatively, the present invention can be applied to a non-contactless array.

Next, a typical example of the manufacturing method of the present invention will be described in detail with reference to the drawings. [Embodiment 1] First, using a p-type silicon substrate as the semiconductor substrate 1 and using a mask having an opening in the lateral direction in FIG. 1 (plan view), arsenic is applied to the surface of the semiconductor substrate, for example, acceleration energy is 40 keV. , Dose 4 × 10 ¹⁵ c
ions are implanted under the condition of m ⁻² , for example, 950 in a nitrogen atmosphere.
Anneal at 20 ° C. for 20 minutes to form the buried diffusion layer 14.

Next, as shown in FIG.
A device isolation film 2 having a thickness of 00 nm is formed in a stripe shape in the vertical direction in FIG. 1 (plan view) to separate device regions, and a gate insulating film 3 is formed on the surface.

As shown in FIG. 5B, the polysilicon film 4 for the floating gate is formed to a thickness of about 5 by the CVD method.
After being formed to a thickness of 00 nm, it is patterned into a rectangular shape over two memory cells in the horizontal direction using a mask 20 for a floating gate as shown in FIG. Thereafter, an HTO as an insulating film between the floating gate and the control gate (hereinafter, also referred to as an FG-CG insulating film) 5 is formed.
(High Temperature CVD Oxi
3 by a high temperature CVD) method or thermal oxidation.
A silicon oxide film of about 0 nm is formed.

At this time, the width of the gap 22 between the floating gates is, for example, about 0.2 μm.
In order to fill 2 with a buried insulating film, a silicon oxide film is deposited to a thickness of about 0.5 μm and then etched back.

Further, as shown in FIG. 5C, a polysilicon film 6 for a control gate is
A silicon oxide film having a thickness of 250 nm is formed as a control gate-erasing gate insulating film (hereinafter also referred to as a CG-EG insulating film) 7 on the surface by a CVD method.

Next, as shown in FIG. 6D, using the photoresist 8 as a mask, the CG-EG insulating film 7 and the polysilicon film 6 are etched to form the control gate 11.
Is separated. At this time, as the opening width of the photoresist,
The width is set to be a narrow width X2 above the buried insulating film 23 and to be a wide width X1 above a portion where the floating gate polysilicon is etched in a later step. Specifically, for example, X2 is 0.2 μm and X1 is about 0.4 μm.

Thereafter, after a silicon oxide film is formed on the entire surface by the CVD method, the silicon oxide film is etched back to form the side wall insulating film 9 on the side wall of the control gate as shown in FIG. Form. In this manufacturing method, X2 may be set to such a width that the inter-CG insulating film 21 is formed simultaneously with the formation of the sidewall insulating film.

Next, as shown in FIG. 7F, etching is performed by using the side wall insulating film 9 as a mask until the element isolation film 2 appears, separating the polysilicon film 4 and turning the floating gate 12 into an island shape. Separately form.

Subsequently, the side wall insulating film 9 is receded by about 40 to 100 ° by wet etching or the like to expose an edge of a corner where electrons are extracted from the floating gate 12 at the time of an erasing operation. Subsequently, the surface of the floating gate 12 is formed by, for example, the HTO method.
Using a mixed gas of SiH ₄ and O _2, a silicon oxide film is formed as a floating gate-erase gate insulating film (also referred to as an FG-EG insulating film) 10 to a thickness of about 20 nm.

Next, as shown in FIG. 7G, after a polysilicon film 15 for an erase gate is formed on the entire surface, a photoresist 16 having a stripe shape in the vertical direction of FIG. Formed on the surface, the polysilicon film 15 is separated by etching to form the erase gate 13 as shown in FIG.

Next, as shown in FIG. 8I, an interlayer insulating film 17 is formed, and necessary contacts and the like are formed to complete a flash memory.

[Embodiment 2] As in Embodiment 1, first, a p-type silicon substrate is used as the semiconductor substrate 1 and FIG.
Using a mask having an opening in the horizontal direction (plan view), arsenic is ion-implanted into the surface of the semiconductor substrate, for example, under the conditions of an acceleration energy of 40 keV and a dose of 4 × 10 ¹⁵ cm ⁻² , for example, in a nitrogen atmosphere. Anneal at 950 ° C. for 20 minutes to form the buried diffusion layer 14.

Next, as shown in FIG.
A device isolation film 2 having a thickness of 00 nm is formed in a stripe shape in the vertical direction in FIG. 1 (plan view) to separate device regions, and a gate insulating film 3 is formed on the surface.

As shown in FIG. 9B, the polysilicon film 4 for the floating gate is formed to a thickness of about 5 by the CVD method.
After being formed to a thickness of 00 nm, it does not appear in the cross-sectional view of FIG.
The polysilicon film 4 is patterned so as to have a stripe shape in the horizontal direction in FIG. 1, and a floating gate-control gate insulating film (FG-CG) is further formed on the surface thereof.
HTO (High Temper)
(attitude CVD Oxidation; high temperature CVD)
A silicon oxide film of about 30 nm is formed by a method or thermal oxidation.

Further, as shown in FIG. 9C, a polysilicon film 6 for a control gate is
0 nm, and a control gate-erase gate insulating film (CG-EG insulating film) 7
A silicon oxide film is formed to a thickness of 250 nm by a VD method. On top of this, a photoresist 30 is formed in the form of a stripe in the vertical direction in FIG. 1 so that its opening is located directly above the element isolation film 2. Photoresist 3 at this time
The opening width X1 of 0 is, for example, 0.4 μm.

As shown in FIG. 10D, using this as a mask, the CG-EG insulating film 7 is etched to remove the photoresist 30, and then the exposed surface of the polysilicon film 6 is etched by thermal oxidation. An oxide film is formed as the stopper film 31.

As shown in FIG. 10E, a silicon nitride film is deposited on the surface and then etched back to form a sidewall film 32 on the sidewall of the CG-EG insulating film. Here, the opening width X2 after the attachment of the sidewall film 32 is, for example, 0.2 μm.

Then, as shown in FIG. 11F, a photoresist 34 is formed to cover every other gap 33 between the patterned CG-EG insulating films 7.

Using the photoresist 34 as a mask, a side wall film (32 in FIG.
When a) is removed by etching, the width of the gap 33a of the CG-EG insulating film becomes X1 again. Thus, the side wall film 32
Is required to be formed of a material different from that of the CG-EG insulating film so that only the side wall film can be removed under predetermined etching conditions. Further, the etching stopper film needs to be a material capable of protecting the control gate material thereunder under the condition of removing the side wall film.

In this state, the gap shown in FIG.
As shown in (g), the control gate polysilicon film 6 is etched until it reaches the FG-CG insulating film.

Next, as shown in FIG. 12 (h), a photoresist 35 covering the opening 33a is formed, and the side wall film 32 is used as a mask to form a photoresist 35 having a width of X2.
As shown in FIG. 6, the control gate polysilicon film 6, the FG-CG insulating film 5,
The polysilicon film 4 for the floating gate is sequentially etched. In the steps so far, a plurality of control gates alternately separated from each other by the gap of the distance X1 and the distance X2 are formed.

After removing the photoresist, a silicon oxide film is formed on the entire surface by CVD, and then etched back to form a side wall insulating film 9 on the side wall of the control gate as shown in FIG. , An inter-CG insulating film 21 is formed. Also in this manufacturing method, X2 may be set to such a width that the inter-CG insulating film 21 is formed simultaneously with the formation of the sidewall insulating film.

Next, as shown in FIG. 13 (k), etching is performed using the side wall insulating film 9 as a mask until the device isolation film 2 appears, separating the polysilicon film 4 to form the floating gate 12 into an island shape. Separately form.

Subsequently, the side wall insulating film 9 is receded by about 40 to 100 ° by wet etching or the like to expose an edge of a corner where electrons are extracted from the floating gate 12 at the time of an erasing operation. Subsequently, the surface of the floating gate 12 is formed by, for example, the HTO method.
Using a mixed gas of SiH ₄ and O _2, a silicon oxide film is formed as a floating gate-erase gate insulating film (also referred to as an FG-EG insulating film) 10 to a thickness of about 20 nm.

Next, the polysilicon film 15 for the erase gate is used.
Is formed on the entire surface, a photoresist 16 having a stripe shape in the vertical direction in FIG. 1 is formed on the surface of the polysilicon film 15, and the polysilicon film 15 is separated by etching, as shown in FIG. An erase gate 13 is formed.

Next, as shown in FIG. 14 (m), an interlayer insulating film 17 is formed and necessary contacts are formed to complete a flash memory.

In the manufacturing method described with reference to Embodiments 1 and 2, the control gate gap where no erase gate is formed is filled before the polysilicon for erase gate formation is deposited. Unrequired polysilicon does not remain in the groove, and a highly reliable flash memory can be formed. Further, the etching amount necessary for patterning the erase gate is only required to be the polysilicon thickness deposited on the CG-EG insulating film, which is the same as the polysilicon thickness deposited on the peripheral circuit portion.
Peripheral circuits can also be manufactured with high productivity.

[0059]

According to the present invention, it is possible to provide a flash memory having high data reliability even in the case of miniaturization and high integration.

Further, according to the present invention, it is possible to provide a method of manufacturing such a highly reliable flash memory with high productivity.

[Brief description of the drawings]

FIG. 1 is a plan view showing one example of a structure of a flash memory of the present invention.

FIG. 2 is a diagram showing a cross section taken along line A1-A1 'of FIG.

FIG. 3 is a view showing a B-B ′ section of FIG. 1;

FIG. 4 is a view showing a mask pattern of a floating gate used in an example of a method for manufacturing a flash memory according to the present invention.

FIG. 5 is a diagram showing a method for manufacturing the flash memory of the present invention shown in the first embodiment.

FIG. 6 is a view illustrating a method of manufacturing the flash memory, following FIG. 5;

FIG. 7 is a view illustrating a method of manufacturing the flash memory, following FIG. 6;

FIG. 8 is a view illustrating a method of manufacturing the flash memory following FIG. 7;

FIG. 9 is a diagram illustrating a method for manufacturing the flash memory of the present invention described in the second embodiment.

FIG. 10 is a view illustrating a method of manufacturing the flash memory following FIG. 9;

FIG. 11 is a view illustrating a method of manufacturing the flash memory, following FIG. 10;

FIG. 12 is a view illustrating a method of manufacturing the flash memory following FIG. 11;

FIG. 13 is a view illustrating a method of manufacturing the flash memory, following FIG. 12;

FIG. 14 is a view illustrating a method of manufacturing the flash memory, following FIG. 13;

FIG. 15 is a plan view showing an example of the structure of a conventional flash memory.

FIG. 16 is a view showing a cross section taken along line A-A ′ of FIG. 15;

17 is a diagram showing a cross section taken along line B-B 'of FIG.

FIG. 18 is a view showing one example of a conventional flash memory manufacturing method.

FIG. 19 is a diagram illustrating an example of a conventional method of manufacturing a flash memory, following FIG. 18;

FIG. 20 is a diagram illustrating an example of a conventional flash memory manufacturing method, following FIG. 19;

FIG. 21 is a view showing one example of a conventional flash memory manufacturing method, following FIG. 20;

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 element isolation film 3 gate insulating film 4 polysilicon film for floating gate 5 floating gate-control gate insulating film (FG-CG insulating film) 6 polysilicon film for control gate 7 control gate-erasing Gate insulating film (CG-
8 Photoresist 9 Side wall insulating film 10 Floating gate-erasing gate insulating film (F
(G-EG insulating film) 11 control gate 12, 12a, 12b floating gate 13 erase gate 14, 14s, 14d buried diffusion layer 15 polysilicon film for erase gate 16 photoresist 17 interlayer insulating film 20 mask for floating gate 21 Control gate insulating film (CG insulating film) 22 Gap between floating gates 23 Buried insulating film 30 Photoresist 31 Etching stopper film 32 Side wall film 33, 33a, 33b Gap 34 Photoresist 35 Photoresist

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2000-174144 (JP, A) JP-A-2000-100976 (JP, A) JP-A-11-354759 (JP, A) JP-A-11-204663 ( JP, A) JP-A-11-195770 (JP, A) JP-A-10-107230 (JP, A) JP-A-8-167706 (JP, A) JP-A-8-241932 (JP, A) JP Hei 8-51164 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (6)

(57) [Claims] 1. A buried diffusion layer which is a source / drain region provided on a surface of a semiconductor substrate, a stripe-shaped inter-element separation film for partitioning the surface of the semiconductor substrate, and a region provided by the element separation film. A channel region, an island-shaped floating gate covering at least a part of the channel region, and a control gate provided in a stripe shape in the same direction as the inter-element isolation film via an insulating film above the floating gate; An erase gate is provided in the form of a stripe in the same direction as the inter-element isolation film via the floating gate and the control gate and an insulating film, and data is erased by extracting electrons from the floating gate to the erase gate. In such a flash memory, the stripe-shaped control gate is The erase gates are alternately separated from each other by a distance X1 and a distance X2 (where X1> X2), and the erase gate is provided to fill a gap corresponding to the wider distance X1. Flash memory. 2. The flash memory according to claim 1, wherein a gap between the control gates corresponding to the distance X2 is filled with the same material as a sidewall insulating film provided on a sidewall of the control gate. . 3. The flash memory according to claim 1, wherein the distance X2 is a distance filled with a material of the side wall insulating film when forming a side wall insulating film provided on a side wall of the control gate. 4. A buried diffusion layer which is a source / drain region provided on the surface of the semiconductor substrate, a stripe-shaped inter-element separation film for partitioning the surface of the semiconductor substrate, and a region provided by the element separation film. A channel region, an island-shaped floating gate covering at least a part of the channel region, and a control gate provided in a stripe shape in the same direction as the inter-element isolation film via an insulating film above the floating gate; An erase gate is provided in the form of a stripe in the same direction as the inter-element isolation film via the floating gate and the control gate and an insulating film, and data is erased by extracting electrons from the floating gate to the erase gate. The method of manufacturing a flash memory according to Forming stripes alternately spaced from each other by X1 and a distance X2 (where X1> X2), and sidewall insulation on the side of the control gate that is separated by a distance X1 from the adjacent control gate Simultaneously forming a film and filling a gap between the control gates separated by a distance X2 with the same material as the material of the sidewall insulating film. 5. A polysilicon film for a floating gate is formed on a semiconductor substrate on which a stripe-shaped inter-element isolation film and a gate insulating film are formed by two memory cells adjacent to each other in a direction orthogonal to the inter-element isolation film. Forming a floating gate-control gate insulating film on the surface of the floating gate polysilicon film; and filling a gap between the floating gates above the element isolation film. A step of forming a polysilicon film for a control gate on the surface and a step of forming an insulating film between the control gate and the erase gate on the surface, and a step of forming a polysilicon film for the control gate and the erase gate on the surface. A width X2 above the buried insulating film and a floating gate policy in a later step. Forming a photoresist having an opening having a width of X1 (where X1> X2) above a portion where a capacitor is to be etched; and using the photoresist as a mask, the control gate-erasing gate insulating film and the control. Etching the gate polysilicon film to separate the control gates; forming a sidewall insulating film on the side of the control gate on the side where the adjacent control gates are separated by a wide width X1; Filling the gap separated by X2 with the same material as that of the sidewall insulating film; and etching the floating gate-control gate insulating film and the polysilicon film for the floating gate from the opening interposed between the sidewall insulating films. Exposing the device isolation film, and Forming a floating gate in an island shape; forming a floating gate-erase gate insulating film on the exposed surface of the floating gate; and forming an erase gate Forming an erase gate by depositing a polysilicon film and then patterning the polysilicon film to form an erase gate. 6. A floating gate polysilicon film is patterned on a semiconductor substrate on which a stripe-shaped inter-element separation film and a gate insulating film are formed in a stripe shape in a direction orthogonal to the inter-element separation film. Forming a floating gate-control gate insulating film on the surface of the floating gate polysilicon film, forming a control gate polysilicon film on the surface, and further forming a control gate-erasing film on the surface. Forming an inter-gate insulating film; forming a photoresist having an opening having a width of X1 on the surface of the control gate-erasing gate insulating film; Etching the inter-erasing gate insulating film,
Patterning into a stripe shape separated by a distance X1 from each other, and after the etching step, etching the surface of the control gate polysilicon film exposed from the gap from which the control gate-erase gate insulating film has been removed. Forming a stopper film; forming a sidewall film on the sidewall of the stripe-shaped insulating film between the control gate and the erasing gate using a material different from the material of the insulating film between the control gate and the erasing gate; , X1> X2), a step of forming a photoresist that covers every other stripe of the insulating film between the control gate and the erase gate, and a step of not covering the gap with the photoresist. Before providing on the side wall of the insulating film between the control gate and the erase gate The side wall film is removed, and the gap width between the control gate and the erase gate insulating film is defined as X1, and the control gate polysilicon film is transferred from the gap having the width X1 to the floating gate-control gate insulating film. Etching, removing the resist used in the etching step, covering the gap of the width X1 with a different photoresist, and removing the control gate from the gap of the width X2 until reaching the device isolation film. Sequentially etching the polysilicon film, the floating gate-control gate insulating film and the floating gate polysilicon film, and after removing the resist used in the etching process,
At the same time as forming a sidewall insulating film on the side wall of the control gate which is separated from the adjacent control gate by a wide width X1, a gap between the control gates separated by a distance X1 is made of the same material as the material of the sidewall insulating film. Burying, etching the floating gate-control gate insulating film and the floating gate polysilicon film from the opening interposed between the sidewall insulating films, exposing the element isolation film, and forming the floating gate in an island shape. Forming an insulating film between the floating gate and the erase gate on the exposed surface of the floating gate; and depositing a polysilicon film for the erase gate in the opening interposed between the sidewall insulating films. Patterning to form an erase gate. Manufacturing method.