JP3143267B2 - Rotation detection pulse input control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a rotation detection pulse input control circuit suitable for use in a speedometer of a bicycle or the like.

[0002]

2. Description of the Related Art In recent years, diversification of bicycles has progressed, and competition bicycles running on off-roads, on-roads and the like have become popular in the market. Along with this, demand for speedometers that display the running speed of bicycles is growing in the accessory market. Many of recent speedometers use a battery, and the speed is displayed on a liquid crystal panel, a fluorescent panel, or the like based on rotation information of wheels. The wheel rotation information can be generated by fixing the magnet (2) to the wheel (1) and fixing the reed switch (4) to the frame (3) as shown in FIG. Specifically, when the magnet (2) and the reed switch (4) face each other while the wheel (1) is rotating, the reed switch (4) is turned on only for a time period facing the magnet (2). A pulse signal indicating that the wheel (1) is rotating at a certain speed is output to a signal processing circuit (not shown) by closing under the influence of the magnetic field. As shown in FIG. 6, this pulse signal has a pulse width and a cycle that change according to the rotation speed of the wheel (1). Specifically, when the wheel (1) is rotating at a low speed, the time for the magnet (2) and the reed switch (4) to face each other and the time until the wheel (1) faces again are long, so that the pulse width W1 and the period T1 Is naturally longer. On the other hand, when the wheel (1) is rotating at a high speed, the time for the magnet (2) and the reed switch (4) to face each other and the time until the wheel (1) again faces are shortened, so that the pulse width W2 (<W1) and the cycle T2 (<T
1) naturally becomes shorter.

[0003] The signal processing circuit has a wheel circumference (cm).
And information indicating the period (msec) of the pulse signal, and calculates the speed per hour (km / h). More specifically, the signal processing circuit can be realized by a microcomputer, and calculates an hourly speed by performing an arithmetic process of Equation 1 described later on binary data indicating the circumference of the wheel and the cycle of the pulse signal. Here, the dimensions of cm / msec and km / h have the relationship shown in Expression 1.

[0004]

(Equation 1)

[0005] For example, in the case of a bicycle having a wheel diameter of 27 inches, when the circumference of the wheel is 215.5 cm and the cycle T and the speed per hour V are obtained by using Equation 1, as shown in FIG. Becomes Here, as is clear from the transition of the hourly speed V, the resolution of the period T is set to 1 msec in order to absorb the error of the hourly speed V more. By the way, 1km / h
When trying to display the nearby hourly speed V, 8000 msec
The nearby period T must be measured, and the number of bits of the counter for counting the period T, the capacity of the memory for sequentially storing the count value of the counter, and the burden on the software for controlling the counter and the memory may be increased. There is. Therefore, conventionally, the maximum count value of the counter is limited (for example, 2
000 msec), the hourly speed display was forcibly set to 0 km / h when the counter counted the maximum count value.
As a result, the number of bits of the counter and the capacity of the memory are reduced, and the load on the software is reduced.

[0006]

However, when the wheel is rotating at a very low speed and a plurality of pulse signals whose cycle exceeds the maximum count value of the counter are generated, the microcomputer takes in these pulse signals. I will. That is, the microcomputer repeats the operation of measuring the period T every time a pulse signal is taken in.
km / h is displayed. Therefore, even when the period T of the pulse signal is in a range exceeding the maximum count value of the counter, there is a problem that the software of the microcomputer continues to operate and the power consumption increases.

It is an object of the present invention to provide a rotation detection pulse input control circuit that can reduce the power consumption of a speedometer.

[0008]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and the feature of the present invention is to detect the rotation of a wheel and to determine a period according to the rotation speed of the wheel. Pulse generation means for generating different rotation detection pulses, calculation means for calculating the rotation speed of the wheel based on the size of the wheel and the cycle of the rotation detection pulse, and between the pulse generation means and the calculation means A gate means interposed between the first and second sensors to pass or cut off the rotation detection pulse; a counter means reset by the rotation detection pulse to count a clock of a predetermined frequency; and a period of the rotation detection pulse by monitoring a count value of the counter means. A time-over detecting means for detecting that the period of the rotation detection pulse is longer than a predetermined period; Pulse cycle detecting means for detecting that the counter means is reset according to the detection output of the time-over detecting means, and the gate means is closed, and the gate means is opened according to the detection output of the pulse cycle detecting means. Wherein the rotation detection pulse is not applied to the arithmetic means when the period of the rotation detection pulse is in a range equal to or longer than a predetermined period.

[0009]

According to the present invention, when the period of the rotation detection pulse is within a predetermined period or more, the gate means interposed between the pulse generation means and the calculation means is closed, and the rotation detection pulse is applied to the calculation means. I try not to let it. by this,
The operation of the calculation means can be stopped, and the power consumption can be reduced.

[0010]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a diagram showing a rotation detection pulse input control circuit according to the present invention. In FIG. 1, the dot-dashed line (5) is a pulse generating means. Inside the pulse generating means (5), (6) and (7) form N which forms an RS flip-flop.
An OR gate, to one input terminal of the NOR gate (6), a pulse signal shown in FIG. 6 whose pulse width and period change according to the rotation speed of the wheel is applied. (8) is an inverter for inverting the output of the NOR gate (6). (9) is a D flip-flop. The output of the inverter (8) is applied to the D terminal, the inversion of the clock CK is applied to the C terminal, and the inverter (8) is applied to the falling edge of the clock CK from the Q terminal. To generate an output that changes in accordance with the output level of. The output of the D flip-flop (9) is fed back to one input terminal of the NOR gate (7). (10) is a latch circuit, the output of the Q terminal of the D flip-flop (9) is applied to the L terminal,
A clock CK is applied to the C terminal, and an inverted output that changes according to the output level of the D flip-flop (9) is generated from the * Q terminal every time the clock CK rises. Reference numeral (11) denotes an AND gate for calculating the logical product of the Q terminal output of the D flip-flop (9) and the * Q terminal output of the latch circuit (10). That is, as shown in FIG. 2, the pulse generation means (5) changes the pulse width and the cycle in accordance with the rotation state of the wheel from the pulse signal a, and changes the pulse width to a half cycle of the clock CK in synchronization with the clock CK. A fixed rotation detection pulse e is generated. In other words, the pulse generating means (5) generates the rotation detection pulse e corresponding to the pulse signal a so that the arithmetic circuit described later can perform appropriate arithmetic processing.

Reference numeral (12) denotes an OR gate, which derives a rotation detection pulse e to a reset terminal of a counter described later. (13) is a 12-bit counter, which is reset at the rising edge of the rotation detection pulse e and has a clock CK.
Is counted to measure the period of the rotation detection pulse e. Here, the frequency of the clock CK is appropriately selected, and the cycle of the rotation detection pulse e is set to a predetermined cycle (for example, 200
(0 msec), any three bits Q9 to Q11 of the counter (13) are set to "1".

Reference numeral (14) denotes an AND gate (time-over detection means) for calculating a logical product of Q9 to Q11 of the counter (13). That is, the AND gate (1
4) outputs “1” when the cycle of the rotation detection pulse e reaches a predetermined cycle. The dashed line (15) is control means. In the control means (15), (16) (1
7) is a NOR gate forming an RS flip-flop, and one input terminal of the NOR gate (16) is connected to AN
The output of the D gate (14) is applied. That is, when the cycle of the rotation detection pulse e reaches a predetermined cycle, the RS flip-flops (16) and (17) are set by receiving the "1" output of the AND gate (14), and the counter (13) is set to N
It is reset upon receiving the "1" output of the OR gate (17). Similarly, (18) and (19) are NOR gates forming an RS flip-flop, and the NOR gate (18)
The set output of the preceding NOR gate (17) is applied to one of the input terminals. (20) is an inverter,
This is to invert the output of the NOR gate (18).
(21) is a latch circuit, the output of the inverter (20) is applied to the L terminal, the clock CK is applied to the C terminal, and the output level of the inverter (20) from the * Q terminal every time the clock CK rises. To generate an output that changes in accordance with (22) is an OR gate, and RS
The output of the NOR gate (18) forming the flip-flop or the output of the * Q terminal of the latch circuit (21) is passed. That is, as shown in FIG. 3, when the cycle of the rotation detection pulse e reaches a predetermined cycle at the time t0, the output of the OR gate (22) is "at a time t1 delayed from the time t0 by a half cycle of the clock CK". 0 ".

Reference numeral (23) denotes an AND gate (gate means) for opening and closing the gate according to the output level of the OR gate (22). That is, an AND gate (23)
Outputs a rotation detection pulse e when the output of the OR gate (22) is "1", and outputs "0" when the output of the OR gate (22) is "0".
In this case, the output of the rotation detection pulse e is prohibited.
Numeral (24) is an arithmetic circuit which measures the period of the rotation detection pulse e output from the AND gate (23), determines the hourly speed using the relation of the equation (1), and displays it on a liquid crystal panel, a fluorescent panel or the like. Is subjected to signal processing. That is, when the cycle of the rotation detection pulse e reaches a predetermined cycle, the arithmetic circuit (24) cannot take in the rotation detection pulse e because the AND gate (23) closes, and stops the arithmetic operation. Become. Therefore, the operation of the software for instructing the arithmetic operation of the arithmetic circuit (24) can be stopped, and the power consumption can be reduced.

Reference numerals (25) and (26) denote D flip-flops (pulse period detecting means), which are connected in cascade and connected to T flip-flops. The rotation detection pulse e is supplied to the C terminal of the preceding D flip-flop (25).
Is applied, and both D flip-flops (25) (2)
The set output of the NOR gate (17) is applied to the R terminal of 6), and the frequency-divided output of the rotation detection pulse e is supplied from the Q terminal of the subsequent D flip-flop (26) to one input terminal of the NOR gate (19). Is to occur. That is,
When the cycle of the rotation detection pulse e reaches a predetermined cycle, the D flip-flops (25) and (26)
The reset is performed upon receiving the "1" output of 7). Thereafter, the frequency of the rotation detection pulse e is started to be divided. D flip-flop (2
5) In (26), the reset is continued if the period of the rotation detection pulse e is continuously equal to or longer than the predetermined period. However, if the period of the rotation detection pulse e becomes shorter than the predetermined period, as shown in FIG. When the rotation detection pulse e arrives, a frequency-divided output m of "1" is generated. Therefore, the RS flip-flops (18) and (19) are reset, and the AND gate (2)
3) opens, and the rotation detection pulse e starts to be applied again to the arithmetic circuit (24). In addition, D flip-flop (25)
The number of stages in (26) may be any number as long as it can be determined that the rotation detection pulse e with a period less than the predetermined period is generated after the rotation detection pulse e with the period of the predetermined period or more is generated. There is no problem even if it is more than a step.

As described above, according to the present embodiment, when the period of the rotation detection pulse e is equal to or longer than the predetermined period, AN
Since the D gate (23) is closed and the arithmetic circuit (24) is not operated, a circuit capable of reducing power consumption can be provided.

[0016]

According to the present invention, when the cycle of the rotation detection pulse is within a predetermined period or more, the gate means interposed between the pulse generation means and the calculation means is closed, and the rotation detection pulse is calculated by the calculation means. Not to be applied. As a result, there is an advantage that the operation of the arithmetic unit can be stopped and the power consumption can be reduced. This is very effective for using a battery-driven speedometer or the like for a long time.

[Brief description of the drawings]

FIG. 1 is a diagram showing an input control circuit of a rotation detection pulse according to the present invention.

FIG. 2 is a time chart showing waveforms of respective parts of the pulse generating means of FIG.

FIG. 3 is a time chart showing waveforms of respective parts of the control means of FIG. 1;

FIG. 4 is a time chart showing waveforms of respective parts of the pulse period detecting means of FIG. 1;

FIG. 5 is a diagram showing a state where a pulse signal generator is attached to a bicycle.

FIG. 6 is a diagram showing a pulse signal corresponding to a rotation speed of a wheel.

FIG. 7 is a diagram illustrating a relationship between a wheel cycle and an hourly speed.

[Explanation of symbols]

 (1) Wheel (5) Pulse generating means (13) Counter (14) (23) AND gate (15) Control means (24) Arithmetic circuit (25) (26) D flip-flop

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-7-5186 (JP, A) JP-A-59-82871 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G01P 3/489 G06F 1/32

Claims (3)

(57) [Claims] 1. A pulse generating means for detecting rotation of a wheel and generating a rotation detection pulse having a different cycle according to the rotation speed of the wheel, and the wheel based on the size of the wheel and the cycle of the rotation detection pulse. Calculating means for calculating the rotation speed of the motor; gate means interposed between the pulse generating means and the calculating means for passing or blocking the rotation detection pulse; and counting a clock of a predetermined frequency reset by the rotation detection pulse. Counter means for monitoring the count value of the counter means to detect that the cycle of the rotation detection pulse has become equal to or longer than a predetermined cycle; and a state in which the cycle of the rotation detection pulse has expanded to a predetermined cycle or more. Pulse period detecting means for detecting that the time has been shortened to less than a predetermined period, and Control means for resetting the counter means, closing the gate means, and opening the gate means in accordance with the detection output of the pulse cycle detection means, wherein the cycle of the rotation detection pulse is within a predetermined cycle or more, A rotation detection pulse input control circuit, wherein a rotation detection pulse is not applied to the arithmetic means. 2. The rotation detecting apparatus according to claim 1, wherein said pulse period detecting means detects that a plurality of rotation detection pulses having a period less than a predetermined period have been generated after a rotation detection pulse having a period equal to or longer than a predetermined period has been generated. Pulse input control circuit. 3. The pulse period detecting means includes a plurality of cascade-connected flip-flops, wherein the plurality of flip-flops are reset according to a detection output of the time-over detecting means, and thereafter, a plurality of rotation detecting pulses shorter than a predetermined period. 3. A rotation detection pulse input control circuit according to claim 2, wherein a frequency-divided output for controlling said gate means is generated by dividing frequency.