JP3141541B2 - Method for activating impurities and method for manufacturing thin film transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an LSI or an active matrix type flat display device.

[0002]

2. Description of the Related Art In an LSI in which the miniaturization is remarkably advanced and the operation speed is increasing year by year, it is an urgent task to reduce the resistance of a gate wiring of a MOS transistor. Instead of polycrystalline silicon thin film, Mo, T
Attempts have been made to use a, W, and these silicides for the gate electrode.

Further, in recent years, active matrix type liquid crystal displays, which are leading flat displays, have begun to be mass-produced. The smaller the resistance of the gate line of the liquid crystal display, the larger the screen size and the higher the resolution can be 10 inches or more diagonally.

For the gate line, a Ta thin film is often used because it has a lower resistance than a polycrystalline silicon thin film, has excellent workability, and can reduce defects by an oxide film formed by anodization.

In order to cope with an increase in the size, definition, and speed of a liquid crystal display, it is required to form a thin film transistor in which a source / drain region is self-aligned with a gate electrode. In order to form a thin film transistor in which the p-type and n-type source / drain regions are self-aligned with the gate electrode on the same substrate, a coplanar structure is advantageous. When fabricating an LSI on a silicon substrate, impurities are activated by thermal annealing at 800 ° C. or higher. However, the glass substrate used for the liquid crystal display, which is inexpensive, has a strain point of about 700 ° C.
It is not possible to adopt a process at which the temperature becomes 0 ° C. or higher. Therefore, activation of impurities ion-implanted into the source / drain regions by laser beam irradiation has been attempted.

In this method, since the temperature of the entire glass substrate is equal to or lower than the strain point, no problematic phenomenon such as expansion and contraction or distortion of the glass occurs. However, this thin film transistor forming method has several problems.

First, as shown in FIG. 19A, a silicon oxide film UDL is formed on a heat-resistant glass substrate GLS to a thickness of 200 nm by an atmospheric pressure chemical vapor deposition method,
Anneal in an inert gas such as nitrogen at a temperature of ° C. for 2 hours. Next, a first silicon film is deposited on the silicon oxide film UDL by a reduced pressure chemical vapor deposition method to a thickness of 150 nm and patterned. The resist is patterned by lithography, and the silicon layer is patterned into an island shape in a tapered shape by dry etching using fluorocarbon as a reaction gas.

Next, a second silicon thin film having a thickness of 100 nm is formed by low pressure chemical vapor deposition so as to cover the island-shaped silicon film formed as described above. The conditions for forming this silicon film may be the same as those for the first silicon film. If necessary, they may be formed under different conditions. Next, the second silicon film is patterned into an island shape by lithography. The first silicon layer is entirely covered by the second silicon layer.

Next, X is added to the silicon layer formed above.
An eCl excimer laser beam is irradiated in a vacuum at a pressure of 1 mtorr or less to form a polycrystalline silicon film. A laser intensity of 250 to 500 mJcm ^-2 is suitable. By this laser beam irradiation, the particle size is 200 nm
It becomes polycrystalline silicon of a degree crystal.

Next, a silicon oxide film serving as a gate insulating film GIS is formed to a thickness of 120 nm by electron cyclotron resonance chemical vapor deposition so as to cover the above-mentioned polycrystalline silicon.

Next, a metal thin film is formed so as to cover the gate insulating film GIS, and is patterned by lithography to form a gate electrode PGE.

Next, the source is
Impurities are implanted into the drain region.

When forming a P-type transistor, B
And for N-type transistors, P is 3 × 10
Inject at a concentration of ¹⁵ cm ^-2 . Next, as shown in FIG. 19B, the XeCl excimer laser LSR is
Irradiation at an intensity of mJcm ^-2 is performed to reduce the
Activate the impurities implanted in the CA DRA. As a result, the sheet resistance of the source / drain region becomes 1 kΩ / □ or less.

Next, as shown in FIG. 19C, a first interlayer insulating film FIL is formed, a contact hole is formed, a source electrode is formed, and a second interlayer insulating film is formed.
Form a contact hole, further form a drain electrode, form a passivation film, and perform hydrogen plasma treatment if necessary, and make the source / drain region self-aligned with the gate electrode. Had formed.

[0015]

However, the conventional method has the following problems.

First, the impurity is activated by irradiating the impurity with a laser. However, since the laser beam is applied only to the source / drain regions, the silicon film in the source / drain regions and the channel below the gate electrode are activated. Because crystal inconsistency occurs between the parts of the silicon film,
There is a problem that a leak current between the source and the drain of the completed thin film transistor becomes large.

Further, when the material of the gate electrode PGE is Ta, the laser irradiation LSR for activating the impurity causes
Not only does the gate electrode evaporate or peel off,
Even if no abnormality is observed by observation with an optical microscope, there is a problem that the gate insulating film is deteriorated due to the deterioration of the gate electrode and the leak current is increased.

In order to eliminate the delay of the scanning line, a low-resistance metal thin film such as Ta is used as a material for the gate electrode, and the impurities in the source / drain regions injected in a self-aligned manner with respect to the gate electrode are irradiated with excimer laser. The activation method has the problems of leakage between the source and drain and damage to the gate electrode as described above. Therefore, there has been a demand for a method of manufacturing a thin film transistor in which the gate electrode is a metal thin film and the activation of impurities can be activated at room temperature by laser irradiation.

[0019]

According to the present invention, there is provided a method for activating an impurity, comprising: forming an insulating film on a silicon layer; forming a metal thin film on the insulating film and patterning the same; And selectively irradiating the silicon layer with an energy beam in a helium gas atmosphere to activate the impurities in the silicon layer.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the illustrated embodiments.

As shown in FIG. 1, a 200-nm-thick silicon oxide film UDL is formed on a GLS on an insulating substrate such as a transparent heat-resistant glass substrate by atmospheric pressure chemical vapor deposition. Next, the first silicon layer is formed to a thickness of 100 nm by a low pressure chemical vapor deposition method using monosilane as a reaction gas.
And is patterned in an island shape using a lithography method. Further, a second silicon layer is formed to a thickness of 50 nm so as to cover the island-shaped first silicon layer,
Patterning is performed by lithography so as to connect the plurality of island-shaped first silicon layers. Next, a silicon oxide film having a thickness of 120 nm is formed by electron cyclotron resonance plasma enhanced chemical vapor deposition so as to cover the island-shaped silicon layer, and is continuously formed by electron cyclotron resonance plasma enhanced chemical vapor deposition. 20nm silicon nitride film
To form a coating. The silicon oxide film SLD and the silicon nitride film SND become a gate insulating film GIS of the thin film transistor.

Next, a Ta thin film having a thickness of 500 nm is formed on the gate insulating film GIS by sputtering. When argon is used as the plasma generation gas, this Ta thin film has a tetragonal crystal structure,
It has an electrical resistivity of 0 μΩcm. Further, a silicon nitride film is formed on this Ta thin film by plasma chemical vapor deposition.
It is formed with a thickness of 00 nm. The silicon nitride film and the Ta thin film are simultaneously dry-etched and patterned by lithography. The etching gas contains fluorocarbon. Thereby, the metal thin film TGE and the cap layer BLL are formed.

Next, ions are implanted into the metal thin film TGE through the gate insulating film in a self-aligned manner with respect to the source / drain regions. B is implanted with an energy of 40 keV for forming a p-type thin film transistor, and P is implanted with an energy of 90 keV for an n-type thin film transistor at a concentration of 3 × 10 ¹⁵ cm ⁻² . As a method for ion implantation, a mass separation type ion implantation apparatus or a non-mass separation type bucket type implantation apparatus can be used.

FIG. 2 is a plan view of the laminated film formed in the step shown in FIG. In this example, the island-shaped silicon films are arranged in a logical manner. However, depending on the use of the active matrix type liquid crystal display, the present invention can be used even in a delta-type arrangement in which island-shaped silicon films are alternately arranged. It is possible. PDS and CLS in FIG. 2 are a first silicon layer and a second silicon layer, respectively, which are patterned in an island shape in FIG. At this point, the scanning lines are connected to each other. For this reason, electric charges generated on the substrate by ion implantation can be released to the outside of the substrate through the scanning line, and thus there is an advantage that electric field breakdown of the gate insulating film does not occur.

Next, the substrate is immersed in an electrolytic solution and a current is applied to etch the side surface of the metal thin film TGE to form an etched gate electrode ETG thinner than the metal thin film TGE as shown in FIG. The electrolytic solution dissolves the gate electrode,
Although it is desirable that the gate insulating film is made of a component that is not etched, when the gate electrode material is Ta, hydrofluoric acid is used as the electrolyte. Since the silicon nitride film in contact with the electrolytic solution at room temperature is not etched by hydrofluoric acid, there is no adverse effect on the gate insulating film in the Ta electrolytic etching process. Gate electrode side etching amount is 5
If it is 00 nm, the electrolytic etching time is about 5 minutes.

The method of electrolytic etching will be described below.
The scanning line also serving as the gate electrode of the active matrix substrate is connected to the anode pad APD for electrolysis at the end of the substrate as shown in FIG. As shown in FIG.
The NL is immersed in the electrolytic solution ESL, and connected to the electrolytic anode pad APD of the substrate PNL with a metal clip or the like. The wiring ADE from the clip CLP is connected to a constant voltage generator (potentiometer) PCR. A cathode CED made of platinum or tantalum is also immersed in the electric field solution and connected to the potentiostat PCR via the wiring LNE. Further, in order to easily control the voltage, the mercury / mercury chloride-based reference electrode SCE is also immersed in the electric field solution, and the potentiostat PCR is performed through the wiring LNE.
It is connected to the. Further, a charge measuring device (coulomb meter) is connected to a potentiostat in order to measure a charge required for electrolysis. The reference electrode is not limited to the mercury / mercury chloride system, but may be a silver / silver chloride system.

4 V against mercury / silver chloride reference electrode SCE
At a potential of Ta, Ta is sufficiently electrolyzed. The side etching amount of Ta can be controlled by measuring the amount of electric charge flowing by electrolysis with a coulomb meter. For example, the scan line T
The thickness of a is 500 nm, the number of scanning lines is 480, the length is 150 mm, each scanning line is connected to the wiring pad APD for electrolysis and the wiring of Ta is 200 mm, and the side etching amount is 500 nm. If so, the Ta to be electrolyzed is 3.61 × 10 ⁻⁵ cm ³ and the mass is 6.01 × 10 ⁻⁴ g, so the required charge amount is 0.320 c. If the ADE wiring of the potentiostat is cut off when the clone meter measures this charge amount, the side etching amount L of Ta becomes 500 nm. Further, the substrate PNL is immediately transferred to a pure water container and washed.

Next, the cap layer BLL is peeled off with a hot phosphoric acid solution. Silicon nitride film S that comes in contact with hot phosphoric acid solution at the same time
The ND is also stripped, but the silicon nitride film SND immediately below the gate electrode ETG is not etched.

The purpose of this side etching is to provide an offset region between the gate electrode and the source / drain to reduce the leak current between the source / drain of the thin film transistor. If this side etching is performed by a dry etching method using a gas containing fluorocarbon, high-energy plasma collides with the gate insulating film.
As shown in FIG. 6, a damaged SEC occurs in the gate insulating film,
This may cause the electrical characteristics of the thin film transistor to deteriorate. If there is a step using a temperature of 800 ° C. or more after the side etching of the gate electrode by the dry etching method, the damaged SEC of the gate insulating film disappears and there is no problem. However, in the manufacture of an active matrix substrate using a glass substrate having a strain point of about 700 ° C., a high temperature of 800 ° C. or higher cannot be used. Therefore, the side etching of the gate electrode is preferably a wet etching method that does not damage the gate electrode.
The wet etching method does not have the above plasma damage, but it is difficult to perform uniform etching. However, with the electrolytic etching of the present invention, etching can be uniformly performed at the same rate over the entire substrate, and the etching amount is also small. It can be freely controlled by the amount of charge. Next, as shown in FIG. 7, in order to activate the impurities implanted into the source / drain regions, an energy beam is irradiated LSR in He gas HGC from the side of the substrate where the elements are formed. The energy beam has a half-width of 50 ns and a wavelength of 308 nm.
It is an eCl excimer laser, and the irradiation intensity immediately before the substrate is 2
It is 40 mJcm ^-2 .

As shown in FIG. 8A, when an excimer laser is irradiated in the air or in a vacuum, the Ta thin film serving as the gate electrode absorbs laser energy and becomes high in temperature, as shown in FIG. 8B. Damage occurs such as sublimation or peeling from the gate insulating film, and the gate electrode is destroyed. I do. In order to prevent this damage, laser irradiation LSR is performed in He gas that has a cooling effect so that the gate electrode ETG does not become hot. The He gas contacts not only the gate electrode but also the gate insulating film to cool it, but the wavelength is 308 nm.
m laser beam passes through the silicon oxide film and
Since the impurities are absorbed by the silicon layer in the drain region, the impurities in this region are activated without any problem.

In the activation of impurities by excimer laser irradiation, the temperature of the silicon layer instantaneously reaches about 1000 ° C. and reaches room temperature in a short period of several hundred nsec, so that there is almost no impurity diffusion. In addition, there is an advantage that the offset region L between the gate electrode and the source / drain region can be easily controlled.

By the laser irradiation LSR, the impurities in the source / drain regions are activated. When the impurities are P, the electric resistivity is 1.2 mΩcm, and when the impurities are B, the electric resistivity is 2.5 mΩcm.

The formation of the source / drain regions by this method has the following advantages.

First, a conventional method for activating impurities in source / drain regions by laser irradiation is shown in FIG. FIG.
(A) shows a source / drain region SDA after ion implantation.
FIG. 4 is a diagram schematically illustrating a boundary portion between a gate electrode and a gate electrode. The crystal of the silicon layer in the source / drain region is broken and becomes amorphous by the ion implantation, but the active silicon layer CLC of the thin film transistor, in which the penetration of high-energy ion particles is blocked by the gate electrode, is polycrystalline. Held in state. Then, a transition region EGD between an amorphous state and a polycrystalline state exists between the silicon layer SDA and the active silicon layer CLC in the source / drain region. An excimer laser with a wavelength of 308 nm passes through the gate insulating film made of transparent silicon oxide in the silicon layer in this state, and the amorphous silicon layer in the source / drain region SDA immediately becomes a polycrystalline silicon film containing impurities. However, in the transition region of the crystalline state of silicon, the laser beam is partially blocked by the gate electrode, so that a microcrystalline silicon layer MCR is formed as shown in FIG. 9B.

The off-state current of the field effect transistor including the thin film transistor is caused by the trap level at the boundary between the drain region and the active silicon layer. FIG. 9B
When the silicon layer in the boundary region is made of microcrystalline silicon, the trap state density is increased and the off-state current of the completed transistor is increased. The essence of this trap level is the existence of dangling bonds of silicon atoms constituting the crystal lattice. As a result of hydrogen plasma treatment, hydrogen atoms combine with silicon atoms using dangling bonds, which reduces trap levels, but as described above, the microcrystalline silicon generated in the transition region between the source / drain region and the active silicon layer In this case, since the crystal lattice of silicon atoms is complicated, hydrogen atoms cannot be arranged in dangling bonds in many cases.

The effect of the present invention that can improve the above phenomenon and reduce the occurrence of off-current will be described.

FIG. 10A is the same as FIG. 9A. After the ion implantation, the gate electrode is side-etched by electrolytic etching described in FIG.
An offset region L is formed as shown in FIG. As a result, the laser beam for activating the impurities is applied not only to the source / drain regions but also to the transition regions EGD between the amorphous silicon layer and the polycrystalline silicon layer. Therefore, sufficient heat required for crystallization is generated in the transition region EGD, so that polycrystalline silicon having a grain size of about 200 nm is formed as in the case of the source / drain regions, as shown in FIG. . Further, since the crystal state of the active silicon layer CLC is continuously taken over, the polycrystalline silicon is extremely high quality.

Therefore, according to the present invention, since there is no trap level at the boundary between the drain region and the active silicon layer, a transistor without off current can be formed.

Next, in order to anodize the gate electrode and the gate line, as shown in FIG.
Soak in LT. The electrolyte is suitably citric acid, phosphoric acid, phosphorous acid, hypophosphorous acid, chloric acid, perchloric acid, or a mixed acid thereof. The anodizing temperature may be room temperature. The gate line of the substrate PNL is connected at the edge of the substrate as shown in FIG. 12 and has a terminal AP common to the electrolytic etching performed in FIG.
D is connected to a potentiostat PCR via a wiring ADE and LNE sandwiched by a clip CLP. Cathode CDE
May be the same as that used in the electrolytic etching.
At this time, the reference electrode SCE is also used. Since the thickness of the anodic oxide film can be controlled by the voltage applied to the anode, the coulomb meter used for electrolytic etching is not necessarily required for anodic oxidation. By applying a potential of 100 V to the anode ADE with respect to the reference electrode, an anodic oxide film ATX having a thickness of 170 nm is formed on the gate electrode and the gate line surface as shown in FIG. In this anodic oxidation, the gate line terminal GLP shown in FIG. 12 is covered with a nitride film or an organic thin film so as not to anodize. After the anodic oxidation, the nitride film or the organic thin film is peeled. Further, as shown in FIG. 14, after anodic oxidation, the respective gate lines are separated by lithographic etching.

Next, as shown in FIG. 15, an interlayer insulating film FIL is formed of a silicon oxide film by the atmospheric pressure chemical vapor deposition method.
Next, a contact hole reaching the source region ASC and the drain region ADR where the impurity is activated is formed. Next, a molybdenum film is deposited to a thickness of 500 nm by sputtering and patterned by lithography to form a source electrode SCE also serving as a data line. Next, a second interlayer insulating film SIL is formed with a silicon oxide film formed by a normal pressure chemical vapor deposition method. Next, a contact hole reaching the drain region ADR is formed, a thin film serving as a drain electrode is formed and patterned by lithography. If the drain electrode is the pixel electrode PXL and the display method of the liquid crystal display is a reflection type, then the material of the drain electrode is suitably aluminum having a large visible light reflectance. If the display method of the liquid crystal display is a transmission type, tin oxide / indium having a large visible light transmittance is suitable, but other transmission materials may be used.

Next, in order to protect the completed device from an external environment such as humidity and contamination, a silicon nitride film as a passivation film PSL is formed by plasma chemical vapor deposition with a thickness of 300 nm.

Further, if necessary, hydrogen treatment is performed by a hydrogen plasma method.

FIG. 16 is a plan view of the active matrix substrate formed by the above steps. GLN indicates a gate line, SLN indicates a data line, PXL indicates a pixel electrode, SLP indicates an external terminal of the data line, TFT indicates a thin film transistor, and CRS indicates an intersection of the gate line and the data line.

FIG. 17 is a sectional view of an intersection CRS between the gate line and the data line shown in FIG.

In the case of an active matrix substrate, the gate line GLN and the data line S at the intersection CRS in the substrate are used.
The occurrence of a short circuit failure of the LN becomes a problem. Data line SL
When the insulating film between N and the gate line was only an anodic oxide film, the probability of a short circuit failure occurring at one intersection CRS was 3.5 × 10 ⁻⁶ , which was statistically obtained experimentally. . On the other hand, when the insulating film between the data line SLN and the gate line is only the interlayer insulating film FIL, the probability is 2.4 × 10
^-6 . However, when the insulating film between the intersections was two layers of the anodic oxide film ATX and the interlayer insulating film FIL, the probability was drastically reduced to 8.4 × 10 ⁻¹² . This is an active matrix substrate having 640 data lines and 480 gate lines GLN, and when the insulating film between the intersections CRS is only the anodic oxide film, when the interlayer insulating film FIL is only, and when the anodic oxide film ATX is used. In the case of two layers of the interlayer insulating film FIL, this means that the short circuit failure occurs in 34%, 48%, and ０0% of the substrate, respectively. Produced a good effect.

Curve A in FIG. 18 is a curve B according to the method of the present invention.
Shows electrical characteristics of a drain current with respect to a change in a gate voltage of an n-type thin film transistor manufactured by a conventional method. The ON current indicated in the region where the gate voltage is positive is
There is little difference between the present invention and the conventional method.

However, in the present invention, the off-state current in the region where the gate voltage is negative was significantly reduced by a factor of 100 compared with the conventional method.

When the present invention has the above-mentioned constitutional requirements, the following remarkable effects can be obtained. (A) Since the helium gas has a cooling effect and the silicon layer is irradiated with a laser beam in a helium gas atmosphere, it is possible to avoid a high temperature of the gate electrode or the gate insulating film. Therefore, damage such as peeling of the gate electrode from the gate insulating film can be suppressed, and the laser beam can be reliably absorbed by the silicon layer.

[0049]

[0050]

[0051]

[0052]

[0053]

[0054]

[0055]

[0056]

[0057]

[0058]

[Brief description of the drawings]

FIG. 1 is a process sectional view of a method for manufacturing a thin film transistor of the present invention.

FIG. 2 is a process plan view of the method for manufacturing a thin film transistor of the present invention.

FIG. 3 is a process sectional view of a method for manufacturing a thin film transistor of the present invention.

FIG. 4 is a process plan view of the method for manufacturing a thin film transistor of the present invention.

FIG. 5 is a schematic view of an electrolytic etching apparatus according to the present invention.

FIG. 6 is a problem diagram of a conventional method for manufacturing a thin film transistor.

FIG. 7 is a process sectional view of the method for manufacturing a thin film transistor of the present invention.

FIG. 8 is a problem diagram of a conventional method for manufacturing a thin film transistor.

FIG. 9 is a problem diagram of a conventional method for manufacturing a thin film transistor.

FIG. 10 is an improved view of a method for manufacturing a thin film transistor of the present invention.

FIG. 11 is a diagram of an anodizing apparatus in a thin film transistor manufacturing process of the present invention.

FIG. 12 is a process plan view of the method for manufacturing a thin film transistor of the present invention.

FIG. 13 is a process sectional view of a method for manufacturing a thin film transistor of the present invention.

FIG. 14 is a process plan view of the method for manufacturing a thin film transistor of the present invention.

FIG. 15 is a process sectional view of the method for manufacturing a thin film transistor of the present invention.

FIG. 16 is a process plan view of the method for manufacturing a thin film transistor of the present invention.

FIG. 17 is a cross-sectional view of a wiring of a thin film transistor of the present invention.

FIG. 18 is an electrical characteristic diagram of the thin film transistor of the present invention.

FIG. 19 is a process sectional view of a conventional thin film transistor.

[Explanation of symbols]

A: Subthreshold characteristics of the thin film transistor manufactured by the present invention ADE: Anode wiring ADR: Drain region with activated impurities APD: Anode pad ASC: Source region with activated impurities ATX: Anodized film B: Conventional thin film transistor Subthreshold characteristics BLL: Cap layer CDE: Cathode electrode CLC: Polycrystalline active silicon layer CLM: Coulomb meter CLP: Clip CNL: Active silicon layer CRS: Intersection of data line and gate line CSL: Second silicon layer DGE ... Destroyed gate electrode DRA ... Drain region ECB ... Electrolytic vessel EGD ... Transition region between amorphous silicon and polycrystalline silicon ESL ... Electrolytic solution ETG ... Metal gate electrode FIL ... First interlayer insulating film GDE ... Gate electrode GIS ... Gate insulating film G S: glass substrate GLP: gate line terminal HGC: helium gas IPL: ion implantation L: side etching amount LNE: wiring LSR: laser irradiation MCR: microcrystalline silicon PCR: potentiostat PDS: first silicon layer PGE: gate electrode PNL: Substrate PSL: Passivation film PXL: Pixel electrode SCA: Source region SCE: Reference electrode SDA: Source / drain region SDC: Source / drain region in polycrystalline state SEC: Damage of gate interface and gate interface SED: Source electrode SIL ... second interlayer insulating film SLD ... silicon oxide film SND ... silicon nitride film SLN ... data line SLP ... data line terminal TBL ... support TFT ... thin film transistor TGE ... metal thin film UDL ... silicon oxide film

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21 / 265,21 / 268 H01L 21 / 306,21 / 3063

Claims (2)

(57) [Claims] A step of forming an insulating film on a silicon layer, a step of forming a metal thin film on the insulating film and patterning the same, a step of selectively injecting impurities into the silicon layer, and a helium gas atmosphere. Irradiating the silicon layer with an energy beam to activate impurities in the silicon layer. 2. A method for manufacturing a thin film transistor, comprising the step of claim 1.