JP3137970B2 - Shared storage control system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] Regarding a shared storage control method in which packets are transferred between a plurality of clusters serving as access sources and a shared memory unit via a shared memory control unit, the cluster side cannot recover during communication The purpose of this is to prevent deadlock when communication is interrupted due to a serious error and to prevent overhead in other clusters. When communication is interrupted due to an error on the cluster side, the dedicated circuit in the shared memory control unit In addition, the configuration is such that initialization of the common circuit, unlocking of the lock register, and data checking and inhibition of validity over the access time of the receiver circuit from the shared memory unit are performed.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shared storage control system for performing data transfer between a shared memory unit of a plurality of clusters serving as access devices by packet transfer via a shared memory control unit.

The cluster consists of one or more CPUs, CPU and channel devices (C
H) and a main storage control unit (MCU) that connects and accesses a main storage (MSU) and the like, and constitutes one system. One or a plurality of such clustered systems are connected to a system storage unit (SSU). Execution of a huge program using a shared storage unit having a large capacity compared to the main storage of the cluster, high-speed execution by executing a program with multiple tasks in a plurality of clusters, and The system is duplicated by making the cluster redundant.

Access and data transfer from the cluster to the shared memory are performed by packet transfer. For example, when a read access is received from a cluster, a communication state is established with the cluster, and the communication state is maintained until packet transfer of data obtained by read access of the shared memory unit to the cluster is completed.

However, if an unrecoverable error occurs on the cluster side during communication, in the worst case, a deadlock occurs in which the function of the shared memory control unit is completely stopped. It takes time to leave the access control state, and this causes overhead for access from other clusters. Therefore, it is desirable to avoid deadlock due to communication interruption when a cluster error occurs, and to minimize the influence on access from other clusters.

2. Description of the Related Art Conventionally, in a plurality of clusters as an access source device configuring one system, a shared memory control unit, and a shared storage control method including a shared memory unit, each cluster for the shared memory unit has Priority control of the shared memory control unit, occupation control of the memory area using the lock address, memory access by pipeline control, and packet transfer of access data to the shared memory are performed for the access of the shared memory.

[Problems to be Solved by the Invention] However, in such a conventional shared storage control method, the cluster connected to the shared memory control device causes an unrecoverable hard error or the like during the memory access communication. Communication may be suddenly interrupted. When the communication is interrupted due to the occurrence of an error, the shared memory control circuit unit is in the setting of various control parameters for enabling packet transfer with the cluster in which the error has occurred and in a circuit operating state. Since normal access cannot be continued, there is a problem that a runaway occurs and an out-of-control deadlock occurs after an error occurs, and that access from another cluster becomes an overhead because it takes time to recover to an initial state.

The present invention has been made in view of such a conventional problem, and even if communication is interrupted due to the occurrence of an unrecoverable error on the cluster side, the deadlock of shared storage control and the occurrence of overhead in other clusters are avoided. It is an object of the present invention to provide a shared storage control system for preventing such a situation.

[Means for Solving the Problems] FIG. 1 is an explanatory view of the principle of the present invention.

First, the present invention provides a shared storage control system for performing packet transfer for read or write access between an access source device and a shared memory unit under the control of a shared memory control unit. A plurality of reception buffers provided for each access source device and storing access data received from a corresponding access source device, provided for each access source device following the reception buffer, and provided in the shared memory unit. A plurality of movers that output write data and output a write or read access command to an access pipeline that controls the shared memory unit, and when two or more movers are simultaneously accessed from the access source device, A priority circuit for permitting output of a specific mover according to a predetermined procedure; A transmission buffer provided for each access device and holding read data from the shared memory unit for transferring to the access source device; and a transmission buffer provided for each access source device for receiving and responding to access data from the access source device. A transmission / reception circuit for storing the read data in the transmission buffer to a corresponding access source device while storing the data in the reception buffer, and the access source device includes a transmission / reception circuit for transmitting an operation-out signal for connection. The transmission / reception circuit of the shared memory control unit is provided for each access source device, and upon receiving an operation-out signal from the transmission / reception circuit of the access source device, turns on an operation-in signal for connection and communicates with the corresponding access source device. A communication state is created, and the error processing means is configured such that the shared memory During communication with the access source device, the operation out signal generated from the transmission / reception circuit of the access source device is interrupted due to the occurrence of an unrecoverable error on the access source device side. When the operation-in signal generated from the transmission / reception circuit is cut off, an interface clear signal is generated inside the shared memory control unit, and recovery processing is performed so as to suppress deadlock and overhead caused by communication cut-off. An error processing unit, wherein the error processing unit initializes a dedicated circuit of an access source device in which an error has occurred based on the interface clear signal; and an access source based on the interface clear signal. Second initialization means for initializing a common control circuit common to the devices; Clearing means for clearing the valid bit and releasing the lock only when the access source identification code of the lock register storing the lock address of the shared memory unit matches the access source device in which the error has occurred based on the interface clear signal. Means for suppressing output of read data by an access of an access source device in which an error has occurred for a receiver circuit for receiving a signal from the shared memory unit based on the interface clear signal for a time equal to or longer than a shared memory access time; Wherein the clearing means comprises: a decoder for decoding an access source ID stored in the lock register; and a logical product of a decoded output of the decoder and an interface clear signal corresponding to the access source device which becomes valid when an error occurs. AND gates that detect And a clear gate for turning off a valid bit of the lock register by an AND output obtained from any of the plurality of AND gates, and performing an error recovery process on an access source device in which an error has occurred. And

Here, the second initialization means 26 initializes the priority circuit as the shared control circuit 24.

Further, the suppression means includes a decoder for decoding an access source ID stored at a predetermined number of stages of the access pipeline controlling the shared memory unit and identifying an access source device in which an error has occurred; A plurality of timer counters provided for each access source device which start upon receiving a preset of a predetermined time value which is equal to or longer than the access time of the shared memory unit; and an output terminal of the decoder and an output terminal of the plurality of timer counters. A gate circuit for inputting for each device and suppressing output of read data from the shared memory to the receiver circuit until the timer counter reaches a preset time in a state where the identification output of the access source device is obtained; Characterized by having;

[Operation] According to the shared storage control system of the present invention having such a configuration, when an unrecoverable error occurs on the cluster side as the access source device, the shared memory control unit detects the communication means and clears the interface. A signal is generated, and a dedicated circuit of the cluster in which an error has occurred, such as a reception buffer and a mover, is initialized, and at the same time, a priority circuit as a common control circuit is initialized. If the cluster in which the error has occurred is in a lock acquisition state occupying the access area of the shared memory unit by the access with the lock, the valid bit of the lock register is cleared to OFF and the lock is released.
Further, since abnormal read data is transferred from the shared memory unit to the receiver circuit after the occurrence of the error, the data check of the receiver circuit is suppressed for a predetermined time longer than the access time, and unnecessary error detection is canceled.

As a result, even if an error occurs on the cluster side and communication is interrupted, the shared memory control unit requires a time slightly exceeding the access time, and deadlocks to the same state as when communication with the cluster where the error occurred ended normally. It can be recovered without causing a problem. From the viewpoint of other normal clusters, the shared memory control unit shifts to accepting access to other clusters in about the same time as when there is no error, even if the cluster has an error in the middle. There is no overhead for Kratus.

Embodiment FIG. 2 is an overall configuration diagram of a system to which the shared storage control system of the present invention is applied.

2, 10-1, 10-2,..., 10-n are clusters as access source devices, 12 is a shared memory control unit,
14 is a shared memory unit. Each of the clusters 10-1 to 10-n includes transmission / reception circuits 200-1 to 200-n.
-1 to 200-n are the transmission / reception circuits 300-1 to 300-1 of the shared memory unit 12.
Connected to the shared memory 14 for access (read or write) from the cluster side under the control of the shared memory controller 12 to execute memory access.

FIG. 3 shows the configuration of the cluster of FIG. 2 as a representative of the cluster 10-1, and includes one or more CPUs 100-1 to 100-100.
-N, the channel device (CH) 102 and the main memory (MSU 10
4) Main memory control unit (MC
U) 106 constitutes one system, and one or a plurality of such cluster systems are connected to a shared memory unit 14 constituting a system storage unit (SSU) via a shared memory control unit 12, Executing a huge program using a shared storage unit having a larger capacity than the main storage of the cluster, high-speed execution by executing the program with multiple tasks in a plurality of clusters, and a dual configuration of the shared storage and the cluster The system is being duplicated.

FIG. 4 is a block diagram of an embodiment of the shared memory control unit 12 in FIG.

In FIG. 4, as receiving units from the clusters 10-1 to 10-n, reception buffers 38-1 to 38-n and movers 40-1 to 40-n are provided as the cluster dedicated circuit 20 for each cluster. A priority circuit 24 is provided as a common control circuit for the movers 40-1 to 40-n, and when two or more clusters are simultaneously accessed, access from a specific cluster is permitted according to a predetermined procedure. .

A lock register 30 is provided for the priority circuit 24, and lock control of the shared memory unit 14 is enabled. The lock register 30 includes a valid bit V indicating that the shared memory unit 14 is in a locked state, a lock address of the shared memory unit 14, specifically, a storage unit of a lock start address, and a cluster that currently acquires a lock. Is stored. While the lock of the shared memory unit 14 has been acquired by the lock register 30, normal access from another cluster, that is, access without lock is performed, and the access address overlaps with the lock address. When the comparison is determined, the priority circuit 24 waits until the access is released.

Data outputs from the movers 40-1 to 40-n are supplied to the shared memory unit 14 as write data via the transfer interface 42. Also, access information from the movers 40-1 to 40-n, that is, a read or write access command (start address, length, discance, etc.)
Is an access pipeline via the transfer interface 44
The memory access (read or write) of the shared memory unit 14 and the transfer reception control (at the time of read access) of the read data to the transfer interface 45 of the shared memory control unit 12 are performed by pipeline control by the access loop pine 46. Done. Following the transfer interface 45, a transmission buffer (read buffer) 48-
Transfer interfaces 50-1 to 50-n for transferring read data to each cluster as packets are provided.

In the present invention with respect to such a configuration of the shared memory control unit 12, when an error occurs on the cluster side during communication with a specific cluster and communication is interrupted, deadlock or other clusters may occur. The first initialization circuit 22 as an error processing means for performing a recovery process without causing overhead
A second initialization circuit 26, a lock register clear circuit 32, and a receive check suppression circuit 36 are provided.

The first initialization circuit 22, the second initialization circuit 26, the lock register clear circuit 32, and the receive check suppression circuit 36
Is an interface clear signal INT-CL1 for each cluster generated on the shared memory control unit 12 side when a cluster error occurs.
To n, an error recovery operation is performed.

FIG. 5 is an explanatory diagram showing a communication control state between the clusters 10-1 to 10-n and the shared memory control unit 12 according to the present invention, and FIG. FIG. 2B shows a case where a cluster error occurs.

First, in the normal state, as shown in FIG.
For example, taking the access from the cluster 10-1 as an example, first, the transmission / reception circuit 200-1 of the cluster 10-1 turns on the operation-out signal OP-OUT to establish the communication state with the shared memory control unit 12. I do. This cluster 10-1
Receiving the ON of the operation-out signal OP-OUT from the communication circuit 300-1 of the corresponding shared memory control unit 12
Turns on the operation-in signal OP-IN. The transmission / reception circuits 200-1 and 300-1 between the cluster 10-1 and the shared memory control unit 12 while the two operation-out signals OP-OUT and OP-IN are on.
Communicable state is created.

On the other hand, as shown in FIG. 5 (b), the operation-out signal OP-OUT is turned on in the cluster 10-1, and accordingly, the operation-in signal OP-OUT is caused in the shared memory control unit 12 side.
If an unrecoverable error occurs on the cluster 10-1 side during the communication with IN turned on, the operation out signal OP-OUT from the cluster 10-1 side is cut off due to the occurrence of the error,
It turns off. An operation out signal OP-OUT accompanying the occurrence of an unrecoverable error of the cluster 10-1
Of the transmission / reception circuit 300-
1 issues an interface clear signal INT-CL1 at the same time as turning off the operation-in signal OP-IN, and an interface clear operation, that is, an error recovery processing operation, which will be described below, is started.

Since the cluster that has caused the unrecoverable error cannot access the shared memory unit 14 thereafter, release all configuration control for the shared memory unit 14 and shift to only access within its own system. I do.

Shared memory controller when an error occurs on the cluster side
The interface clear signal INT-CL1 generated on the 12 side is applied to each of the first initialization circuit 22, the second initialization circuit 26, the lock register clear circuit 32, and the receive check suppression circuit 36 shown in FIG. An error recovery process is started when an error occurs in a cluster that is currently communicating, for example, in the cluster 10-1.

First, the first initialization circuit 22 includes reception buffers 38-1 to 38-n, located in the reception circuit units from the clusters 10-1 to 10-n.
The movers 40-1 to 40-n are initialized and the cluster 10
Transmission buffer 48 located in the transmission circuit section for -1 to 10-n
-1 to 48-n and the transfer interfaces 50-1 to 50-n are initialized.

Next, the second initialization circuit 26 initializes the priority circuit 24 as shown in FIG.

FIG. 6A shows the operation of the priority circuit at the time of normal termination, and FIG. 6B shows the operation of the priority circuit at the time of occurrence of a cluster error.

First, in the normal state shown in FIG. 6A, for example, when an access by communication with the cluster 10-1 in the mover 40-1 is received, the priority request signal PR
-REQ is issued to the priority circuit 24. Movers 40
The priority circuit 24, which has received the priority request signal PR-REQ from -1, issues a priority permission signal PR-OK if no access has been received from another cluster having a higher priority at the same time, and the mover 40-1 has the shared memory. The access of the unit 14 is executed. When one packet transfer is completed by access from the mover 40-1, the mover 40-1
-1 issues a priority end signal PR-END, which terminates the priority permission signal PR-OK of the priority circuit 24 and returns to the initial state.

On the other hand, when a cluster error occurs as shown in FIG. 6 (b), the priority permission signal PR-O is transmitted by the priority request signal PR-REQ from the mover 40-1.
When the interface clear signal INT-CL1 is issued due to a cluster error while K is being issued, the priority end signal PR-END is forcibly issued, the priority enable signal PR-OK is turned off, and the priority circuit 24 is turned off. Restore to the initial state.

Next, an embodiment of the lock register clear circuit 32 of FIG. 4 will be described with reference to FIG.

In FIG. 7, the lock register 30 has a valid bit V, a lock address of the shared memory unit 14, specifically, a lock start address, and a storage area of a cluster ID that has acquired the lock. The valid bit V of the lock register 30 turns on the valid bit V when the priority circuit 24 gives a priority permission for the access with lock. At the same time, the lock address (lock start address) is stored, and the ID of the cluster that has acquired the lock is set.

In this state, if a normal access without a lock is performed by another cluster, the lock address comparison determination unit 54
An access address, specifically an access start address, is given to the shared memory unit 14 in which the access address is included in the lock address of the shared memory unit 14 in which the lock is currently acquired based on a comparison with the lock address of the lock register 30. Judgment is made, and if not included, an access permission is issued via a NOR gate 56 (an AND gate having an inverter at the input, that is, a NOR gate), and if included, an access prohibition is issued.

For such a circuit portion of the lock register 30, a decoder 58 and a NOR gate 60-
A circuit including 1 to 60-n and an OR gate 62 is provided. Decoder 58 decodes the cluster ID in lock register 30 and produces an identification output of the cluster currently acquiring the lock. Each cluster identification output of the decoder 58 is output to NOR gates 60-1 to 60-
n. The other of the NOR gates 60-1 to 60-n is supplied with interface clear signals INT-CL1 to CLn of negative polarity for each cluster. Therefore, for example, an error occurs during communication with the cluster 10-1 and the cluster 10-1
When the interface clear signal INT-CL1 corresponding to -1 is turned on, if the lock has been acquired by accessing the cluster 10-1 at this time, the cluster ID of the cluster 10-1 is stored in the lock register 30. NOR gate 60−
The output of the decoder 58 corresponding to 1 is turned on (because the inverter is connected to the output, that is, the state of output 0), and the on output of the NOR gate 60-1 is cleared to the lock register 30 via the OR gates 62 and 52. The valid bit V, which is provided as a signal and is on at that time, is forcibly turned off.

Next, the receive check suppression circuit 36 provided for the access pipeline 46 of FIG. 4 will be described with reference to FIG.

The receive check suppression circuit 36 shown in FIG.
Is provided to the decoder 64, the output of a predetermined number of pipeline stages of the access pipeline 46, that is, the output of the Nth stage. Since the access pipeline 46 stores the ID of the cluster currently being accessed, The N-th cluster ID is input to the decoder 64, and the N-th cluster identification output corresponding to the cluster ID is obtained.

On the other hand, timer counters 66-1 to 66-n are provided corresponding to clusters 10-1 to 10-n. Counters 66-1 to 66
For −n, the initial value T is preset by turning on the interface clear signal obtained by the occurrence of an error in the corresponding cluster. The counters 66-1 to 66-n are a subtractor 74.
-1 to 74-n, and repeats the subtraction of the counter preset value every predetermined clock cycle. Counter 66-1
The counter output of 66-n is kept in the on state (since the inverter is connected to the output, that is, the state of output 0) until the counter preset value becomes zero.

The counter outputs of the counters 66-1 to 66-n are input to one of NOR gates 68-1 to 68-n provided for each cluster, and the other of the NOR gates 68-1 to 68-n is supplied from the decoder 64 to the other. Each cluster identification output is input. Therefore, the NOR gates 68-1 to 68-n obtain the cluster identification output from the decoder 64, that is, output 0, and the counters 66-1 to 68-n.
The counter-on output from 66-n until the preset value becomes less than 0, that is, 0 output is generated while the 0 output is obtained. The outputs of the NOR gates 68-1 to 68-n are collected by a NOR gate 70 and input to one of the NOR gates 72. A negative check valid signal output from the access pipeline 46 to the transfer interface 45 that receives read data from the shared memory unit 14 shown in FIG.

Here, the initial value T preset in the timer counters 66-1 to 66-n is equal to or longer than the access time of the shared memory unit 14.

Next, the operation of FIG. 8 will be described.
Assuming that an error occurs during the communication with the decoder 64, the cluster ID indicating the cluster 10-1 is input to the decoder 64 as the N-th output of the access pipeline 46, and the NOR gate 6
The decoder output for 8-1 becomes 0 and the NOR gate 68-
Given to one.

On the other hand, when an error occurs in the cluster 10-1, the counter is issued with the issuance of the corresponding interface clear signal INT-CL1.
The initial value T is preset for 66-1. The time counter 66-1, having received the preset value of the initial value T, decrements the counter content by one at a predetermined clock cycle by the subtracter 68-1, and repeats the decrement operation until the counter content becomes zero. The output of the timer counter 66-1 maintains the output 0 until the content of the counter becomes 0.
Accordingly, the output of the NOR 68-1 becomes 1, and the NOR gate 72 is disabled via the OR gate 70, and the timer counter 66-
Shared memory unit 14 determined by initial value T preset to 1
For a predetermined time longer than the access time of
The output of read data to the transfer interface 45, which is a receiver circuit, is suppressed.

The above is the error recovery processing in the shared memory control unit 12 when a cluster error occurs.
The state machine corresponding to the cluster provided every 10-n is set to the idle state by the interface clear signal INT-CL corresponding to the cluster in which the error has occurred at that time.

4, the first initialization circuit 22, the second initialization circuit 26, and the lock register clear circuit 32 that perform error recovery when an unrecoverable cluster error occurs for convenience of explanation. Although the receiving check suppression circuit 36 is separately extracted and shown, it is actually integrally formed as a part of each circuit to be processed.

[Effects of the Invention] As described above, according to the present invention, even if communication is interrupted due to occurrence of an unrecoverable error on the cluster side,
The control circuit and the common circuit unit corresponding to the cluster in which the error has occurred can be restored to the initial state based on the interface clear signal accompanying the occurrence of the error, and deadlock of the entire system can be reliably prevented by the occurrence of the cluster error.

In addition, since the recovery processing when a cluster error occurs is completed during the access time of the shared memory unit or a time slightly longer than the access time, when viewed from other clusters, the other processing takes about the same time as no error. Of the other cluster, and therefore does not impose any overhead on the operation of other clusters.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention; FIG. 2 is a diagram illustrating the overall configuration of the present invention; FIG. 3 is a diagram illustrating the cluster configuration of the present invention; FIG. FIG. 6 is a diagram for explaining the operation when a cluster error occurs; FIG. 6 is a diagram for explaining the initialization of a priority circuit according to the present invention; FIG. 7 is a diagram showing the configuration of a clear circuit of a lock register according to the present invention; It is a circuit block diagram. In the figure, 10-1 to 10-n: cluster 12: shared memory control unit 14: shared memory unit 18: error processing means 20: cluster dedicated circuit 22: first initialization means (circuit) 24: common control circuit (priority) Circuit) 26: second initialization means (circuit) 30: lock register 32: clear means (lock register clear circuit) 34: receiver circuit unit 36: suppression means (receiver check suppression circuit) 38-1 to 38-n: data Buffers 40-1 to 40-n: Mover 42,44,46,50-1 to 50-n: Transfer interface 46: Access pipeline 48-1 to 48-n: Transmission buffer (read buffer) 52,62: OR Gate 54: Lock address comparison judging unit 56, 60-1 to 2, 68-1 to n, 70, 72: NOR gate 58, 64: Decoder 66-1 to 66-n: Timer counter 74-1 to 74-n : Subtractors 100-1 to 100-n: CPU 102: Channel device 104: Main storage (MSU) 106: Main storage control unit (MCU) 200-1 to 200-n, 300-1 300-n: transmission and reception circuit

Claims (3)

(57) [Claims] 1. A shared memory control system for performing packet transfer for read or write access between an access source device and a shared memory unit under the control of a shared memory control unit. A plurality of reception buffers provided for each access source device and storing access data received from a corresponding access source device, provided for each access source device following the reception buffer, and provided in the shared memory unit. A plurality of movers that output write data and output a write or read access command to an access pipeline that controls the shared memory unit, and when two or more movers are simultaneously accessed from the access source device, A priority circuit for permitting output of a specific mover according to a predetermined procedure; A transmission buffer provided for each of the access source devices and holding read data from the shared memory unit for transferring to the access source device; and a reception buffer provided for each of the access source devices for receiving and responding to access data from the access source device. A transmission / reception circuit for storing the read data of the transmission buffer to a corresponding access source device while storing the data in a buffer, and the access source device includes a transmission / reception circuit for transmitting an operation-out signal for connection. The transmission / reception circuit of the shared memory control unit is provided for each access source device, and upon receiving an operation-out signal from the transmission / reception circuit of the access source device, turns on an operation-in signal for connection to communicate with the corresponding access source device. A state is created, and the error processing means is configured so that the shared memory When the operation out signal generated from the transmission / reception circuit of the access source device is interrupted due to the occurrence of an unrecoverable error on the access source device side during communication with the source device, the corresponding shared memory control unit side When the operation-in signal generated from the transmission / reception circuit is cut off, an interface clear signal is generated inside the shared memory control unit, and recovery processing is performed so as to suppress deadlock and overhead caused by communication cut-off. An error processing unit, wherein the error processing unit initializes a dedicated circuit of an access source device in which an error has occurred based on the interface clear signal; and an access source based on the interface clear signal. Second initialization means for initializing a common control circuit common to the devices; Clearing means for clearing a valid bit and releasing the lock only when an access source identification code of a lock register storing a lock address of the shared memory unit matches an access source device in which an error has occurred based on an interface clear signal: Inhibiting means for inhibiting output of read data by an access of an access source device having an error during a shared memory access time or more for a receiver circuit for receiving a signal from the shared memory unit based on the interface clear signal; And a decoder for decoding an access source ID stored in the lock register; and a logical product of a decoded output of the decoder and an interface clear signal corresponding to an access source device that is enabled when an error occurs. Multiple AND gates detected for each access source device A clear gate for turning off a valid bit of the lock register by a logical product output obtained from any of the plurality of AND gates, and performing error recovery processing on an access source device in which an error has occurred. Shared storage control system. 2. The shared storage control system according to claim 1, wherein said second initialization means initializes a priority circuit as a common control circuit. 3. The shared storage control system according to claim 1, wherein said inhibiting means decodes an access source ID stored at a predetermined stage number position of said access pipeline controlling said shared memory unit, and generates an error. A decoder for identifying an access source device which has occurred; and a plurality of timer counters provided for each access source device which start upon receiving an preset of a predetermined time value which is equal to or longer than the access time of the shared memory unit by an interface clear signal when an error occurs. And inputting the output terminal of the decoder and the output of the plurality of timer counters for each access source device, and until the timer counter reaches a preset time in a state where the identification output of the access source device is obtained, the common use. A gate circuit for suppressing output of read data from the memory to the receiver circuit. And a shared storage control system.