JP3137758B2 - PN pattern generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PN pattern generating circuit for generating a pseudo-random code having a steep autocorrelation characteristic and a flat cross-correlation characteristic.

[0002]

2. Description of the Related Art In a digital transmission system, in order to confirm that a transmission line is correctly formed at the start of operation, expansion, operation and the like, a monitor is provided via a payload arranged based on a frame configuration of the transmission line. A pseudo random code (hereinafter, referred to as a "PN pattern") is transmitted as a signal, and the receiving end determines whether or not the PN pattern is correctly received. At the transmitting end, a PN pattern generating circuit that sequentially generates a PN pattern with a desired number of bits in parallel is used to divide such a PN pattern and insert it into each frame.

FIG. 4 is a diagram showing a configuration example of a conventional PN pattern generation circuit. In the figure, the parallel developing unit 41
The first output is connected to an input of the latch 42 _1, the input and the selector 44 ₁ to 44 ₃ of the output latch 43 ₁
Connected to the first input of The second output of the parallel expansion unit 41 is connected to the input of the latch 42 _2, the output of which is connected to a second input of the input and the selector 44 _2, 44 ₃ latch 43 _2. A third output of the parallel expansion unit 41 is connected to the input of latch 42 _3, the output of latch 4
3 is ₃ inputs and connected to the third input of the selector 44 _3. The output of latch 43 ₁ is connected to a second input of the selector 44 _1, the output of the latch 43 ₂ selector 44 _1,
It is connected to a third input of 44 _2. The output of the latch 43 ₃ is connected to a fourth input of the selector 44 ₁ to 44 _3, the first to third control outputs of the timing control unit 46 to the select input of the selector is connected individually. Selector 44
The output of the _{1-44 3} outputs a bit string of 48 bit length through the latch 45. Parallel expansion unit 41, latch 4
The 2 _{1-42 3,} 43 _{1-43 3,} 45 of the clock input,
Each clock output of the timing control circuit 46 is connected.

In such a PN pattern generation circuit,
, The parallel developing unit 41 outputs the first to third outputs described above.
48-bit bit string P output prior to₄₇~ P
₃₂, P₃₁~ P₁₆, P_Fifteen~ P₀Of which, P₁₄~ P₀Consists of
The exclusive OR operation shown in FIG. 5 is concurrently performed on the lower 15 bits.
The following bit sequence P₄₇~ P₃₂, P ₃₁
~ P₁₆, P_Fifteen~ P₀Generate Generated in this way
The bit string to be stored is a 15 bit
A division circuit formed using a shift register of
Via the remainder to the primitive polynomial (X^Fifteen+ X + 1)
Of the PN pattern obtained by dividing
Equal to 48 bits and output from the timing control unit 46.
Latch 42 in synchronization with the clock₁~ 42_ThreeOutput
And latch 43₁~ 43_ThreeIs transmitted to the output.

[0005] The timing control unit 46, as shown in FIG. 6 (a), when sending a PN pattern continuously dividing one by 48 bits in the payload of each frame, the selector 44 ₁ to 44 ₃ and the latch 45 through the bit sequence P ₄₇ to be respectively outputted from the latch 43 ₁ to 43 ₃
To P _32, and sends the _{P 31 ~P 16, P 15 ~P} 0.

However, for example, as indicated by hatching in FIG. 6B, a sequential number is assigned to a specific field of the above-described payload (here, the first 16 bits on the payload for simplicity). When other information is arranged, a bit string having the same number of bits as the length of the field (hereinafter, a PN pattern formed of such a bit string is referred to as a “missing PN pattern”) .) Need to be placed. In such a case, the timing control unit 46
The selector 44 _{1-44 3} each latch 43 _3, 42
_1, 43 or to select the _second output (Fig. 7), the latch 4
By 2 _1, 43 _2, 43 to select the _third output (Fig. 7), it generates a PN pattern of missing teeth mentioned above.

[0007]

By the way, in such a conventional PN pattern generating circuit, the parallel developing section 41 is used.
The bit strings output in parallel by the latches 42 ₁ to 42 4
2 _3, 43 _{1-43 3} delays through, further to have generated a PN pattern of the missing tooth by rearranging of these bit strings via the selector 44 ₁ to 44 _3, the latch 42 ₁ to 42 ₃ must control complex synchronization based on 43 _{1-43 3} and selectors 44 ₁ to 44 ₃ number of elements constituting the lot, and the timing controller 46 clocks and frame structure described above these latches and the selector Therefore, the circuit scale was large.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a PN pattern generating circuit capable of reliably generating a missing PN pattern by simplifying a circuit configuration.

[0009]

FIG. 1 is a block diagram showing the principle of the present invention. The present invention provides a generating means 11 for repeatedly generating a pseudo-random code by repeatedly dividing an externally applied bit string by a primitive polynomial, and a desired number of bits among bits included in the pseudo-random code generated by the generating means 11 Selecting means 13 for selecting a continuous bit that has been traced back to provide a bit string.

[0010]

According to the present invention, the selection means 13 determines the bit string to be divided by the primitive polynomial in order for the generation means 11 to generate the subsequent pseudo-random code, as a bit string included in the pseudo-random code already generated by the generation means 11. Among them, consecutive bits retrospectively desired number of bits are selected. The generation means 11
After outputting the same bit pattern as the end of the pseudo-random code already generated over such a desired number of bits, a subsequent pseudo-random code is generated.

That is, as compared with the conventional example in which a normal pseudo-random code which does not include the same bit pattern which is output redundantly and which does not include the same bit pattern and performs the process of rearranging the bit string is performed, the storage means for performing the rearrangement is performed. And the selection means are not required, and the procedure for controlling these means is simplified, so that the PN pattern with missing teeth can be reliably generated by simplifying the circuit configuration.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 2 is a diagram showing one embodiment of the present invention.

In the figure, components having the same functions and configurations as those shown in FIG. 4 are denoted by the same reference numerals, and description thereof is omitted here. In the present embodiment, the parallel expansion unit 21 having the same internal configuration and the above-described external input terminal of the lower 15 bits is arranged in place of the parallel expansion unit 41 in this embodiment. given directly output to the input of the latch 45, of the bit stream P ₄₇ to P ₀ being outputted from the latch 45, and the lower 15 bits P ₁₄ to P ₀ of P ₃₁ to P ₁₆ adjacent to these bits, the lower A selector 22 for selecting 15 bits P _{30 to} P ₁₆ and providing the external input terminal described above is provided, and a timing control unit 23 for supplying a selection signal to the selector and supplying a clock to the parallel development unit 21 and the latch 45 is provided. The point is that it is arranged in place of the timing control unit 46.

In the correspondence between the present embodiment and the block diagram shown in FIG. 1, the parallel developing unit 21 and the timing control unit 23 correspond to the generation unit 11 and the latch 4
5, the selector 22 and the timing controller 23 correspond to the selector 13.

FIG. 3 is a diagram for explaining the operation of the present embodiment. Hereinafter, the operation of the present embodiment will be described with reference to FIGS. The timing controller 23 always supplies a clock to the latch 45 in the same manner as in the conventional example. However, when the PN pattern is arranged in all the payloads of the subsequent frame, the lower 15 bits P _{14 to} P _{0 are} supplied to the selector 22. (FIG. 3), the parallel developing unit 21 generates a continuous PN pattern.

However, when information other than the PN pattern is arranged at the beginning of the payload of the subsequent frame, the timing control unit 23 selects the 15 bits P _{30 to} P ₁₆ described above over a single frame period. Is given (FIG. 3). The parallel expansion unit 21 outputs the bit sequence of the higher order bit of the PN pattern in the same manner as in the conventional example, and the bit sequence equal to the result obtained by dividing the 15-bit bit sequence given to the external input terminal by the primitive polynomial described above. Is output. Therefore, the parallel developing unit 21 generates the same bit sequence as the least significant 16 bits P _{15 to} P ₀ of the 48-bit length bit sequence previously output, and the subsequent 32-bit bit sequence forming a PN pattern continuous with the bit sequence. Is output (FIG. 3).

Further, in the present embodiment, the timing control unit 46 in the conventional example is compared to the number of bits of the selection signal supplied to the selector 44 ₁ to 44 ₃ ( "6" or "12"), development portion 21 the selector 22 , The number of bits of the selection signal to be supplied is "1", and the latches 42 _{1 to} 42 ₃ , 43 ₁ to 43 ₃ and the selectors 44 ₁ to 44 ₃ used in the conventional example are used.
44 ₃ so becomes unnecessary, the circuit scale is significantly reduced.

As described above, according to this embodiment, it is possible to reliably generate a missing PN pattern using a circuit having a simple configuration. Although the present embodiment employs a circuit that generates a PN pattern in parallel every 48 bits by adapting the missing PN pattern to the digital transmission path to be transmitted, the present invention employs such a PN pattern. The generation method is not limited. For example, a bit string set in a register is converted to a predetermined bit string by a clock having a frequency higher than the maximum number of bits of the PN pattern to be transmitted in a unit frame with respect to the frame frequency of the digital transmission path described above. A method of repeatedly dividing by a primitive polynomial may be used, and a method of latching the output of the circuit at a predetermined field timing may be used.The same circuit is operated in a bit-synchronized manner at a predetermined field timing to operate in series. Alternatively, a circuit that generates a PN pattern may be used.

In the present embodiment, only the earliest 16-bit length field out of the fields arranged in each frame has the last 16 bits of the previously generated PN pattern.
Although the same bit pattern as the bit is duplicately generated and arranged, the present invention can be applied regardless of the position of the missing PN pattern and the number of bits.

Further, in this embodiment, the parallel developing unit 2
In order to obtain a bit string to be given to 1, the already generated PN pattern is latched, and a continuous bit string included in the PN pattern is selected via the selector 22. The present invention employs such a method. Without limitation, for example,
A method may be used in which the already generated PN is sequentially parallel-to-serial converted and the amount of delay (the number of bits) accompanying the serial conversion is variably set.

[0021]

As described above, according to the present invention, in order to generate a pseudo-random code, the generation means returns a desired number of bits from the end of the already generated pseudo-random code as a bit string to be divided by a primitive polynomial. The selection means selects and supplies the consecutive bits.

That is, as compared with the conventional example in which a regular pseudo-random code is generated and then the bit sequence of the code is rearranged, storage means and selection means required for the rearrangement become unnecessary, and these means are controlled. Since the procedure is simpler, the circuit configuration can be simplified, and a missing PN pattern can be reliably generated.

Therefore, in the electronic apparatus to which the present invention is applied, the power consumption is reduced and the cost is reduced, and the performance is improved.

[Brief description of the drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a diagram showing one embodiment of the present invention.

FIG. 3 is a diagram illustrating the operation of the present embodiment.

FIG. 4 is a diagram showing a configuration example of a conventional PN pattern generation circuit.

FIG. 5 is a diagram illustrating a generation operation of a PN pattern performed by a parallel expansion unit.

FIG. 6 is a diagram showing a manner of generating a PN pattern.

FIG. 7 is a diagram illustrating a process of generating a missing PN pattern.

[Explanation of symbols]

 Reference Signs List 11 generating means 13 selecting means 21, 41 parallel developing section 22, 44 selector 23, 46 timing control section 42, 43, 45 latch

Claims (1)

(57) [Claims] A generating unit configured to generate a pseudo-random code by iteratively dividing an externally applied bit sequence by using a primitive polynomial; and generating a pseudo-random code included in the pseudo-random code generated by the generating unit. A selection means (1) for selecting a continuous bit having a desired number of bits retroactively and providing the bit string.
3) A PN pattern generation circuit, comprising: