JP3137457B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a cut portion such as a fuse which can be cut to set or switch a part of the circuit to a predetermined state after the completion of the circuit portion, and more particularly to a cut-off state of the semiconductor integrated circuit. The present invention relates to a semiconductor integrated circuit whose operation needs to be confirmed.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit (hereinafter, referred to as an IC), when a circuit portion is completed, a part of the circuit is adjusted or switched so as to obtain a predetermined output. For example, the resistance value is adjusted so as to obtain a precise reference voltage, or a defective portion is replaced with a redundant circuit portion provided in advance. To perform such adjustment or switching, a fuse is usually used. A fuse is provided in a part of the circuit, and the circuit is switched depending on whether the fuse is cut or not. FIG. 8 shows an example of a conventional circuit for obtaining a precise voltage by cutting a fuse.

In order to obtain a desired potential, a method of both potential dividing resistance of the high voltage V _EE and the low potential V _SS are often used. However, there is a problem that it is difficult to obtain a precise output potential due to an error between the high potential V _EE and the low potential V _SS and a resistance error. Therefore, as shown in the circuit of FIG. 8, a large number of resistors R80 to R87 and R90 are connected in series to form a resistor R8.
Fuses F81 to F87 are provided in parallel with 1 to R87. When the fuse is not blown, the resistor R81
To R87 are similar to absent, and R80 and R9
An output potential divided by 0 is obtained. If the potential is different from the desired potential, a fuse connected in parallel with the resistor is blown so that a resistor expected to be suitable for obtaining the desired potential is connected. For example, fuse F
By cutting 3, the resistance is divided by R80 + R83 and R90. If the potential is still different from the desired potential, another fuse is blown. As described above, in the circuit of FIG. 8, a desired output potential is obtained by repeating the measurement and disconnection operations.

FIG. 9 shows a circuit for obtaining a desired output potential by connecting a MOS transistor in a diode manner. By cutting a fuse, the number of connected transistors changes and the output potential changes. Also in this case, the operation of cutting the fuse while measuring the output is repeated to obtain a desired output potential. The above is a circuit for obtaining a precise potential, such as an analog circuit or a dynamic RA.
It is used for a circuit for generating an intermediate potential of M or the like.

Further, there is a circuit for adjusting a resistance value to obtain a desired frequency output. In such a circuit, a fuse is provided, and the output frequency may be adjusted while cutting the fuse. Further, in a memory IC, a redundant circuit portion is provided in advance, assuming that a defective portion occurs in a normal circuit portion, and when a defect occurs, the defective portion is replaced with a redundant circuit so that it can be used as a good product. That is being done. In this case, a fuse is also used to instruct replacement of a defective portion.

[0006]

As described above, in an IC, a fuse is used to switch the state of a circuit. In any case, it is necessary to confirm the output and operation again after cutting the fuse. There is. For example, in a circuit for obtaining the above-mentioned reference potential, it is necessary to continue the operation of measuring the output potential after cutting a certain fuse and cutting the other fuse again until a desired potential is obtained. It is very complicated to repeat such different operations such as potential measurement and fuse cutting. Further, since a fuse once blown cannot be restored, there is a possibility that an improper fuse is blown and the IC becomes unusable.

[0007] Even in a memory IC having a redundant circuit, it is necessary to confirm the operation after cutting the fuse and replacing it with the redundant circuit. The redundant circuit of the memory IC is used to check whether there is a defective portion in the redundant circuit portion after replacement, and to check in advance that there is no defective portion in a dedicated circuit, and if there is a defective portion, avoid the portion and avoid other portions. It may be replaced with a redundant circuit.

In order to confirm the operation after replacement, if the replaced redundant circuit portion does not operate normally, it is necessary to cut the fuse to replace it with another redundant circuit portion again, and further confirm the operation. is there. in this case,
In order to replace the redundant circuit with another redundant circuit, it is necessary to prevent the part once replaced from operating, which requires a considerably complicated circuit.

Even when a redundant circuit is to be inspected in advance,
Since the control circuit for replacement is not tested, it is necessary to perform a test after disconnection, and if that part does not operate normally, it is necessary to replace it with another part as described above. As described above, in a conventional IC circuit using a fuse, the result obtained by cutting the fuse is not known until the fuse is cut, and the complicated work as described above is required.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has the advantage that a result obtained by cutting a fuse can be known in advance so that a complicated operation of repeating cutting and measurement can be eliminated. An object of the present invention is to prevent occurrence of defective products due to necessary cutting.

[0011]

FIG. 1 is a diagram showing the principle configuration of the present invention. The semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit including a cutting unit 2 that enables setting or switching of a circuit portion to a predetermined state by cutting. And a switching unit 3 which is turned off when a signal is applied from the outside and becomes conductive when no signal is applied from the outside.

A semiconductor integrated circuit according to another aspect has an external input terminal 5 that is not connected to the outside when completed, and a signal applied to the switching means 3 is input to the external input terminal 5.

[0013]

Since the switching means 3 is provided in series with the cutting means 2, cutting the switching means 3 can realize the same state as cutting the cutting means 2. The switching means 3 is turned off by applying a signal from the outside, and becomes conductive when no signal is applied from the outside. Therefore, the state of the cutting means 2 can be arbitrarily changed depending on whether or not a signal is applied from the outside. Can be set. Therefore, by realizing a state equivalent to cutting the cutting means 2 in advance and measuring the output, it is possible to know the state of the cutting means 2 necessary to obtain a desired output,
A desired output can be obtained by one cutting operation, and erroneous cutting is not performed. The switching means 3 is conductive when no signal is applied from the outside. Therefore, by applying no signal except when the cutting means 2 is tested, a state equivalent to the case where only the cutting means 3 exists can be realized.

Although the semiconductor integrated circuit is provided with terminals for inputting and outputting signals to and from the outside when completed, the second aspect of the present invention provides a terminal for externally applying a signal to the switching means 3. Since the external input terminal 5 is not connected to the outside at the time of completion, the number of external input / output terminals at the time of completion of the semiconductor integrated circuit does not increase.

[0015]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 2 is a diagram showing the configuration of the first embodiment of the present invention. In this embodiment, the switching means is realized by an n-channel MOS transistor. In this embodiment, as shown in the figure, an n-channel MOS transistor nTr is connected in series to a fuse, and its control electrode (gate electrode) is connected to a test node and at the same time has a high potential via a resistor R. Unit _Vcc .
The test node is a test electrode used when applying a signal to generate a state equivalent to the state where the fuse F is blown, and does not become a terminal to the outside when completed. Therefore, even if this test node is provided, the number of terminals does not increase.

The gate electrode is connected to the high potential side V via a resistor R.
_Since it is connected to _CC , if no signal is applied to the test node, a high potential is applied to the gate electrode and the transistor nTr conducts. When a low potential is applied to the test node, a low potential is applied to the gate electrode of the transistor nTr, so that the transistor nTr becomes non-conductive,
The state where the node 1 and the node 2 are cut off, that is, the same state as the state where the fuse F is cut off is realized.

Therefore, two states equal to the state where the fuse is cut and the state where the fuse is not cut can be realized depending on whether or not the low potential signal is applied to the test node.
In the final product, since no signal is applied to the test node, transistor nTr is rendered conductive, and the state between nodes 1 and 2 is determined only by the state of fuse F.

FIG. 3 shows a second embodiment in which a p-channel transistor is used as the switching means. The first embodiment in FIG. 2 is a p-channel transistor pTr, and its gate electrode is connected via a resistor R. And low potential side V _SS
The difference is that they are connected to Since the gate electrode is connected to the low potential side V _SS via the resistor R, a low potential is applied to the gate electrode unless a high potential signal is applied to the test node, and the transistor pTr is turned on. That is, a state equivalent to a state in which only the fuse F is connected between the node 1 and the node 2 is realized. When a high potential signal is applied to the test node, a high potential is applied to the gate electrode of the transistor pTr.
Is turned off, and a state where node 1 and node 2 are cut off, that is, the same state as a state where fuse F is cut off is realized.

FIG. 4 is a diagram showing the configuration of the third embodiment.
The third embodiment is an example in which the present invention is applied to a reference voltage generating circuit for obtaining a highly accurate output voltage. In the figure,
Tr1 and Tr2 are transistors for turning on this circuit by turning on Tr3 when a high potential signal is applied to the operation control terminal. Tr4 to Tr10 are T
An n-channel transistor that is diode-connected between r3 and ground. Resistors R1 to R4 are connected in series between the source and the drain of the transistor Tr4 in parallel with the transistor Tr4.
1 to R4 divide the potential of the source and drain of the transistor Tr4 by resistance. Each connection point of the resistor is connected to the fuse F1,
F2, F3, F4, and F5 are connected to output terminals via p-channel transistors Tr11, Tr12, Tr13, Tr14, and Tr15. Fuse F1, F
Depending on which of the fuses F2, F3, F4 and F5 is blown, the resistance substantially connected between the source and the drain of the transistor Tr4 changes, and the output potential changes. Transistors Tr11, Tr12, Tr13, Tr
14 and each gate electrode of Tr15 are resistors R5, R6, R
7, R8, and R9 are connected to the ground. The portion composed of the fuse and the transistor is the same as the circuit shown in FIG. 3, with node 1 corresponding to each connection point of the resistor and node 2 corresponding to the output terminal. Each transistor is turned off by applying a high potential signal to the terminals A, B, C, D, and E, and is turned on when no signal is applied. That is, the fuses F1, F2, and F depend on whether a high-potential signal is applied to the terminals A, B, C, D, and E.
3, a state in which F4 is cut and a state in which F4 is not cut can be arbitrarily realized.

The fuses F6, F7, F8, the p-channel transistors Tr16, Tr17, Tr18 and the resistor R
Each circuit composed of 10, R11, and R12 is the same as the circuit shown in FIG. 3, and is provided between each source of the diode-connected n-channel transistors Tr8, Tr9, and Tr10 and the ground. In the state shown,
Although the drain of the transistor Tr7 is connected to the ground, the transistors F8, Tr9,.
Since Tr10 is diode-connected and the number of transistors connected in diode changes, the output potential changes. Transistors Tr16, Tr17, Tr
Numeral 18 turns off when a high potential signal is applied to each of the terminals F, G, and H, and turns on when no signal is applied.

In order to obtain a desired output potential, it is appropriate to first measure the output potential without applying a high potential signal to the terminals A to H, and to cut the fuse to obtain the desired output potential. The signal applied to the corresponding terminal is changed so as to make the transistor corresponding to the non-conductive state.
This operation is continued until a desired output potential is obtained. Then, when a desired output potential is obtained, a fuse corresponding to the transistor which has been turned off is cut. Since the output potential in a state where these fuses are cut has already been confirmed, a desired output potential can be obtained by one fuse cutting operation.

FIG. 5 is a diagram showing the configuration of the fourth embodiment.
This embodiment is an example in which the present invention is applied to a circuit for generating a refresh address signal in a dynamic RAM. In the dynamic RAM, a potential other than the applied potential may be generated. Such a potential is obtained by charging and discharging a signal of an internal oscillation circuit to a capacitor while changing a duty ratio. The circuit of this embodiment divides the output signal of the internal oscillation circuit to generate a refresh address signal. However, the output frequency of the internal oscillation circuit has a large error. There is a problem that an address signal cannot be obtained. Therefore, a refresh address signal of a predetermined frequency is obtained by setting the initial value of the 1/2 frequency dividing circuit connected in multiple stages by cutting the fuse.

In FIG. 5, reference numeral 51 denotes an internal oscillation circuit, and reference numeral 52 denotes a counter in which a 1/2 frequency dividing circuit 53 is connected in multiple stages. 54 is a refresh address counter. Reference numeral 55 denotes a counter value setting circuit for setting an initial value of each 1/2 frequency dividing circuit of the counter 52. FIG. 6 is a diagram showing details of a set of each 1/2 frequency dividing circuit and the counter value setting circuit. In FIG. 6, reference numeral 53 denotes a 1/2 frequency dividing circuit;
Is a counter value setting circuit for setting the initial value of the 1/2 frequency dividing circuit 53. The 分 frequency divider circuit 53 is a well-known circuit, and detailed description thereof is omitted here. However, by setting 1 and 0 or 0 and 1 to the R and S terminals in the figure, The initial value of the counter 52 can be set. After the initial values are set, both the R and S terminals are set to 1. With this initial value, the frequency of the signal output to the refresh address counter 54 can be changed. For example, 1/2
Assuming that the frequency dividing circuit 53 is a counter for counting 256 pulses connected in eight stages, when the initial values of all the 1/2 frequency dividing circuits are set to zero, the refresh address counter 54 is counted when 256 pulses are counted. Is output, but only the initial value of the final stage 1/2 frequency divider is 1
, A signal is output to the refresh address counter 54 when 128 pulses are counted.

The counter value setting circuit 56, as shown, the fuse 61, transistor 62, and the same fuse circuit and FIG. 2 is formed by resistors 63, the high-potential side V _CC
Is connected to the resistor 64 connected to. The potential at one end of the resistor 64 changes depending on whether the fuse 61 is cut or not. That is, if the fuse 61 is not cut, the potential becomes low, and if the fuse 61 is cut, the potential becomes high. The signal of that part is input to the OR gate 67 to which the counter set signal is input and becomes a set signal applied to the S terminal, and is simultaneously input to the inverter 65, inverted and then input to the OR gate 66. The reset signal is applied to the R terminal. Therefore, fuse 6
When 1 is not blown, the counter is set to 0. When fuse 61 is blown, the counter is set to 1.
Is set to The counter set signal is 0 only when the counter is set, and is 1 otherwise.

Until now, the fuse was blown while measuring the frequency of the output signal, so that the operation was complicated. However, in this embodiment, the fuse 61 was blown by applying a low potential to the test terminal. Since the state can be realized, it is possible to select a signal to be applied to the test terminal in advance and know the cutting condition of the fuse for obtaining the refresh address signal of a desired frequency, so that the cutting operation of the fuse only needs to be performed once. Thereby, the complicated work as described above is reduced.

FIG. 7 is a diagram showing the configuration of the fifth embodiment of the present invention. In this embodiment, the present invention is applied to a circuit for replacing a static RAM with a redundant circuit. In FIG. 7, reference numeral 71 denotes a normal memory cell array (normal cell array), and reference numeral 72 denotes a redundant memory cell array. 7
3 is a row decoder, and 74 is a column decoder. 75
Is a switch line for a bit line pair in a normal cell array, and 76 is a switch line for a bit line pair in a redundant memory cell array. 77 is a sense amplifier.

In order to replace the defective portion of the normal cell array 71 with the redundant memory cell 72, the position of the defective portion is stored, and when the defective portion is accessed, the redundant memory cell is accessed instead. A fuse ROM is used to store the location of the defective portion. Reference numeral 79 in FIG. Such a fuse R
The OM exists for the number of bits required to indicate the position of the position of the defective portion. 78 is an address signal but fuse ROM
Is a match detection circuit for detecting whether or not the position matches the position stored in the bit line pair of the redundant memory cell array, and stops the output of the column selection signal from the column decoder 74. Reference numeral 80 denotes a fuse ROM indicating that replacement with a redundant memory cell has been performed. If the capacity of the redundant memory cell 72 is equivalent to a plurality of bit line pairs,
The fuse ROM 79, the coincidence detection circuit 78, and the replacement instruction fuse ROM indicating the position of the defective portion are required for the bit line pairs. Each fuse ROM has the configuration shown in FIG. 2, and by applying a signal to the test terminal, it is possible to replace an arbitrary position of the normal cell array 71 with a redundant memory cell without cutting the fuse. . Therefore, it is possible to check in advance whether or not the circuit operates normally when the fuse is blown.

In the memory IC having the redundant circuit, there has been described that the memory IC 72 is inspected for a defective portion in the redundant memory cell 72 before the replacement and the memory IC is not inspected. Since the operation of the redundant memory cell 72 can be checked before the fuse is blown as described above, it can be naturally checked whether or not a defective portion exists in the redundant memory cell 72. In a conventional memory IC that inspects a redundant memory cell 72 for a defective portion before replacement,
Although an additional circuit such as a multiplexer has been used to enable such a test, such an additional circuit is complicated and the circuit of the present embodiment shown in FIG. 7 is simpler. There are advantages.

The embodiment of the present invention has been described above.
The present invention is applicable to all semiconductor integrated circuits having a means for setting a state by cutting a fuse or the like, and is not limited to the above embodiments.

[0030]

As described above, according to the present invention,
In a semiconductor integrated circuit that sets a state by cutting a fuse or the like, a state similar to that of cutting a fuse can be easily realized without cutting the fuse, and the fuse should be cut to obtain a desired state. Since the state is known in advance, there is an effect that the cutting operation is easy and reliable.

[Brief description of the drawings]

FIG. 1 is a principle configuration diagram showing a configuration of a semiconductor integrated circuit of the present invention.

FIG. 2 is a diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a second embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a third embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a fourth embodiment of the present invention.

FIG. 6 is a diagram showing some details of a fourth embodiment;

FIG. 7 is a diagram showing a configuration of a fifth embodiment of the present invention.

FIG. 8 is a diagram showing an example of a conventional circuit for obtaining a predetermined potential by cutting a fuse.

FIG. 9 is a diagram showing another example of a conventional circuit for obtaining a predetermined potential by cutting a fuse.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 semiconductor integrated circuit body 2 disconnecting means 3 switching means 4 non-operation setting means 5 external input means

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/10 491

Claims (3)

(57) [Claims] Cutting means (2) for setting or switching a circuit portion to a predetermined state by cutting
A semiconductor integrated circuit comprising: a serial connection to the disconnecting means (2), a disconnection state by applying a signal from the outside in a state where the disconnection means is not disconnected, and a conduction state when no signal is externally applied. Switching means (3), and an external input terminal (5) for inputting a signal applied to the switching means (3), which is not connected to the outside when completed. Semiconductor integrated circuit. 2. The switching means (3) is an N-channel MOS transistor, and a gate electrode of the transistor is connected to the external input terminal (5) and to a high potential portion via a resistor. The semiconductor integrated circuit according to claim 1, wherein: 3. The switching means (3) is a P-channel MOS transistor, and a gate electrode of the transistor is connected to the external input terminal (5) and to a low potential portion via a resistor. The semiconductor integrated circuit according to claim 1, wherein: