KR100266648B1 - Redundancy circuit in semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: A redundancy circuit of semiconductor integrated circuit is provided to detect accurate information for a defect cell and prevent each cell in a memory cell sub-array from being defected, by oppositely designing data written on the each cell of the memory cell sub-array and data written on each cell of a redundancy cell block at a position corresponding to the cells. CONSTITUTION: A row decoder and a column decoder receive an address signal Ai. A cell subarray(3) includes a plurality of cells each being selected by a word line Wli decoded by the row decoder and a bit line BITi and a bitbar line BITiB decoded by the column decoder. A sense AMP block(4) amplifies data outputted from the cell subarray(3) and outputs the same through two input/output buses(IO, IOB) externally. A row redundancy cell block(5) and a column redundancy cell block(6) are connected to the bit line BITi and the bitbar line BITiB, replaces a predetermined number of cells containing the defect cell with the blocks when any cell of the cell subarray(3) has a defect. The bit line BITi of the cell subarray(3) is connected with the input/output buses(IO) via the sense AMP block(4). The bitbar line BITiB of the cell subarray(3) is connected with the input/output buses(IOB) via the sense AMP part(4). The bit line RBIT of the column redundancy cell block(6) is connected with the input/output buses(IOB) via the sense AMP block(4). The bitbar line RBITB of the column redundancy cell block(6) is connected with the input/output buses(IO) via the sense AMP block(4).

Description

Redundancy Circuit of Semiconductor Integrated Circuits

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a redundancy circuit of a semiconductor integrated circuit, and more particularly, to a redundancy circuit of a semiconductor integrated circuit capable of accurately determining a position of a cell that is recovered after redundancy is performed in a DRAM.

In a semiconductor device such as a DRAM, a spare cell is added to prevent the entire wafer from being used due to a defective cell generated in the finished wafer after the wafer process is completed, and the defective cell is replaced by the spare cell by a wafer test. . Here, the spare cell is called a redundancy cell.

1 is a configuration diagram of a conventional general semiconductor integrated circuit, as shown in FIG. 1, a row decoder 1 and a column decoder 2 for receiving an address signal Ai, respectively; A cell sub array 3 selected by a word line WLi decoded by the row decoder 1 and two bit lines BITi and BITiB decoded by the column decoder 2 to store or output arbitrary data. )Wow; A sense amplifier block 4 for amplifying the data output from the cell sub array 3 and outputting the amplified data to the outside via input / output buses IO and IOB; When any cell of the cell subarray 3 is defective, a low redundancy cell block 5 for replacing a predetermined number of cells including the defective cell by any number of word lines WL or columns. ) And column redundancy cell block 6; The sense amplifier block 4 includes an input / output gate for controlling input and output of data.

FIG. 2 is a configuration diagram of a redundancy circuit of a conventional semiconductor integrated circuit, and shows a detailed configuration of the cell sub array 3, the sense amplifier block 4, and the column redundancy cell block 6 in the configuration of FIG. 1.

As shown, the cell subarray 3 and the column redundancy cell block 6 have a bit line BITi and a bit bar line BITiB of the sense amplifiers 41 and 42 of the sense amplifier block 4. And a folded bit line structure connected to (43, 4R), and the sense amplifier block (4) is a bit line (BITi) and a bit bar line via the sense amplifiers (41, 42, 43, 4R) (BITiB) and a plurality of input and output gates (401, 402, 403, ..., 40R) connected to each of the input and output buses (IO, IOB).

Each of the input / output gates 401, 402, 403,..., 40R is selected by a selection signal YSELi RYSEL output from the column decoder 2 to connect the bit line BITi to the input / output bus IO. Second switching transistors T21 selected by the switching transistors T11, T12 and T13 (T1R) and the selection signal YSELi RYSEL to connect the bit bar line BITiB and the input / output bus IOB. , T22, T23) (T2R).

One end of two cells M3 and M4 of the cell sub-array 3 is connected to a bit line BIT0, and the bit line BIT0 is connected to the input / output gate 401 through the sense amplifier 41. One end of the first switching transistor T11 is connected, and the other end of the first switching transistor T11 is connected to the input / output bus IO. In addition, one end of the three cells M1, M2, and M5 of the cell sub array 3 is connected to the bit bar line BIT0B, and the bit bar line BIT0B is connected through the sense amplifier 41. It is connected to one end of the second switching transistor T21 of the input / output gate 401, and the other end of the second switching transistor T21 is connected to the input / output bus IOB.

One end of two cells RM3 and RM4 of the column redundancy cell block 6 is connected to a bit line RBIT, and the bit line RBIT is connected to the input / output gate 40R through the sense amplifier 4R. It is connected to one end of the first switching transistor T1R, and the other end of the first switching transistor T1R is connected to the input / output bus IO. In addition, one end of three cells RM1, RM2, and RM5 of the column redundancy cell block 6 is connected to a bit bar line RBITB, and the bit bar line RBITB is connected to the sense amplifier 4R. It is connected to one end of the second switching transistor T2R of the input / output gate 40R, and the other end of the second switching transistor T2R is connected to the input / output bus IOB.

If a wafer test is performed in the structure as described above and a failure occurs in a part of the cell sub-array 3, the fuse (not shown) connected to the cell determined to be defective is cut off, and the cell no longer operates. The cell block containing the defect is replaced with the column redundancy cell block 6, and the column decoder 2 replaces the bit line BITi and the bit bar line BITiB connected with the defective cell with the bit line RBIT. ) And the bit bar line RBITB, and the selection signal YSELi is replaced with the selection signal RYSEL.

For example, if any cell among the cells M1 to M5 connected to the first bit lines BIT0 and BIT0B is determined to be defective, a fuse (not shown) connected to each of the cells is blown. Instead of outputting the first selection signal YSEL0, the column decoder 2 outputs the selection signal RYSEL connected to the column redundancy cell block 6. The cells M1 to M5 are then replaced with the cells RM1 to RM5 of the redundancy cell block 6. In this way, the data to be stored in the cells M1-M5 of the cell subarray 3 is stored in the cells RM1-RM5 of the column redundancy cell block 6.

In other words, assuming that the cells M1 to M5 operate normally, the data stored in the cells M3 and M4 are loaded on the bit line BIT0 and transferred to the sense amplifier 41, and the first selection is performed. The switching transistor T11 of the input / output gate 401 is turned on by the signal YSEL0, so that the data are output to the outside via the input / output bus IO. In the same manner, the data stored in the cells M1, M2, and M5 are output to the outside via the bit bar line BITOB, the switching transistor T21, and the input / output bus IOB.

On the contrary, assuming that the cells M1 to M5 have recovered to the cells RM1 to RM5 of the column redundancy cell block 6, the data stored in the cells RM3 and RM4 are loaded on the bit line RBIT. The data is transmitted to the sense amplifier 4R, and the first switching transistor T1R of the input / output gate 40R is turned on by the selection signal RYSEL, so that the data are output to the outside via the input / output bus IO. In the same manner, the data stored in the cells RM1, RM2, and RM5 are output to the outside via the bit bar line RBITB, the second switching transistor T2R, and the input / output bus IOB.

Accordingly, data to be written and read in the cells M1 to M5 is written and read in the cells MR1 to MR5, and the selection signal YSEL0 of the column decoder 6 is replaced by the selection signal RYSEL. .

When the recovery is completed as described above, the cells RM1 to RM5 of the column redundancy cell block 6 replace the respective cells M1 to M5 of the cell subarray 3 that are defective cells, thereby providing a circuit. The original operation of is performed normally.

On the other hand, the above-described recovery process is achieved during the wafer test, and the manufacturer cannot know whether the redundancy cell is used because the defective cell is replaced.

3 is a block diagram of a device capable of confirming whether or not a redundancy cell is used in the circuit of FIG. 2. As shown in FIG. 2, a rasva signal (/ RAS), a cascade signal (/ CAS), and a word enable bar signal ( / WE) and a test mode setting unit 31 for outputting a test signal TMODE in accordance with the logic state of the address signals Ai-Ak; An NMOS transistor M1 that receives the test signal TMODE as a gate; A current limiting resistor R connected between the pad 32 and one terminal 33 of the NMOS transistor M1; And a fuse F connected between the other terminal 34 of the NMOS transistor M1 and the ground terminal 35, and the current limiting resistor R between the pad 32 and the ground terminal 35. The NMOS transistor M1 and the fuse F are connected in series.

The operation of FIG. 3 will be described with reference to FIG. 4, which shows a waveform diagram of each signal.

The ras bar signal / RAS, the cas bar signal / CAS, the word enable bar signal / WE, and the address signal Ai-Ak are input to the test MOS setting unit 31, and the casbar signal (/ After the predetermined time passes after the CAS) and the word enable bar signal / WE transition to the low level, the ras bar signal / RAS transitions to the low level. The test signal TMODE output from the test mode setting unit 31 is transitioned to the active high state by the low level Rasva signal / RAS, and the NMOS transistor M1 is applied by the test signal TMODE. ) Is turned on.

Meanwhile, since the NMOS transistor M1, the current limiting resistor R, and the fuse F are connected in series between the pad 32 and the ground terminal 35, the fuse F is disconnected. There is no current flowing through the pad 32 because the path of the current is interrupted. On the contrary, if the fuse F is not cut, a current having a predetermined value flows through the pad 32.

Therefore, when the current flowing through the pad 32 is measured, it is possible to determine whether the fuse F is disconnected, and thus it is possible to determine whether the redundancy cell is used based on the measured current value.

Such a redundancy circuit used in the conventional semiconductor integrated circuit can prevent the entire wafer from being used by the defective cell in the completed wafer by determining whether the cell is recovered or not, but it is shown in FIG. Since a separate device is required and the exact information on the defective cell cannot be known, the same defective cell can be continuously generated in the finished wafer because the fundamental countermeasure that the defective cell can not be taken. That is, there is a problem that it is difficult to prevent the generation of defective cells by the same process.

To solve this problem, an object of the present invention is to design such that data written to each cell of a memory cell sub-array and data values written to each cell of the redundancy cell block of the corresponding position of the cell are opposite to each other, It is an object of the present invention to identify accurate information on a cell in which a failure occurs so that each cell of the cell sub array does not become a defective cell.

1 is a configuration diagram of a conventional general semiconductor integrated circuit

2 is a configuration diagram of a redundancy circuit of a conventional semiconductor integrated circuit

3 is a block diagram of an apparatus capable of confirming whether or not a redundancy cell is used in the circuit of FIG.

4 is a waveform diagram of each signal of FIG. 3.

5 is a configuration diagram of an embodiment of a redundancy circuit of the semiconductor integrated circuit of the present invention.

FIG. 6 shows a pattern of data written to each cell in the structure of FIG.

7 illustrates a bitmap in which defective cells of a cell subarray are displayed according to the present invention.

**** Explanation of symbols for the main parts of the drawing ****

1: row decoder 2: column decoder

3: cell sub-array 4: sense amplifier block

5: low redundancy cell block 6: column redundancy cell block

41,42,43,4R: Sense amplifier 401,402,403,40R: I / O gate

T11, T12, T13, T1R: first switching transistor

T21, T22, T23, T2R: second switching transistor

The present invention for achieving the above object is connected to the bit line (RBIT) and the bit bar line (RBITB), when any cell of the cell sub array (3) is a predetermined number of cells including the defective cell A row redundancy cell block 5 and a column redundancy cell block 6 that are replaced by any number of word lines WL or columns, and correspond to each cell of the cell subarray 3. Each cell of the column redundancy cell block 6 is configured to be connected oppositely to the connection relationship of each cell of the cell subarray 3.

FIG. 5 is a configuration diagram of one embodiment of a redundancy circuit of a semiconductor integrated circuit according to the present invention. As shown therein, a bit line RBIT, a bit bar line RBITB, and a sense amplifier connected to the column redundancy cell block 6 are illustrated in FIG. The connection relationship between the input and output gates 40R of the block 4 is different from that of the conventional circuit of FIG. 2, and the rest of the configuration is the same as that of FIG.

That is, one end of two cells RM3 and RM4 of the column redundancy cell block 6 is connected to the bit line RBIT, and the bit line RBIT is the sense amplifier 4R of the sense amplifier block 4. The first switching transistor T1R of the input / output gate 40R is connected to one end thereof, and the other end of the first switching transistor T1R is connected to the input / output bus IOB. In addition, one end of three cells RM1, RM2, and RM5 of the column redundancy cell block 6 is connected to a bit bar line RBITB, and the bit bar line RBITB is connected to the sense amplifier 4R. The other end of the second switching transistor T2R of the input / output gate 40R is connected to the one end of the second switching transistor T2R and the input / output bus IO.

The data stored in the two cells RM3 and RM4 is output via the bit line RBIT and the input / output bus IO according to FIG. 2, but according to FIG. 5, the bit line RBIT and the input / output bus IOB are shown according to FIG. 5. Output via In addition, data stored in the three cells RM1, RM2, and RM5 is output via the bit bar line RBITB and the input / output bus IOB according to FIG. 2, but according to FIG. 5, the bit bar line RBITB. It is output via the input / output bus IO.

The operation of one embodiment of the present invention configured as described above will be described.

In the prior art, the bit line BIT0 corresponds to the bit line RBIT, the bit bar line BIT0B corresponds to the bit bar line RBITB, and the bit line RBIT is connected to the input / output bus IO. The bit bar line RBITB is connected to the I / O bus IOB, but according to the configuration of the present invention, the bit line RBIT is connected to the I / O bus IOB and the bit bar line RBITB is connected to the I / O bus IB. IO).

As described above, although the cell arrangement of the cell subarray 3 and the column redundancy cell block 6 is the same as in the related art, the connection of the two bit lines RBITB of the column redundancy cell block 6 is conventional. As opposed to this, if " 0 " is written to each of the cells M1-M5 of the cell subarray 3, " 1 " is written to each of the cells RM1-RM5 of the column redundancy cell block 6.

That is, as shown in FIG. 6, when data "0" is written to each cell of the cell subarray 3, two bit lines RBIT of the column redundancy cell block 6 are written. Since the RBITB connection relationship is opposite to the two bit line (BITi, BITiB) connection relationships of the cell subarray, "1" is written to each of the cells RM1-RM5 of the column redundancy cell block 6.

On the other hand, according to the memory characteristics, the time at which the data values "0" and "1" stored in the cell are different from each other. When the refresh operation is performed using the characteristics, the redundancy cell is used. It is possible to determine which cell of the cell sub array 3 has been recovered, which will be described below.

First, it is assumed that any cell among the cells M1-M5 of the cell sub array 3 connected to two bit lines BIT0 and BIT0B is defective. When the wafer test is performed, the cells M1-M5 containing the defective cells are replaced with the cells RM1-RM5 of the column redundancy cell block 6 and the selection signal YSEL0 of the column decoder is the selection signal RYSEL. By being replaced by, the cells RM1-RM5 may replace the operations of the cells M1-M5.

Under this assumption, the following checks are performed.

When the address Ai is input, the word line WLi is selected by the row decoder 1 and the bit lines BITi (RBIT) (BITiB) (RBITB) are selected by the column decoder 2. When the bit bar line BITiB (RBITB) becomes high by the column decoder 2, the bit line BITi (RBIT) becomes low, and when the word line WLi is made high, Based on the scramble equation, physical data is written to each cell.

The test equipment has information about the values to be written to each cell, that is, which value will be stored in which cell. For example, if the physical data value "0" is written to all cells of the cell sub array 3, the test equipment recognizes that "0" is stored in all cells.

After the write operation is completed, the charge corresponding to the data written to each memory cell, that is, the charge stored in each capacitor starts to discharge. Due to the characteristics of the memory cells, the time for which the charge corresponding to data "1" written to each cell is discharged differs from the time for which the charge corresponding to data "0" is discharged. The time at which "1" is discharged is about tens of times faster than the time at which "0" is discharged.

Using this characteristic, the data written in each cell is transferred to the test equipment at an arbitrary point T before the charge corresponding to “1” has passed and the charge corresponding to “0” has been discharged. In examination, the data value of the cell in which "0" is written is normally output as "0". However, the data value of the cell in which "1" is written changes to "0".

The data value of each cell, which is pre-stored in the test equipment at a predetermined time T, is "0", and this "0" is compared with the data value currently output from each cell.

If there are no defective cells, the data value currently output from each cell will be "0".

Substantially, the data value of the cells RM1-RM5 is changed from "1" to "0", but because the cells M1-M5 have already been replaced by the cells RM1-RM5 from above, that is, the recovery is completed. The test rig recognizes that the data values of the cells M1-M5 change from "1" to "0".

Therefore, at that time T, the data values of the cells M1-M5 already stored in the test equipment are "0", and the data values currently output from the cells M1-M5 are set to "1". Changes to "0". The test equipment compares previously stored values and currently output values with each cell, and displays the compared result in a bitmap as shown in FIG.

If the two values are different, the part is marked in black. 7 indicates the entire area of the cell subarray, and the portion indicated by the solid line is the recovered portion.

Therefore, the solid line shown in black is recovered from the bitmap, and the black line intermittently indicates that the defective cell is replaced in units of blocks.

The manufacturer can look at the bitmap and determine which cells in the cell subarray have become defective cells and have been replaced with redundancy cell blocks.

In the above, " 0 " is written to each cell of the cell subarray 3 so that " 1 " is written to each cell of the column redundancy cell block 6 so that " 0 " and " 1 " The discharge time was measured and tested, but each cell of the cell subarray 3 was written "1", and each cell of the column redundancy cell block 6 was written "0" and the "1" and "0". "You may measure the discharge time.

In an embodiment of the present invention, the defective cells of the cell sub-array are replaced with the cells of the column redundancy cell block. For example, the cells of the low redundancy cell block are not replaced. However, the operation of replacing the defective cells of the cell sub array with the cells of the low redundancy cell block may be performed in the same manner as described above.

As described above, the present invention can find out which cell has become a defective cell in the finished wafer, thereby providing fundamental data for preventing the defective cell from occurring. Therefore, it is possible to investigate the cause of the cell failure based on the data, if the cause is found, there is an effect that the defective cell may not occur in the next process.

Claims (5)

A row decoder 1 and a column decoder 2 for receiving an address signal Ai, respectively; Cell sub array 3 in which each cell is selected by the word line WLi decoded by the row decoder 1 and the bit line BITi and bit bar line BITiB decoded by the column decoder 2. )Wow; A sense amplifier block 4 for amplifying the data output from the cell sub array 3 and outputting the amplified data to the outside through two input / output buses IO and IOB; A low redundancy cell block connected to a bit line RBIT and a bit bar line RBITB to replace a predetermined number of cells including the defective cell with a block when any cell of the cell sub array 3 is defective. 5) and column redundancy cell block 6, wherein data stored in each cell of the cell subarray 3 and the redundancy cell block 5, 6 is transmitted via the sense amplifier block 4; A redundancy circuit of a semiconductor integrated circuit outputted to two input / output buses IO and IOB; The bit line BITi of the cell sub array 3 is connected to the input / output bus IO via the sense amplifier block 4, and the bit bar line BITiB of the cell sub array 3 is The bit line RBIT of the column redundancy cell block 6 is connected to the input / output bus IOB via the sense amplifier block 4, and is connected to the input / output bus IOB via the sense amplifier block 4. ), And the bit bar line RBITB of the column redundancy cell block 6 is connected to the input / output bus IO via the sense amplifier block 4. . 2. The apparatus of claim 1, wherein the sense amplifier block (4) comprises: a plurality of sense amplifiers (41, 42, 43) connected to the two bit lines (BITiB) of the cell sub array (3), respectively; A sense amplifier 4R connected to two bit lines RBITB of the column redundancy cell block 6; And a plurality of input / output gates (401, 402, 403, 40R) connecting the plurality of sense amplifiers (41, 42, 43, 4R) and the input / output buses (IO, IOB), respectively. 3. The first switching circuit of claim 2, wherein each of the input / output gates 401, 402, 403 is selected by a selection signal YSELi output from the column decoder 2 to connect the bit line BITi and the input / output bus IOB. Second switching transistors T21, T22, and T23 selected by the transistors T11, T12, and T13 and the selection signal YSELi to connect the bit bar line BITiB to the input / output bus IO. The input / output gate 40R is selected by the selection signal RYSEL output from the column decoder 2 to connect the bit line RBIT and the input / output bus IOB to the first switching transistor T1R. And a second switching transistor (T2R) selected by the selection signal (RYSEL) and connecting the bit bar line (RBITB) and the input / output bus (IO). 2. The redundancy circuit according to claim 1, wherein data is written to each cell of said cell sub-array (3), and a state in which charge corresponding to the written data value is discharged is measured. The semiconductor integrated device according to claim 4, wherein the time point at which the charge is discharged is measured before the charge corresponding to “0” is discharged and the charge corresponding to “0” is discharged. Redundancy circuit of the circuit.

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