JP3134258B2 - Power control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an application-specific integrated circuit having an application-specific circuit.
Specific Integrated Circuit
it: ASIC).

[0002]

2. Description of the Related Art Conventionally, when an application-specific circuit is composed of an operation circuit and a plurality of power supply circuits, the operation circuit is divided by a power supply circuit for supplying power, and is integrated into an IC as an application-specific integrated circuit. The application-specific integrated circuit is mounted on a printed circuit board.

[0003]

In a conventional application-specific integrated circuit, an operation circuit is divided by a power supply circuit, and the operation circuit is divided by a power supply circuit.
The use of C has a problem that the mounting area on the printed circuit board is increased. Further, there is another problem that the division into power supply circuits and the formation of ICs increase the development cost of integrated circuits for specific applications.

SUMMARY OF THE INVENTION The present invention provides a printed circuit board for an integrated circuit for a specific application by switching a plurality of power supply circuits to supply power to an integrated circuit for a specific application and eliminating the limitation of the integration of the specific application circuit by a power source classification. It is an object of the present invention to provide a power supply control circuit capable of reducing the mounting area on a semiconductor device and reducing the development cost of an application-specific integrated circuit.

[0005]

In order to achieve the above object, a power supply control circuit according to the present invention comprises a power supply switching circuit for switching a plurality of power supply voltages supplied to an operation circuit, and a control signal for controlling the operation circuit. And a reset circuit for outputting a reset signal generated for each power supply voltage as a gate signal.

[0006]

When power is supplied to the power supply switching circuit and the reset circuit of the power supply control circuit for specific use configured as described above, the power supply switching circuit switches the power supply voltage, and the reset circuit outputs a reset signal for each power supply voltage. The gate signal is generated and output as a gate signal to a gate circuit of a control signal for controlling the operation circuit, so that the gate circuit is opened.

Therefore, according to the present invention, a plurality of power supply circuits can be switched to supply power to an application-specific integrated circuit. And the development cost of an integrated circuit for a specific application can be reduced.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to the drawings. Elements common to the drawings are denoted by the same reference numerals.

[0009] First Embodiment FIG. 1 is a block diagram showing a configuration of a first embodiment. Different input voltages V1 and V2 are applied to the input side of the power switch circuit 1.
Power supply lines 2 and 3 for supplying (V1> V2) are connected, and are also connected to input sides of reset circuits 4 and 5. A power supply input line 7 and reset signal lines 8 and 9 are connected between the input side of the application specific integrated circuit 6 (hereinafter referred to as ASIC 6) and the output side of the power switch circuit 1 and reset circuits 4 and 5. .

The power switch circuit 1 comprises diodes 1a and 1b, as shown in FIG.
Power supply lines 2 and 3 for supplying different input voltages V1 and V2 are connected to the input side of the power supply line 1b.
Are connected at one end. When any one of the input voltages V1 and V2 input to the power switch circuit 1 is supplied, the input voltage is supplied to the operation circuits 10 and 11 of the ASIC 6 via the power input line 7. Is done.
When both the input voltages V1 and V2 are supplied, the voltage V1 is supplied to the ASIC 6 from V1> V2 by the action of the diodes 1a and 1b. In the ASIC 6, two operation circuits 10 and 11 having different operation voltages are integrated into an IC.
It is mounted on a ceramic substrate together with the gate circuits 12 and 13. The gate circuits 12 and 13 input / output control signals from a control unit (not shown) via control signal lines 14 and 15 using the reset signals of the reset circuits 4 and 5 as gate signals.

As shown in FIG. 4, reset circuits 4 and 5 are provided with reset ICs 16 and 17 and resistors 18 and 19, respectively.
And capacitors 20 and 21. After the input voltage V1 input to the reset circuit 4 rises from the low level and reaches a specified voltage VK (V1> VK: VK is a characteristic value of the reset IC), a predetermined time tK (reset IC, resistor, capacitor) After a lapse of time determined by the above values, the output side of the reset circuit 4 changes from low level to high level (voltage V1). When the input voltage V1 drops from the high level to reach the voltage VK, the output side of the reset circuit 4 changes from the high level to the low level. The reset circuit 5 performs the same operation as that of the reset circuit 4, and the specified voltage VK '
(V2> VK ': VK' is a characteristic value of the reset IC) and after a predetermined time tK '(time determined by the values of the reset IC, the resistor, and the capacitor) elapses, the output side of the reset circuit 5 becomes low level. To high level (voltage V2)
become. When the input voltage V2 drops from the high level to reach the voltage VK, the output side of the reset circuit 5 changes from the high level to the low level.

FIG. 2 is a waveform diagram for explaining the operation of the first embodiment, and FIGS. 2A to 2E respectively show A to E shown in FIG.
Corresponding to

Next, the operation will be described with reference to FIG. At time t1, as shown in FIG.
When power is supplied to the power switch circuit 1 and the reset circuit 4 after rising from the low level, the ASI is almost simultaneously output from the output side of the power switch circuit 1 as shown in FIG.
C6. At time t2, the input voltage V1 becomes the voltage VK
, And at time t3, the input voltage V1 reaches a high level. At time t4 when time tK elapses from time t2, (D)
As shown in (1), the output side of the reset circuit 4 outputs the voltage V1 to the gate circuit 12 as a reset signal. A control signal from a control unit (not shown) is output from the gate circuit 12 to the operation circuit 10 using a reset signal as a gate signal. The operation circuit 10 operates on the power supply voltage V1 supplied from the power supply switch circuit 1 and the control signal output from the gate circuit 12.

At time t5, the input voltage V2 rises from the low level as shown in FIG. 3B, and power supply to the power switch circuit 1 and the reset circuit 5 is started. The voltage on the output side of the power switch circuit 1 remains at the voltage V1 due to the action of the diodes 1a and 1b, as shown in FIG. At time t6, the input voltage V2 reaches the voltage VK ', and at time t7, the input voltage V2 reaches the high level. At time t8 when time tK 'has elapsed from time t6, the output side of the reset circuit 5 outputs the voltage V2 to the gate circuit 13 as a reset signal, as shown in FIG. A control signal from a control unit (not shown) is output from the gate circuit 13 to the operation circuit 11 using the reset signal as a gate.

At time t9, the input voltage V1 starts dropping from a high level as shown in FIG. At about the same time, the output voltage of the power switch circuit 1 also starts to drop. Time t
At 10, the input voltage V1 reaches the voltage VK, and the output side of the reset circuit 4 goes low as shown in FIG. When the input voltage V1 reaches the voltage V2 at time t11, the output voltage of the power switch circuit 1 also becomes the voltage V2, and thereafter the voltage V2 is maintained. A control signal from a control unit (not shown) is output from the gate circuit 13 to the operation circuit 11 using the reset signal as a gate. The operation circuit 11 operates with the power supply voltage V2 supplied from the power supply switch circuit 1 and the control signal output from the gate circuit 13.

At time t12, the input voltage V2 starts dropping from the high level as shown in FIG. At about the same time, the output voltage of the power switch circuit 1 also starts to drop. Time t
At 13, the input voltage V2 reaches the voltage VK ', and the output side of the reset circuit 5 goes low as shown in FIG. Therefore, no control signal is output from the gate circuit 13 to the operation circuit 11 thereafter, and the operation circuit 11 cannot operate.

In this embodiment, the input voltages are different, but a plurality of the same voltages may be input.

The operating circuit 11 operates at the input voltage V2. However, if the operating circuit operates at the input voltage V1, the operating circuit 1 operates at the time t8 to the time t10.
Both 0 and 11 become operable.

According to the present embodiment, a plurality of power supply circuits can be switched to supply power to an application-specific integrated circuit, so that the application-specific circuit is not limited to an IC by a power supply classification, and the application-specific circuit is not limited. ASICs can reduce the mounting area of integrated circuits on printed circuit boards
The development cost for commercialization can be kept low, and the unit price of the ASIC can be reduced.

Second Embodiment FIG. 5 is a block diagram showing the configuration of the second embodiment. The second embodiment differs from the first embodiment in that a delay circuit 22 as shown in FIG. The delay circuit 22 includes an NPN transistor 23 and a PN
The collector of the transistor 23 and the base of the transistor 24 are connected via the protection resistor 26, and the P-type transistor 24 and the protection resistors 25 to 27 are connected.
, The output of the reset circuit 4 is input to the base of the transistor 23, the input voltage V2 is input to the emitter of the transistor 24, and is output from the collector of the transistor 24 to the reset circuit 5 in the next stage. The emitter of the transistor 23 is grounded by providing a protective resistor 27 between itself and the base.

When the output of the reset circuit 4 is at a low level, the transistors 23 and 24 are turned off, and the input voltage V
The output is low regardless of whether 2 is high or low. When the output of the reset circuit 4 is at the high level, the transistors 23 and 24 are turned on, and the output goes to the high level and the low level according to the high level and the low level of the input voltage V2.

FIG. 6 is a waveform chart for explaining the operation of the second embodiment, and FIGS. 6A to 6F respectively show A to F shown in FIG.
Corresponding to

Next, the operation will be described with reference to FIG. At time t1, as shown in FIG.
When power is supplied to the power switch circuit 1 and the reset circuit 4 after rising from the low level, the ASI is almost simultaneously output from the output side of the power switch circuit 1 as shown in FIG.
C6. At time t2, voltage VK is reached and at time t2
At 3, the input voltage V1 reaches a high level. At time t4 when time tK has elapsed from time t2, the output side of reset circuit 4 outputs voltage V1 to gate circuit 12 as a reset signal, as shown in FIG. A control signal from a control unit (not shown) is output from the gate circuit 12 to the operation circuit 10 using the reset signal as a gate. The operation circuit 10 includes the power supply voltage V1 supplied from the power supply switch circuit 1 and the gate circuit 12
It operates with the control signal output from.

At time t1, the input voltage V2 also rises from the low level as shown in (B) and starts supplying power to the power switch circuit 1 and the reset circuit 5, and as shown in (E), at time t5 Rises from low level at time t6
At time t7, and at time t7, the input voltage V2 reaches a high level. Time t when time tK 'has elapsed from time t6
At 8, the output of the reset circuit 5 outputs the voltage V2 to the gate circuit 13 as a reset signal as shown in FIG. A control signal from a control unit (not shown) is output from the gate circuit 13 to the operation circuit 11 using the reset signal as a gate.

According to this embodiment, even if a plurality of power supply voltages are simultaneously raised, a time difference occurs before the operation circuit becomes operable, so that malfunction can be prevented.
Since there is no need to make the power output time-lag on the power side,
Standard inexpensive power supplies can be used.

[0026]

The present invention is configured as described above and has the following effects.

By switching a plurality of power supply circuits so that power can be supplied to an application-specific integrated circuit, it is possible to eliminate the limitation of the application-specific circuits to be integrated into ICs according to the power source classification and to apply the application-specific integrated circuit to a printed circuit board. Can be reduced, the development cost of commercializing the ASIC can be reduced, and the unit price of the ASIC can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment.

FIG. 2 is a waveform chart for explaining the operation of the first embodiment.

FIG. 3 is a detailed diagram of a power switch circuit.

FIG. 4 is a detailed diagram of a reset circuit.

FIG. 5 is a block diagram showing a configuration of a second embodiment.

FIG. 6 is a waveform chart for explaining the operation of the second embodiment.

FIG. 7 is a detailed diagram of a delay circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Power switch circuit 4, 5 Reset circuit 6 ASIC 22 Delay circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03K 17/00-17/70 G06F 1/00 330-341

Claims (2)

(57) [Claims] 1. A power supply switching circuit for inputting a plurality of power supply voltages and switching a power supply voltage to be supplied to an operation circuit, and a power supply as a gate signal to a control signal gate circuit supplied with the power supply voltage and controlling the operation circuit And a reset circuit for outputting a reset signal generated for each voltage. 2. The reset circuit according to claim 1, further comprising :
A first reset supplied to generate the reset signal
Circuit and a second power supply voltage to supply the reset signal.
A second reset circuit for generating the second reset circuit.
The output of the first reset circuit and the second
And the output of the second reset circuit
, And a reset circuit of the second reset circuit.
Reset signal is behind the reset signal of the first reset circuit
The power supply control circuit according to claim 1, wherein the power supply control circuit rises .