JP3119407B2 - Sequential operation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sequential operation circuit for performing a sequential operation on analog data, and more particularly, to a plurality of sample-and-hold circuits connected in series to sequentially hold and sequentially transfer an analog voltage, and And an arithmetic circuit for calculating the output of the sample-and-hold circuit. Each sample-and-hold circuit includes an input-side switch, an input-side capacitance,
A first-stage amplifier, an intermediate switch, an intermediate capacitance, and a second-stage amplifier are connected in series. A first input initialize switch is connected in parallel to the input-side switch, and a second input is connected in parallel to the intermediate switch. An initialization switch is connected, an inverter is connected in series to the first input initialization switch and the second input initialization switch, and the first and second input initialization switches are connected in series.
The input and output of the stage amplifier are connected by a feedback capacitance, and the input and output are connected to be openable and closable by first and second initialize switches, respectively. The arithmetic circuit has an amplifier inside and the input and output of this amplifier is connected to a third input / output terminal. The present invention relates to a sequential operation circuit that is openably and closably connected by an initialization switch.

[0002]

2. Description of the Related Art In recent years, the limitations of digital computers due to the exponential increase in the amount of capital investment related to microfabrication technology have been discussed, and analog computers have been receiving attention. The inventor has proposed a sequential operation circuit for performing the above-described sequential operation of analog data. However, the proposed circuit has a problem of an error due to electric charge leakage or the like, and requires an initialize switch to solve this problem. However, the initialization has a contradictory function of removing charges, while the sample-and-hold circuit has to hold charges, which may cause an error.

[0003]

SUMMARY OF THE INVENTION The present invention has been made in order to solve such a conventional problem, and it is an object of the present invention to provide a sequential operation circuit for preventing an error due to charge charging and preventing an error due to initialization. The purpose is to provide.

[0004]

A plurality of sample-and-hold circuits connected in series to sequentially hold and sequentially transfer an analog voltage, and an arithmetic circuit for calculating an output of each sample-and-hold circuit, wherein each sample-and-hold circuit includes・ Hold circuit
An input-side switch, an input-side capacitance, a first-stage amplifier, an intermediate switch, an intermediate capacitance, and a second-stage amplifier connected in series; a first-input initialization switch is connected in parallel to the input-side switch; A second input initialization switch is connected to the switch in parallel, an inverter is connected in series to the first input initialization switch and the second input initialization switch, and the first and second stage amplifiers are input by feedback capacitance. The output is connected, and the input and output are connected to be openable and closable by first and second initialize switches, respectively. The arithmetic circuit has an amplifier therein, and the input and output of the amplifier are connected to be openable and closable by a third initialize switch. In the sequential operation circuit, , The third initialization switch is closed after the first initialization switch is opened, the first initialization switch, and is closed after the second, third initialization switch is opened.

[0005]

Next, a sequential operation circuit according to the present invention will be described with reference to the drawings. In FIG. 1, according to the present invention, a plurality of sample-and-hold circuits H1 to H10 connected in series via a transfer circuit, and sample-and-hold circuits H1 to H10 through circuits branched from the transfer circuit between each sample and hold.
And a plurality of multipliers M1 to M10 connected to
And an arithmetic circuit having a multi-input adder ADD connected to .about.M10.

FIG. 2 shows sample and hold circuits H1 to H10.
An example of the circuit shown in FIG. Each sample and hold circuit includes an input-side switch SW2, an input-side capacitance C11, a first
A stage amplifier AMP1, an intermediate switch SW5, an intermediate capacitance C21, and a second stage amplifier AMP2 are connected in series. A first input initialization switch SW1 is connected in parallel to the input side switch SW2, and a second input initialization switch SW4 is connected in parallel to the intermediate switch SW5.

Further, the first input initialize switch SW1 and the second input initialize switch SW
4 is connected to an inverter INV in series. The input and output of the first and second stage amplifiers AMP1 and AMP2 are connected by feedback capacitances C12 and C22, and the first and second initialization switches SW
3, the input and output are connected to be openable and closable by SW6.

FIG. 5 shows a first example of each sample and hold circuit.
Input initialization switch SW1, input side switch S
W2, first initialization switch SW of first stage amplifier
3, an open / close timing chart of the intermediate switch SW5, the second input initialize switch SW4, and the second initialize switch SW6 of the second stage amplifier.

When the sample and hold circuit H1 is applied, first, the first input initialize switch SW
1 and the first initialization switch SW3 of the first-stage amplifier AMP1 are simultaneously closed. Three-stage inverter INV
Are formed on the same wafer, the potential A and the potential B of the reference voltage become equal, the voltage difference becomes almost 0, and the first
Initialization of P1 in the stage amplifier AMP1 is performed, and charges causing an error are erased.

After a lapse of a predetermined time, the first-stage amplifier AMP
The first initializing switch SW3 is opened, and after a lapse of a predetermined time, the first input initializing switch S3 is opened.
W1 is similarly opened. Then, at the same time as the first input initialize switch SW1 is opened, the input switch SW2 is closed, and the analog voltage X1 becomes the first voltage.
It is input to the stage amplifier AMP1. The reference voltage provided in this manner has an advantage that the stability is high due to INV.

As described above, since P1 in the first-stage amplifier AMP1 is initialized immediately before the analog voltage X1 is input, the voltage analog voltage X1 without error is input to the first-stage amplifier AMP1. After a lapse of a predetermined time, the input side switch SW2 is opened, and after a lapse of the predetermined time, the second input initialization switch SW4 and the second initialization switch SW6 of the second stage amplifier AMP2 are simultaneously closed.

The second input initializing switch SW4 and the second initializing switch S2 of the second-stage amplifier AMP2
When W6 is closed at the same time, since the three-stage inverter INV is formed on the same wafer, the potential A and the potential C of the reference voltage become equal to each other, and the voltage difference becomes almost zero. Initialization is performed, and charges causing errors are erased.

After a lapse of a predetermined time, the second-stage amplifier AMP
The second initialization switch SW6 of the second input is opened, and after a lapse of a certain time, the second initialization switch SW6 is opened.
W4 is similarly opened. Then, at the same time that the second input initialize switch SW4 is opened, the intermediate switch SW5 is closed, and the analog voltage X1 output from the first-stage amplifier AMP1 is input to the second-stage amplifier. As described above, since P2 in the second-stage amplifier is initialized immediately before the analog voltage X1 is input, the analog voltage X1 without error is input to the second-stage amplifier AMP2.

The opening and closing operations of each switch are sequentially performed according to the same timing chart shown in FIG. 5, and in the next cycle, analog data X2 is input, and thereafter, X3.
Are sequentially input to the sample and hold circuit H1.

The above-described second-stage amplifier AMP2 is a sample amplifier.
The analog voltage X1 is output to the subsequent sample-and-hold circuit H2 as the output of the hold circuit H1, and then the analog voltage X1 is sequentially transferred to the sample-and-hold circuit H10. Similarly, the subsequent analog voltages X2... Xn are sequentially transferred to the respective sample and hold circuits H2 to H10.

Each of the sample and hold circuits H1 to H9
Is the analog voltage X1
.. While transferring Xn while corresponding multipliers M1
.. Xn are output to .about.M9 via branch circuits. The sample-and-hold circuit H10 has no subsequent sample-and-hold circuit, and sequentially outputs analog voltages X1,..., Xn only to the multiplier M10.

FIG. 3 shows an example of a circuit diagram of the multipliers M1 to M10. The multipliers are multiplexers MUX 31 , MUX 32 , MU
X33 and amplifiers 1 and 2, and a third initialization switch SW7 is connected to these amplifiers 1 and 2. The opening and closing operations of the amplifiers 1 and 2 are performed by the third initialization switch SW7. Multiplexer MUX 31 ,
The MUX 32, MUX33 is input analog data X1 and the reference voltage, which are controlled by the control signal CTL.

The third initialization switch SW7 of the amplifiers 1 and 2 and the multiplexers MUX 31 , MUX 32 , MUX
When the 33 IN0 of the closed formed at the same time, three-stage inverter IN
Since V is formed on the same wafer, the potential A and the potential D of the reference voltage become equal to each other, and the voltage difference becomes almost 0, P3 in the amplifier 1 and P4 in the amplifier 2 are initialized, and the charge causing an error is generated. Is erased.

After a lapse of a predetermined time, the third initialization switches SW7 of the amplifiers 1 and 2 are opened. After a lapse of a predetermined time, the multiplexers MUX 31 , MUX 32 , MUX
At the same time that IN0 of 33 is opened, IN1 of these multiplexers is closed, and first, the multiplexer MUX 31
And the MUX 32 receives the analog voltage X1. Multiplexer MUX 31 and MUX 32 outputs the analog voltage X1 to the amplifier 1.

As described above, since P3 in the amplifier 1 is initialized immediately before the analog voltage X1 is input, the analog voltage X1 is input to the amplifier 1 without error. The amplifier 1 outputs the input analog voltage X1 to the amplifier 2 via the multiplexer MUX33.
As described above, since the initialization of P4 in the amplifier 2 is performed immediately before the analog voltage X1 is input, the analog voltage X1 is input to the amplifier 2 without error. Each of the multipliers M1 to M10 is a sample and hold circuit H1.
.., Xn sequentially inputted from the amplifiers 2 to H10, and multiplied by the multipliers.
Output to DD.

FIG. 4 shows an example of a circuit diagram of the adder ADD.
The adder ADD includes a plurality of multiplexers MUX1 to MUX1.
0, consisting of MUX11 to MUX20 and amplifiers 3 and 4,
A multiplexer MUX30 is arranged between the amplifiers 3 and 4. A third initialization switch SW8 is connected to the amplifiers 3 and 4, and the opening and closing operations of the amplifiers 3 and 4 are performed by the third initialization switch SW8. Multiplexers MUX1 to MUX10, MU
Analog data X1 to X1 are stored in X11 to MUX20 and MUX30.
0 and a reference voltage are input, and these are control signals C
It is controlled by TL.

The third initialization switches SW8 of the amplifiers 3 and 4 and the multiplexers MUX1 to MUX10 and MUX1
If 1~MUX20 and IN0 of MUX30 is made closed at the same time,
Since the three-stage inverter INV is formed on the same wafer, the potential A and the potential E of the reference voltage become equal to each other, and the voltage difference becomes almost zero, so that P5 in the amplifier 3 and P6 in the amplifier 4 are initialized, causing an error. Is erased.

After a lapse of a predetermined time, the third initialization switches SW8 of the amplifiers 3 and 4 are opened. After a lapse of a predetermined time, the multiplexers MUX1 to MUX10, MUX1
At the same time as IN0 of 1 to X20 and MUX30 are opened, IN1 of these multiplexers is closed. The analog voltages X1 to X10 are based on the signals S1 to S10,
UX1 to MUX10 or multiplexer MUX11 to MUX2
Input to any of 0.

When the analog voltages X1 to X10 are input to the multiplexers MUX1 to MUX10, the multiplexers output the analog voltages X1 to X10 to the amplifier 3.
As described above, P5 in the amplifier 3 is the analog voltage X1.
Has been initialized just before the input of the analog voltages X1 to X10, so that the product sum of the analog voltages X1 to X10 without error is input to the amplifier 3. The amplifier 3 outputs the product sum of the analog voltages X1 to X10 to the amplifier 4 via the multiplexer MUX30. Again, as described above, P6 in the amplifier 4
Is initialized immediately before the sum of products of the analog voltages X1 to X10 is input to the amplifier 4, and data having no error is input to the amplifier 4.

On the other hand, when the analog voltages X1 to X10 are input to the multiplexers MUX11 to MUX20, these multiplexers add the product sum of the analog voltages X1 to X10 to the amplifier 4.
Output to As described above, the sum of the products of the analog voltages X1 to X10 without error is input to the amplifier 4. Adder ADD
The amplifier 4 outputs the product sum of the analog voltages X1 to X10 as the operation result of the sequential operation circuit according to the present invention.

[0026]

As described above, each sample and hold circuit includes a plurality of sample and hold circuits connected in series so as to sequentially hold and sequentially transfer an analog voltage, and an arithmetic circuit for calculating the output of each sample and hold circuit.・ Hold circuit
An input-side switch, an input-side capacitance, a first-stage amplifier, an intermediate switch, an intermediate capacitance, and a second-stage amplifier are connected in series, and the input and output of the first and second-stage amplifiers are connected by feedback capacitance. A sequential operation in which the input and output are connected to be openable and closable by first and second initialize switches, respectively, and the arithmetic circuit has an amplifier therein and the input and output of the amplifier are connected to be openable and closable by a third initialize switch; in the circuit, the second, the third initialization switch is closed to <br/> after the first initialization switch is opened, the first initialization switch, after the second, third initialization switch is opened As it is designed to be closed, errors due to charge charging are prevented,
In addition, there is an effect that generation of an error due to initialization can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram of a sequential operation circuit according to the present invention.

FIG. 2 is an example of a circuit diagram of a sample and hold circuit.

FIG. 3 is an example of a circuit diagram of a multiplier.

FIG. 4 is an example of a circuit diagram of an adder.

FIG. 5 is a timing chart of each switch.

[Explanation of symbols]

H1 to H10 Sample and hold circuit M1 to M10 Multiplier ADD Adder X1, X2, X3, X10, Xn Analog voltage SW1 to SW8 Switch C11 Input capacitance C21 Intermediate capacitance C12, C22 Feedback capacitance AMP1 First amplifier AMP2 Second amplifier 1 , 2, 3, 4 Amplifier A Reference voltage B, C, D, E Potential OUT output MUX 31 , MUX 32 , MUX 33, MUX 1 to MUX 10,
MUX11 to MUX20, MUX30 Multiplexer C31, C32, C33, C61 to C70, C71 to C80, C90
Capacitance S1 ~ S10 signal P1, P2, P3, P4, P5, P6 Input terminal of amplifier

Continued on the front page (72) Inventor Makoto Yamamoto 3-5-18 Kitazawa, Setagaya-ku, Tokyo Takayama Building Co., Ltd. Takayamauchi (72) Inventor Osamu 3-5-18 Kitazawa, Setagaya-ku, Tokyo Takayama Building Co., Ltd. Takayamauchi (72) Inventor Akira Urushiba 3-5-18 Kitazawa, Setagaya-ku, Tokyo Takayama Building Co., Ltd. Takayamauchi Examiner Yoshio Mizuno (56) References JP-A-58-35670 (JP, A) JP-A Sho JP-A-63-289462 (JP, A) JP-A-2-64788 (JP, A) JP-A-6-237148 (JP, A) JP-A-7-6190 (JP, A) A) (58) Field surveyed (Int.Cl. ⁷ , DB name) G06G 7/12 G06G 7/14 G06G 7/16

Claims (2)

(57) [Claims] A plurality of sample and hold circuits connected in series to sequentially hold and sequentially transfer an analog voltage;
An arithmetic circuit for calculating the output of each sample-and-hold circuit, wherein each sample-and-hold circuit connects an input-side switch, an input-side capacitance, a first-stage amplifier, an intermediate switch, an intermediate capacitance, and a second-stage amplifier in series A first input initialization switch connected in parallel to the input side switch, and a second input initialization switch connected in parallel to the intermediate switch, wherein the first and second stage amplifiers are connected. The input and output are connected by a feedback capacitance, and the input and output are connected to be openable and closable by first and second initialization switches, respectively. The arithmetic circuit has an amplifier therein, and the input and output of the amplifier are connected to a third initialization switch. A sequential operation circuit that is openably and closably connected by the second and third circuits. Nisha Rise switch is closed after the first initialization switch is opened, first
A sequential operation circuit, wherein the initialization switch is closed after the second and third initialization switches are opened. 2. The arithmetic circuit comprises a plurality of multipliers and one multi-input adder. The output of the sample and hold circuit is input to the multiplier, and each of the multiplier and the adder has an amplifier. And a third initialization switch connected to each of the amplifiers.
The sequential operation circuit according to the above.