JP2985997B2 - Multiplication circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplication circuit, and more particularly to a multiplication circuit capable of directly multiplying digital data and analog data.

[0002]

2. Description of the Related Art In recent years, capital investment for microfabrication processes has increased remarkably, and the limitations of digital computers have been discussed. Thus, computers based on analog arithmetic are being reviewed.
On the other hand, the need for cooperation with already accumulated digital technologies is also high, and an arithmetic processing system in which analog data and digital data are mixed is important. However, conventionally, there is no known arithmetic circuit in which analog and digital are mixed.

[0003]

SUMMARY OF THE INVENTION The present invention has been made to solve such a conventional problem, and an object of the present invention is to provide a multiplication circuit capable of directly multiplying analog data and digital data. I do.

[0004]

SUMMARY OF THE INVENTION A multiplying circuit according to the present invention allows an analog voltage level-compensated by an operational amplifier to conduct an output of the operational amplifier by switching of a field-effect transistor, and to connect digital data to the gate of the field-effect transistor. Is input.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the multiplying circuit according to the present invention will be described with reference to the drawings. 1 includes a pair of operational amplifiers Amp ₃ and Amp ₄ and a pair of field effect transistors Tr ₃ and Tr ₄ , and the input analog data AX is input to the non-inverting input of Amp ₃ . The output of Amp ₃ is T
It is connected to the drain of r ₃ , and the source of Tr ₃ is grounded via capacitances C ₃ and C ₄ . And C ₃ , C ₄
The voltage between them is fed back to the inverting input of Amp ₃ . Tr ₃ has a digital input B input to the gate and B
Conducts when is at a high level. When Tr ₃ is conducting,
C ₄ output of Amp ₃ so that the voltage equal to AX is applied is adjusted to, charge so that the charging voltage is AX stored in the C _4. At this time, the source voltage of the Tr ₃ becomes _{AX {(C 3 -C 4)} / C 3}.

A non-inverting input of Amp ₄ is grounded, and its output is connected to the source of Tr ₄ . The drain of Tr ₄ is connected to C ₃ and is fed back to the inverting input of Amp ₄ . Digital data obtained by inverting B with the inverter INV is input to the gate of Tr ₄ , and Tr ₄ conducts when B is at a low level. When Tr ₄ is conducting, the output of Amp ₄ is adjusted so that 0 V is generated at the drain of Tr ₄ .

[0007] The source of Tr ₃ and the drain of Tr ₄ are connected to an output capacitance C ₅ , and a weighted voltage value determined by capacitive coupling including C ₅ becomes an output.
That is, M has executed AX by multiplying by ｛(C ₃ −C ₄ ) / C ₃ ｝ C _cp C _cp : weight determined by capacitive coupling or a multiplier of 0.

Here, the capacitive coupling means a configuration as shown in FIG. 4, and a plurality of capacitances (here, 8 of C _{51 to} C ₅₈ ).
Are connected in parallel. When the voltage V ₁ ~V ₈ is applied to these capacitances, the output voltage V _{8 is, V 8 = (C 51 V} 1 + C 52 V 2 + ··· + C 58 V 8) / (C 1
+ C ₂ +... + C ₈ ), and weighted addition is performed.

A circuit as shown in FIG. 1 is provided in parallel, and each bit of digital data is inputted as B, and ｛(C ₃ -C ₄ )
If / C ₃ ｝ C _cp is set to 2 ⁿ , multiplication of analog data AX and digital data can be directly performed. Although the above multiplication circuit can be applied to various uses, the filter circuit shown in FIG. 2 is an advantageous application. Figure in the multiplication circuit M ₁₁ ~
M ₁₈ and M _{21 to} M ₂₈ are shown.

[0010] In FIG. 2, the filter circuit has a first product-sum circuit MC1 and the second sum-of-products circuit MC2, first sum-of-products circuit MC1 connects a plurality of holding circuit H ₁₁ to H ₁₈ in series And the output of each hold circuit H _1k becomes a multiplication circuit M _1k
Has been entered. While the second sum-of-products circuit MC2 is constituted by connecting a plurality of hold circuits H ₂₁ to H ₂₈ in series, the output of the holding circuit H _2k is inputted to the multiplier circuit M _2k.

[0011] Input data D _in is input to the first sum-of-products circuit, and D _in is temporarily held by each hold circuit and then transferred to the next-stage hold circuit. This time-series data of D _in the respective hold circuit is held. This time-series data is represented here as X (tk). Each multiplier circuit M ₁₁ ~M ₁₈ is inputted predetermined multiplier a ₁ ~a ₈ in advance, when performing the following multiplication for series data. m _1k = _ak × X (tk) m _1k : multiplication result of multiplication circuit M _1k

The outputs of the multiplication circuits M _1k and M _{1 (k + 1)} are added by an addition circuit A _1k , and the addition result is added to the next addition circuit A
Output to _{1 (k + 1)} . Therefore, the sum of the outputs of all of the multiplication circuit is the addition circuit A ₁₇ in the first product-sum circuit

(Equation 1) Is calculated.

[0013] The second product-sum circuit, via a switch SW, A ₁₇ output or H ₁₈ output is input as the second input data D _m, D _m is temporarily held by the holding circuit H ₂₁ to H ₂₈ After that, the data is transferred to the next-stage hold circuit. Thus, each hold circuit holds _Dm time-series data. This time-series data is expressed as Y (t−
k). Each of the multipliers M _{21 to} M ₂₈ has a predetermined multiplier b.
₁ ~b ₈ is inputted in advance, when performing the following multiplication for series data. m _2k = b _k × Y (tk) m _2k : multiplication result of the multiplication circuit M _2k

The outputs of the multiplication circuits M _2k and M _{2 (k + 1)} are added by an addition circuit A _2k , and the addition result is added to the next addition circuit A
Output to _{2 (k-1)} . Therefore, the adding circuit A ₂₇ is a sum of outputs of all the multiplying circuits in the second product-sum circuit.

(Equation 2) Is calculated.

[0015] The output of the adder A ₂₁ is input to the adder A ₁₇ in the first product-sum circuit MC1, the output of which the A ₁₇ is the sum of MC1, MC2 both multiplication results. If SW is connected to the H ₁₈ side, D _m is X (t-
8) and the output of MC2 is

(Equation 3) Becomes Here, if b _k = a _{(k + 8)} , the sum of MC1 and MC2 output from A ₁₇ is

(Equation 4) It can be seen that the characteristics of the FIR filter can be obtained.

[0016] If the SW is connected to the side A _17,

(Equation 5) It is generally expressed as Y (t) = D _m, and it can be seen that IIR type characteristics were obtained.

As described above, two types of filters, FIR and IIR, are realized by switching only the SW in the dedicated circuit. In the case of the FIR type, a relatively large number of stages utilizing all hold circuits and multiplication circuits Is realized. That is, a filter having both versatility and high speed can be realized.

FIG. 3 shows an embodiment of the hold circuit _{Hjk in} FIG.
H _jk has a pair of operational amplifiers Amp ₁ and Amp ₂ and a pair of field-effect transistors Tr ₁ and Tr ₂ , and input data d _in is input to the non-inverting input of Amp ₁ . The output of Amp ₁ is connected to the drain of the Tr _1, the source of the Tr ₁ is fed back to the inverting input of Amp ₁ is grounded through a capacitor C _1. Tr ₁ clock CLK ₀ is input to the gate, CLK ₀ is conductive when the high level. Of the time conduction tr _1, the output of Amp ₁ is adjusted so that the voltage equal to d _{i n} is applied to the C _1, C ₁
Is charged so that the charging voltage becomes d _in .

The charged voltage of C ₁ is connected to Amp ₂ noninverting input, the output of Amp ₂ is connected to the drain of the Tr _2, T
The source of r ₂ is grounded via a capacitance C ₂ and is fed back to the inverting input of Amp ₂ . The gate of Tr ₂ is supplied with a clock CLK ₁ having a phase opposite to that of CLK ₀ , and is conducted at a phase opposite to that of Tr ₁ . Tr ₂
During conduction, the voltage equal to d _in the charging voltage of C ₁ is C ₂
The output of Amp ₂ is adjusted so as to be applied, and charge is stored _in C _{2 so} that the charging voltage becomes d _in, and d _out corresponding to d _in is output. This is held only d _{i n} timing of one clock, and since the time of charging the C ₁ no influence on the subsequent stage, can reliably held at a predetermined timing is performed.

The adder circuit _Ajk can also be realized by a configuration in which FIG. 4 has two or three inputs. The output signal _Dout output by the above configuration is once held at _Hout .

[0021] FIG. 5 shows a second embodiment of a filter circuit, instead of the adding circuit A _jk, 1 single adder circuit A _t
Is used. When the outputs of the multiplier circuits M _jk and m _jk,
As shown in FIG. 6, weighted addition is performed by capacitive coupling formed by connecting capacitances C _jk in parallel. The operation form is the same as the circuit of FIG.

[0022]

As described above, the multiplying circuit according to the present invention makes the analog voltage level-compensated by the operational amplifier conduct the output of the operational amplifier by switching the field-effect transistor, and supplies the digital data to the gate of the field-effect transistor. Is input, so that it is possible to directly multiply analog data and digital data.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a multiplication circuit according to the present invention.

FIG. 2 is a block diagram showing a filter circuit using the embodiment.

FIG. 3 is a circuit diagram showing a hold circuit in the filter circuit.

FIG. 4 is a circuit diagram showing an example of capacitive coupling.

FIG. 5 is a block diagram showing a second embodiment of the filter circuit.

FIG. 6 is a circuit diagram showing an adding circuit in a second embodiment of the filter circuit.

[Explanation of symbols]

H _jk , H _{11 to} H ₁₈ , H _{21 to} H ₂₈ , H _in , H _out Hold circuit MC1, MC2 Product-sum circuit D _in , d _in Input data M _{11 to} M ₁₈ , M _{21 to} M ₂₈ , M Multiplication circuit _{A 11 ~A 17, A 21 ~A} 27, A t adder circuit SW switches Amp ₁ ~Amp ₄ operational amplifier Tr ₁ to Tr ₄ field effect transistor _{C 1 ~C 5, C 51 ~C} 58 capacitance CLK _0, CLK ₁ clock AX analog data B digital input INV inverter V ₁ ~V ₈ voltage V ₈ output voltage D _out output signal _{m 11 ~m 18, m 21 ~m} 28 output of the multiplier circuit

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kotobuki Kokuryo 3-5-18 Kitazawa, Setagaya-ku, Tokyo Co., Ltd. Takayamauchi (72) Inventor Nao Takatori 3-5-18 Kitazawa, Setagaya-ku, Tokyo Co., Ltd. Takayamauchi (72) Inventor Makoto Yamamoto 3-5-18 Kitazawa, Setagaya-ku, Tokyo Takayamauchi Co., Ltd. (56) References JP-B-52-26858 (JP, B2) (58) Fields surveyed (Int.Cl) . ^6, DB name) G06J 1/00 - 3/00

Claims (1)

(57) [Claims] 1. A multiplication circuit for multiplying an analog input voltage by 1-bit digital data having a predetermined weight, comprising: an inverting input and a non-inverting input, wherein the analog input voltage is connected to the non-inverting input. A first operational amplifier having a source, a drain, and a gate, wherein the one-bit digital data is connected to a gate, and an output of the first operational amplifier is connected to a drain; An inverter for inverting digital data; a second operational amplifier having an inverting input and a non-inverting input, the non-inverting input being grounded; and having a source, a drain and a gate, wherein the output of the inverter is connected to the gate; An output of the second operational amplifier is connected to a source, a drain is fed back to an inverting input of the second operational amplifier, and A second field effect transistor connected to the source of the field effect transistor; having a first terminal and a second terminal, a first terminal connected to the source of the first field effect transistor, and a second terminal connected to the first terminal. A first capacitance fed back to the inverting input of the operational amplifier; a first capacitance having a first terminal and a second terminal, the first terminal being connected to the second terminal of the first capacitance, and the second terminal being grounded. The analog input voltage is AX, the 1-bit digital data is B, the capacitance of the first capacitance is C3, the capacitance of the second capacitance is C4, the source of the first field-effect transistor and the second field-effect transistor. Assuming that the output voltage generated at the drain is V, V = AX · {(C3-C4) / C3} · B Circuit.