JP3118243B2 - LCD drive circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LCD drive circuit for driving an LCD (liquid crystal monitor) by alternating current, and more particularly, to stabilizing the pedestal level of an LCD drive signal and changing the pedestal level. The present invention relates to an LCD drive circuit that suppresses the rate and improves the gradation of LCD display.

[Conventional technology]

When driving an LCD using a CRT video signal, it is necessary to convert the CRT video signal into an LCD drive video signal because the LCD video signal has a different waveform from the CRT video signal.

That is, when the LCD is driven by direct current, the ionic impurities in the liquid crystal material are charged, and the electrodes and the liquid crystal material are oxidized and reduced, thereby deteriorating these materials and significantly shortening the life. For this reason, it is necessary to drive the LCD in AC, and an AC video signal is generated from a DC video signal. In order to generate the AC video signal, the polarity of the video signal is also converted.

FIG. 6 shows a block configuration of a general LCD drive circuit for a color LCD. This LCD drive circuit has three primary color video signals R,
An amplifier circuit 91 for amplifying G and B, a counter electrode inverting circuit 93, and a pedestal level clamp circuit 95 are provided.

The counter electrode inversion circuit 93 inverts the polarity of the video signal applied to the opposite electrode in the LCD for each horizontal line of the LCD.

The pedestal level clamp circuit 95, as shown in FIGS. 7 (a) to 7 (c), reproduces the video signal from which the DC component has been lost in the preprocessing (FIG. 7 (c)) in order to faithfully reproduce the brightness of the video. ) Is a circuit for generating a video signal (FIG. 7B) reproduced from the DC component. That is, when the DC component is lost, the zero level of the AC signal shifts to the average level as shown in FIG. 7 (c), and the pedestal level, which is the reference of the video signal, moves. When the pedestal level moves, for example, as shown on the left end of FIG. 7 (a), when the LCD screen is partially “black” on the whole “white” screen, the originally white part is gray. LCDs that become colored or, conversely, as shown on the right end of FIG. 7 (c), become entirely “black” and partially “white”
In the case of a screen, a portion that is originally black becomes gray, and a faithful density cannot be reproduced. Therefore, the pedestal level is clamped to a certain level by the pedestal level clamp circuit 95.

FIG. 8 shows the configuration of a conventional LCD drive circuit. This LCD drive circuit is one of the color LCD drive circuits, for example,
This figure shows the circuit for red (R), and shows the amplifier circuit 91R, the polarity inversion circuit 93R, the pedestal level clamp circuit 95R, and the video signal before the polarity inversion and the video whose polarity is inverted from the pedestal level clamp circuit 95R. It comprises a switching circuit 97R for switching signals. The switching circuit 97R is switched in accordance with a video signal synchronization signal to generate an AC drive signal,
The AC drive signal from the switching circuit 97R is
To drive the LCD in AC.

FIG. 10 shows an example of a waveform of an output signal from the LCD drive circuit shown in FIG. As shown in FIG. 9, the signal waveform in FIG. 10 uses a signal in which black follows the steer case (upper) and a signal in which white follows the steer case (lower) for evaluation. It is.

FIGS. 11 (a) and 11 (b) show images of an LCD driven by the conventional LCD drive circuit by the output signals shown in FIG. FIG. 11 (a) is a diagram corresponding to the signal on the upper side of FIG. 9, and FIG. 11 (b) is a diagram corresponding to the signal on the lower side of FIG.

[Problems to be solved by the invention]

According to the conventional LCD drive circuit, as shown in FIG. 11B, there is a problem that the density (gradation) of the LCD image is large.

The cause is (a / b) X100, as shown in Fig. 10.
This is because the pedestal level fluctuation rate defined by (%) is as large as 25%. It is considered that the reason is that the pedestal level of the video signal that has not been pedestal-clamped fluctuates due to various factors such as passing through an amplifier circuit and noise. In particular, the amount of relative fluctuation is large for a pedestal clamped video signal whose polarity is inverted.

Therefore, an object of the present invention is to provide an LCD drive circuit capable of improving the pedestal level fluctuation rate and improving the gradation characteristics.

[Means for solving the problem]

As shown in FIG. 1, the LCD drive circuit of the present invention has a basic concept in addition to a first pedestal level clamp circuit 3 provided at an output stage of a polarity inversion circuit 1 for inverting the polarity of a video signal. A second pedestal level clamp circuit 5 for clamping a pedestal level also for a non-inverted video signal whose polarity is not inverted is provided.

That is, in order to facilitate understanding, the LCD drive circuit of the present invention will be described with reference to FIGS. 1 and 2 in which reference numerals are used to describe an input video signal, a first pedestal level clamp signal, A first switching circuit (20) for switching a second pedestal level clamp signal to generate a second video signal including a first pedestal level clamp signal and a second pedestal level clamp signal; A differential amplification type inverted / non-inverted video signal generation circuit (1, 10) for outputting an inverted video signal and a non-inverted video signal from the second video signal generated by the switching circuit (20), and a pedestal based on the horizontal synchronization signal Control pulse (CLAM
Pedestal control pulse generation circuit that generates P) (80)
And an inverted video signal output from the differential amplification type inverted / non-inverted video signal generation circuit (1, 10) according to the pedestal control pulse (CLAMP) generated by the pedestal control pulse generation circuit (80). A first pedestal level clamp circuit (3, 30) for clamping a first pedestal level clamp signal included therein; and the difference according to a pedestal control pulse (CLAMP) generated by the pedestal control pulse generation circuit (80). A second pedestal level clamp circuit (5, 50) for clamping a second pedestal level clamp signal included in the non-inverted video signal output from the dynamic amplification type inverted / non-inverted video signal generation circuit (1, 10); A second output for selectively outputting the outputs of the first and second pedestal level clamp circuits in response to an LCD operation cycle;
And a switching circuit (7, 70).

[Action]

A first switching circuit (20) generates a second video signal including a first pedestal level clamp signal and a second pedestal level clamp signal for an input video signal. As a result, two stable pedestal level clamp signals to be clamped in a later operation are included in the video signal.

Differential amplification type inverted / non-inverted video signal generation circuit (1,10)
In step (1), an inverted video signal including a pedestal level clamp signal whose polarity is inverted and a non-inverted video signal including a pedestal level clamp signal whose polarity is not inverted are generated.

The first pedestal level clamp circuit (3, 30) generates a first pedestal level clamp signal included in the inverted video signal according to the pedestal control pulse (CLAMP) generated by the pedestal control pulse generation circuit (80). Clamp. The added second pedestal level clamp circuit (5, 50) includes a pedestal control pulse (CLAM) generated by the pedestal control pulse generation circuit (80).
According to P), the second pedestal level clamp signal included in the non-inverted video signal is clamped. in this way,
By clamping the pedestal levels for both the inverted video signal and the non-inverted video signal, the pedestal levels of the polarity-inverted video signal and the non-inverted video signal applied to the second switching circuit (7, 70) are stabilized.
As a result, the pedestal fluctuation rate decreases. In addition, since the above-described clamping operation is performed alternately for each horizontal synchronization signal in accordance with the pedestal control pulse (CLAMP) generated by the pedestal control pulse generation circuit (80), flicker generated when performing each vertical synchronization signal is reduced. Can be prevented.

The second switching circuit (7, 70) outputs an AC drive signal including the pedestal clamp signal to the LCD in response to the LCD operation cycle, and AC drives the LCD.

In the LCD drive circuit of the present invention, since the pedestal level fluctuation rate is small, the gradation of the LCD image is improved. Furthermore, the LCD drive circuit of the present invention switches the pedestal level clamping operation according to the horizontal synchronization signal, so that flicker is reduced.

〔Example〕

FIG. 2 shows an LCD drive circuit diagram of the embodiment of the present invention. This LCD drive circuit shows a drive circuit for red (R) among the three primary colors for color LCD. The same applies to the other three primary colors, green (G) and blue (B), and a description thereof will be omitted.

In FIG. 1, an amplification / polarity inversion circuit 10 is composed of transistors 11 and 12 and resistors 13 to 19 which are differentially connected. This differential transistor circuit is an amplifier circuit having a gain of, for example, 15 dB in order to amplify the voltage level of the video signal R to a voltage level for driving an LCD (not shown). Also, since the video signal R has a wide frequency band in the range of 0 to 0.4 MHz, this differential transistor amplifier circuit has a wide frequency characteristic in order to faithfully reproduce the video signal R. The video signal R is applied to the bases of the transistors 11 and 12 connected to the differential pair via the circuit 20, and the base of the transistor 12 is grounded. Therefore, the collector output of transistor 11 inverts the signal applied to the base of transistor 11, and the collector output of transistor 12 outputs a non-inverted signal. That is, the amplification and polarity inversion circuit 10
The video signal is amplified, the transistor 11 inverts the polarity of the video signal, and the transistor 12 is configured not to invert the polarity of the video signal.

The first pedestal level clamp circuit 30 includes a capacitor 31, a transistor 32, and a first clamp voltage source 33.
It is composed of This first clamp voltage source 33 has a voltage
It consists of a variable resistor provided between Vcc and the earth,
It is connected to apply the first clamp voltage EREF1 to the emitter of the transistor 32. Therefore, the transistor 32 of the first pedestal level clamp circuit 30
Is turned on by the clamp control pulse CLAMP,
The collector level is set to the first clamp voltage EREF1.

Similarly, the second pedestal level clamp circuit 50
It comprises a capacitor 51, a transistor 52, and a second clamp voltage source 53. This second clamp voltage source
53 is also constituted by a variable resistor provided between the voltage Vcc and the ground, and is connected so as to apply the second clamp voltage EREF2 to the emitter of the transistor 52. Similarly, when the transistor 52 of the second pedestal level clamp circuit 50 is turned on by the clamp control pulse CLAMP, its collector level is changed to the second clamp voltage ER.
Change to EF2.

The video signal R is supplied to a first level adjusting / switching circuit 2a, comprising a variable resistor 21 and a switching circuit 22,
The voltage is applied to the amplification / polarity conversion circuit 10 via the level adjustment / switching circuit 20 including the second level adjustment / switching circuit 2b including the variable resistor 24 and the switching circuit 25.

Further, a first buffer circuit 6a having a transistor 61 at a stage subsequent to the first pedestal level clamp circuit 30 and a second buffer circuit 6b having a transistor 61 at a stage subsequent to the second pedestal level clamp circuit 50 are provided. ing. Then, the outputs of the buffer circuits 6a and 6b are applied to the switching circuit 70, and the switching circuit 70
An LCD drive AC voltage output VR is output to an LCD (not shown).

First and second pedestal level clamp circuits 30,5
The clamp control pulse CLAMP for controlling 0 is supplied to a switching circuit 81 which is energized by the horizontal synchronization signal H-SYNC, a circuit 82 for filtering the output of the switching circuit 82,
The signal is output from a clamp control pulse generation circuit 80 including a switching circuit 83 that is switching-controlled by the output of the filtering circuit 82.

 The operation of the LCD drive circuit shown in FIG. 2 will be described.

The signal level of the video signal R can be adjusted by a variable resistor 21. The level-adjusted video signal R is switched in the switching circuit 22. The switching of the switching circuit 22 is performed by a control signal C that utilizes (validates) the entire video signal. The switched video signal R is applied to a switching circuit 25 which is energized by a red (R) video control signal Rc as shown by a solid line in FIG.
Is applied to

FIGS. 3A and 3B show the operation characteristics of the amplification and polarity inversion circuit 10. FIG. FIG. 3 (a) shows Orangestar 11
FIG. 3 (b) shows an inverted signal at the collector of the transistor 11 in FIG. As is apparent from this figure, the polarity of the input video signal R having a one-way inclination is inverted to a signal having both inclinations with respect to the center level. However,
The collector output of transistor 12 is not inverted.

It should be noted that if the polarity inversion is performed for each vertical synchronization signal, flicker is noticeable. Therefore, the polarity is inverted for each horizontal synchronization signal H-SYNC so that flicker is not noticeable.

Since the polarity inversion is realized by a configuration in which the transistors 11 and 12 are operated in a differential manner, the frequency characteristics are good.

The output of the amplification / polarity inversion circuit 10 is applied to the buffer circuits 6a and 6b via the collectors of the first and second pedestal level clamp circuits 30 and 50. When a "high" level pedestal control pulse CLAMP is applied to the transistors 32 and 52 of the first and second pedestal level clamp circuits 30 and 50, the base of the transistors 61 and 62 of the buffer circuits 6a and 6b is A first clamp voltage EREF1 and a second clamp voltage EREF2 are applied. On the other hand, when the pedestal control pulse CLAMP is at the “low” level,
The outputs of the collectors of the transistors 11 and 12 of the polarity inversion circuit 10 are directly applied to the bases of the transistors 61 and 62.

Here, when the pedestal control pulse CLAMP is at the “high” level, the base voltages of the transistors 61 and 62 surely become the first and second clamp voltages, so that the pedestal level fluctuation rate decreases as described later. .

Outputs of the buffer circuits 6a and 6b are applied to input terminals of a switching circuit 70, and the switching circuit 70 switches a switching signal SW for switching these applied signals to AC.
To output an AC voltage signal VR for AC driving the LCD.

Therefore, the LCD is AC driven by the AC drive voltage signal VR.

FIG. 4 shows a waveform diagram of the AC voltage drive signal VR. This signal waveform diagram corresponds to the conventional signal waveform diagram shown in FIG. 10, and for evaluation purposes, as in the conventional case, the signal in FIG. 9, that is, the signal (upper) in which a steer case is followed by black (upper). ,
This uses a signal (lower side) in which a steer case is followed by white.

The pedestal level fluctuation rate, (a / b) × 100 (%), for the signal waveform shown in FIG. 4 was 9%.
This value is much smaller than the above-mentioned conventional pedestal level fluctuation rate of 25%.

Therefore, as shown in the LCD image diagrams in FIGS. 5A and 5B, the gradation of the LCD image is improved. FIG. 5 (a) corresponds to the upper side of FIG. 9, and FIG. 5 (b) corresponds to the lower side of FIG.

〔The invention's effect〕

As described above, the present invention reduces the pedestal level fluctuation and performs AC driving by not only applying pedestal clamp to the polarity-reversed video signal but also applying pedestal clamp to the non-inverted video signal. LCD gradation could be improved.

Also, in the present invention, since the polarity is inverted by the horizontal synchronization signal, flicker of the LCD image is insignificant.

[Brief description of the drawings]

FIG. 1 is a block diagram of an LCD drive circuit of the present invention, FIG. 2 is a diagram of an LCD drive circuit of an embodiment of the present invention, and FIGS. 3 (a) and 3 (b) are diagrams of the amplifier / polarity inverting circuit of FIG. FIG. 4 is an input / output signal waveform diagram, FIG. 4 is an LCD drive circuit output signal waveform diagram of the embodiment of the present invention, FIGS. 5 (a) and (b) are LCD playback video diagrams according to the embodiment of the present invention, and FIG. FIG. 7 (a) to FIG. 7 (c) are diagrams showing a general relationship between an LCD screen and video signals, FIG. 8 is a conventional LCD drive circuit diagram, FIG. The figure is an exemplary evaluation signal waveform diagram, FIG. 10 is a conventional LCD drive circuit output waveform diagram, and FIGS. 11 (a) and (b) are conventional LCD playback video diagrams. (Explanation of Signs) 1 ... Polarity Inverting Circuit, 3,5 ... Pedestal Level Clamp Circuit, 7 ... Switching Circuit, 10 ... Amplifying / Polarity Inverting Circuit, 20 ... Level Adjusting / Switching Circuit, 30,50 ... … Pedestal level clamp circuit, 70… switching circuit, 80… pedestal control pulse generation circuit, 6a, 6b… buffer circuit.

Claims (1)

(57) [Claims] A first pedestal level clamp signal; a second pedestal level clamp signal including a first pedestal level clamp signal and a second pedestal level clamp signal; A first switching circuit for generating a video signal, and a differential amplification inverted / non-inverted video for operating and amplifying the second video signal generated by the first switching circuit to output an inverted video signal and a non-inverted video signal A signal generation circuit, a pedestal control pulse generation circuit that generates a pedestal control pulse based on a horizontal synchronization signal, and the differential amplification type inverted / non-inverted video according to the pedestal control pulse generated by the pedestal control pulse generation circuit. First pedestal signal included in the inverted video signal output from the signal generation circuit A first pedestal level clamp circuit for clamping a clamp signal, and a non-inverted video output from the differential amplification type inverted / non-inverted video signal generation circuit in response to a pedestal control pulse generated by the pedestal control pulse generation circuit. A second pedestal level clamp circuit that clamps a second pedestal level clamp signal included in the signal; and a second pedestal level clamp circuit that selectively outputs the outputs of the first and second pedestal level clamp circuits in response to an LCD operation cycle. An LCD drive circuit comprising: a second switching circuit;