JP3116419B2 - Effect adding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an effect adding device,
More specifically, the present invention relates to an effect adding device that varies a phase of an input sound to be modulated and a mixing ratio between the shifted input sound and the original sound in accordance with the input level of the original sound.

[0002]

2. Description of the Related Art Conventionally, a high-frequency waveform shifted by using a phase shifter that changes the phase of an input sound and a high-pass filter that deletes a low-frequency portion of a sound waveform whose phase has been changed by the phase shifter. A so-called exciter, which is an effect adding device for phase-shifted waveform mixing that enhances high-frequency overtones by adding this to the original sound waveform to enhance the sound, has been known. In the above-described hardware configuration, for example, when the input signal is sin θ and the phase angle is changed by 90 ° by the phase shifter, the output obtained by mixing this with the original input signal is sin θ + sin (θ + 90 °) = 2 ^1/2 s
in (θ + 45 °), and the amplitude increases. Then, since the low-pass is removed by the high-pass filter, the amplitude is increased only in the high-pass and the overtones in the high-pass are emphasized, so that the sound is sharpened and the sound comes out over the entire surface.

[0003]

However, with the above configuration, when used as an effector of an electronic stringed instrument, for example, the degree of phase modulation is constant regardless of the strength of the string operation, and the strength of the string operation is small. There is no significant change in timbre corresponding to. On the other hand, in an acoustic guitar, for example, the stronger the string is played, the greater the distortion generated in the sound, and the weaker the string, the more the sound is not distorted. In general, not only guitars but also natural instruments, when sounding operation is performed strongly, the modulation of the timbre changes slightly in accordance with the sounding operation, and the modulation is often emphasized.

As described above, in an electronic stringed musical instrument, even if an effect such as an exciter is added as described above and a string is changed to be strong / weak and operated, there is no change in timbre corresponding to the strength of the string operation. It is considered that this is caused firstly by the fact that the phase modulation characteristic of the phase shifter is constant, and secondly, the mixture ratio between the original sound and the effect sound is also constant.

An object of the present invention is to provide an effect adding device in which the effect of phase-shifted waveform mixing added to a generated sound is expressed by reflecting the strength of a performance operation.

[0006]

The means of the present invention are as follows. First, according to the first aspect of the present invention, the phase varying means changes the phase of the input acoustic signal and outputs the resultant signal. The means comprises, for example, an all-pass filter.

[0007] The level detecting means detects the input level of the input audio signal. The means comprises, for example, a full-wave rectifier. The phase control means varies the degree of phase shift of the output signal from the phase variable means based on the detection signal from the level detection means. The means includes, for example, a multiplier, an adder / subtractor, and the like.

[0008] The filtering means performs high-pass filtering on the signal from the phase varying means and outputs the signal. The means comprises, for example, a delay unit, an adder and the like. The mixing means mixes and outputs the signal from the filtering means and the input acoustic signal. The means comprises, for example, an adder.

The mixing ratio control means varies the mixing ratio between the input acoustic signal mixed by the mixing means and the signal from the filtering means based on the detection signal from the level detection means. The means includes, for example, a multiplier, an adder / subtractor, and the like.

[0010] According to the second aspect of the present invention, the level detecting means of the first aspect of the present invention extracts a predetermined signal which changes smoothly with time from an input audio signal, and extracts the extracted signal. The input level of the input audio signal is detected based on the input signal. The means comprises, for example, a low-pass filter or the like.

According to the third aspect of the present invention, the phase changing means changes the phase of the input acoustic signal and outputs the resultant signal. The means comprises, for example, an all-pass filter. The level detection means extracts an envelope of the input audio signal and detects an input level of the input audio signal based on the extracted envelope. The means
For example, it comprises an envelope extraction circuit and the like.

The phase control means varies the degree of phase shift of the output signal from the phase variable means based on the detection signal from the level detection means. The means includes, for example, a multiplier, an adder / subtractor, and the like.

The filtering means performs a high-pass filtering process on the signal from the phase changing means and outputs the signal. The means comprises, for example, a delay unit, an adder and the like. The mixing means mixes and outputs the signal from the filtering means and the input acoustic signal. The means comprises, for example, an adder.

The mixing ratio control means varies the mixing ratio between the input acoustic signal mixed by the mixing means and the signal from the filtering means based on the detection signal from the level detection means. The means includes, for example, a multiplier, an adder / subtractor, and the like.

[0015]

The operation of the means of the present invention is as follows. According to the first aspect of the present invention, when an audio signal is input, first, the input level of the input audio signal is detected by the level detection means. Then, when a change is made to the phase of the input acoustic signal, the degree of phase change is varied by the phase control means based on the detection signal from the level detection means. When the phase-shifted signal is filtered and mixed with the input audio signal, the mixing ratio is varied by the mixing ratio control unit based on the detection signal from the level detection unit.

Thus, the effect of the phase-shifted waveform mixing added to the generated musical tones is expressed by reflecting the strength of the performance operation. Further, as described in claim 2, the detection of the input level may be performed based on a predetermined signal that changes smoothly over time and is extracted from the input audio signal.

Thus, when the effect of the phase-shifted waveform mixture added to the generated musical tone is expressed by reflecting the strength of the performance operation, it changes smoothly. Next, according to the third aspect of the present invention, when an acoustic signal is input, the input level is detected,
This is performed based on the envelope extracted from the input acoustic signal. Then, the phase of the audio signal is changed based on the detection signal, and the phase-shifted and filtered audio signal is mixed with the input audio signal at a mixing ratio based on the detection signal.

As a result, the effect of the phase-shifted waveform mixing added to the generated sound is expressed by reflecting the sound envelope.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit configuration diagram of the electronic stringed instrument of the present embodiment.

In FIG. 1, a pickup 1 outputs an electric signal to a pair of positive and negative input terminals of a differential amplifier 2 in response to vibration of a string of an electronic stringed instrument. The differential amplifier 2 amplifies the potential difference between the electric signals input to the pair of input terminals and outputs the amplified signal to the electronic circuit unit 3 as a tone signal i. Electronic circuit part 3
Outputs a tone signal o obtained by adding a phase-shifted waveform mixing effect described later to the input tone signal i. This tone signal o
The tone quality is controlled by the tone control variable resistor 4, and the volume is controlled by the volume variable resistor 5, and then output to the outside via the output jack 6.

FIG. 2 is a block diagram showing the internal configuration of the electronic circuit section 3. As shown in FIG. In FIG.
The digital converter (AD) 21 is a digital signal
The analog tone signal i input from the differential amplifier 2 shown in FIG. 1 is sampled at a predetermined sampling interval and converted into a digital signal.
It is output to the DSP 22 as a digital input tone signal.

Accordingly, the digitally converted input tone signal sampled at a predetermined sampling interval is input to the DSP 22. A digital / analog converter (DA) 23 and a CPU (Central Processing Unit) 24 are also connected to the DSP 22.
Under the control of Step 4, the input tone signal from the AD 21 is subjected to the phase-shifted waveform mixing processing of the present invention, and the processed digital tone signal is output to the DA 23.

The DA 23 converts the tone signal from the DSP 22 from a digital signal to an analog signal and outputs it as an output tone signal o to a tone generator or the like (not shown). CPU2
4 operates in accordance with a microprogram stored in a built-in ROM (not shown) and controls the entire circuit. In addition to the DSP 22, the CPU 24 also
An M (read only memory) 25 and a RAM (random access memory) 26 are connected.

The ROM 25 stores a program, particularly a program for the phase-shifted waveform mixing process of the present invention, and other necessary data, coefficients, and the like.
Is used as a work area.

The CPU 24 transfers the program in the ROM 25 to the DSP 22, and causes the DSP 22 to execute the phase shift waveform mixing process. FIG. 3 is a functional block diagram for performing the phase shift waveform mixing process.

In the figure, a block 3-1 shown by a broken line
Performs the envelope extraction processing of the input tone signal, block 3
-2 is a phase shift process for the input tone signal, block 3-3 is a high-pass filtering process for the phase-shifted tone signal, and block 3
-4 performs mixing processing of the input tone signal and the tone signal subjected to the high-pass filtering process.

This will be described in more detail with reference to FIG. In block 3-1, the input tone signal W (IN
P) is input to the adders / subtractors 301, 302, and 303. In the adder 301, the input tone signal W (INP)
Is subtracted from the constant W (ZRO) having a value of “0”, and the result is provided to the positive / negative detector 304. This “0” subtraction process is a process for directly giving the value of the input musical tone signal W (INP) to the positive / negative detector 304.

In the adder / subtractor 302, the input tone signal W (INP) is added to a constant “0”, and the result is given to the gate 305. This addition processing to “0” is for giving the value of the input tone signal W (INP) to the gate 305 as it is.

In the adder / subtractor 303, the input tone signal W (INP) is subtracted from the constant "0", and the result is output to the gate 306.
Given to. This subtraction process from “0” is performed by inverting the value of the input musical tone signal W (INP) in the positive and negative directions and using the gate 306.
To give to.

The positive / negative detector 304 detects the most significant bit of the input tone signal W (INP), and if it is "0", activates the signal output to the gate 305,
Therefore, the gate 305 is turned on. On the other hand, if the detected bit is “1”, the signal output to the gate 306 is activated, and the gate 306 is turned on. .

Thus, if the most significant bit, that is, the sign bit is "0", that is, if the value of the input tone signal W (INP) is positive, the positive value W (INP) passes through the gate 305. On the other hand, the sign bit is "1", that is, the input tone signal W
If the value of (INP) is negative, W (INP), which has become a positive value due to inversion, passes through the gate 306.

As described above, the input tone signal W (INP)
Is converted from a negative value to a positive value and becomes a positive-only signal, that is, full-wave rectified waveform data W (EP0) and is input to the multiplier 307.

The multiplier 307 has a control unit (not shown)
A first low-pass filter coefficient P (CE0) is given as a multiplier, and input full-wave rectified waveform data W (EP0)
And the result is provided to the adder 308. The adder 308 adds the signal values input from the multiplier 309 described later, and outputs the result to the one-sample delay unit (Z ⁻¹ ) 310 and the adder 311.

The one-sample delay unit (Z ⁻¹ ) 310 is connected to the adder 3
08 is delayed by one sampling timing, and the low-pass filter delay output data W (CL
0) to multipliers 309 and 312.

A second low-pass filter coefficient P (CE1), which is a multiplier, is input to the multiplier 309 from the control unit. The coefficient P (CE1) and the one-sample delay unit (Z ^-1 )
Signal W one sampling timing prior to signal W
(CL0) and the result is multiplied by the adder 308 described above.
Output to The multiplier 312 also receives a third low-pass filter coefficient P (CE2) as a multiplier from the control unit, and multiplies the coefficient P (CE2) by the signal W (CL0) one sampling timing earlier. Then, the result is output to the adder 311.

The adder 311 sequentially convolves the input values by adding the output from the adder 308 and the output from the multiplier 312. With this cyclic operation,
A signal whose high-frequency component has been removed and becomes gentle, that is, an envelope W (CL1) is extracted. Then, the envelope W (CL1) is output to the multipliers 313 and 31.
4 and 315.

The multipliers 313, 314, and 315 include:
From the control unit, the first to third envelope coefficients P
(CE3), P (CE4), and P (CE5) are given, multiplied by the envelope W (CL1) inputted from the adder 311 respectively, and the result is output to adders / subtractors 316, 317, and 318, respectively. Is done.

The first to third offset data W (OF0), W (OF1), and W (OF2) are supplied from the control unit to the adders / subtractors 316, 317, and 318, respectively.

The adder / subtractor 316 subtracts the value input from the multiplier 313 from the first offset data W (OF0), and the result is used as first envelope data as a multiplier 320 related to a phase shift process described later. And 32
Output to 3.

Then, the adder / subtracter 317 adds the second offset data W (OF1) to the value input from the multiplier 313, and adds the result as second envelope data to a multiplier related to a mixing process described later. 330, and the adder / subtractor 318 outputs the third offset data W (O
F2) to the value input from the multiplier 313,
The result of the addition is output as third envelope data to a multiplier 331 related to the mixing process described later.

Thus, the extracted envelope has
Multiply each by the optimally set envelope coefficient,
Furthermore, three different envelope data obtained by adding the optimally set offset data are:
The variation coefficients of the phase shift processing or the mixing processing are respectively given to predetermined multipliers.

Subsequently, in the phase shift processing of the block 3-2, first, the input tone signal W (INP) is given to the adder 319. The adder 319 adds the output of the multiplication result of the multiplier 323 to be described later to the input musical tone signal W (INP), and sends the addition result to the multiplier 320 and the m-th order sample delay unit (Z- ^m ) 321. Output. Multiplier 320
Is added to the input tone signal W (INP) by an adder 316.
Envelope data W (EV0) input from
And outputs the result to the adder / subtractor 322.

Further, the m-th order sample delay unit (Z- ^m ) 321
The signal value input from the adder 319 is delayed by m sampling timings so that the phase shift delay output data T
(PH0) is output to the multiplier 323 and the adder / subtractor 322. The multiplier 323 also adds the phase shift delay output data T (PH0) to the adder 31 again.
6, the first envelope data W (EV
0), and outputs the multiplication result to the adder 319 described above.

The adder / subtractor 322 is a phase shift delay output data T from the m-th order sample delay unit (Z- ^m ) 321.
The input data from the multiplier 320 is subtracted from (PH0) to obtain all-pass output data W (AP0).

In general, the transfer function for performing the above-described phase shift processing is represented by X representing the input tone signal W (INP), b
_{If 1} is the first envelope data W (EV0) and Q given to the multipliers 320 and 323, Q is the phase shift delay output data T (PH0), and Y is the all-pass output data W (AP0), then Q − (Qb ₁ + X) b ₁
= Y and Q = (Qb ₁ + X) Z ⁻¹ , the amplitude characteristics are:

[0046]

(Equation 1)

And the value is always "1". That is, it is an all-pass filter. The phase characteristic is the phase term

[0048]

(Equation 2)

Is represented by This phase characteristic diagram is shown in FIG.
(A) to (d). In the figures (a) to (d),
When the first envelope data W (EV0) is a relatively large value "0.5", the change is large, and when the first envelope data W (EV0) is a relatively small value "0.3", the change is gentle (see FIG. a), (b)). Further, it is shown that the degree of change is emphasized when the delay order m is relatively large, such as “8”, and the degree of change decreases as the value decreases to “5” or “1”.

Returning to FIG. 3, as a result of the above, the input tone signal W (INP) is delayed by m sampling timings, that is, shifted in phase, so that the first envelope data W (INP) is shifted.
(EV0) modulated all-pass output data W (AP
0) is output to the multiplier 324 relating to the next high-pass filtering process.

The high-pass filtering processing of the next block 3-3 is performed with the same functional configuration as the low-pass filtering processing in the envelope processing of the block 3-1 except that only the filter coefficients used are different.
That is, the first to third low-pass filter coefficients P (CE
0), P (CE1) and P (CE2)
3 high-pass filter coefficients P (KE0), P (KE1)
And P (KE2) are respectively provided to predetermined multipliers.

As a result, the all-pass output data W (AP0) input to the multiplier 324 is a high-pass filter output data W (FL1) consisting of only the high-frequency components after removing a predetermined low-frequency component. Is output to the multiplier 331 in the mixing process.

In the mixing process of block 3-4, the multiplier 3
Reference numeral 30 denotes the second envelope data W (EV1) from the adder / subtractor 317 described above, which is added to the input tone signal W (INP).
And outputs the result to the adder 333.

As a result, the second envelope data W
(EV1), that is, the input tone signal W (INP) for which the mixture value is determined by the mixture ratio coefficient is input to the adder 333.

The multiplier 331 adds the above-mentioned adder 3 to the input high-pass filter output data W (FL1).
The third envelope data W (EV
2), and outputs the result to the adder 333.

Thus, the third envelope data W
The high-pass filter output data W (FL1) whose mixing value is determined by the mixing ratio coefficient (EV1) is added to the adder 3
33 is input.

The adder 333 adds the above two values and outputs the result to the outside as output waveform data W (MIX). Thus, the input tone signal W (I) whose mixing ratio is determined by the second and third envelope data, respectively.
NP) and the high-pass filter output data W (FL1) are mixed and output to an external tone generator or the like.

Next, FIG. 5 shows the internal configuration of the DSP 22 of FIG. 2 for executing the above-described phase-shift waveform mixing processing.
2, a program memory 201 is a memory for storing a predetermined microprogram,
A predetermined operation program is supplied to the control circuit 202 according to the instruction from the control circuit 202. Further, an address counter (not shown) is connected to the program memory 201.
The program memory 201 sequentially supplies the program contents to the control circuit 202 according to the address designation from the address counter.

The control circuit 202 controls the program memory 20
1 and the flag data F (AR) output from the register (AR) 222 described later, various data for transferring data between each register and memory, and controlling opening / closing of each gate and latch described later. A control signal and a counter value SC incremented at each sampling timing are output, and a desired signal processing operation is performed.

As shown in FIG. 6, the coefficient memory (P) 203 is a register for storing various parameters for adding a phase-shift waveform mixing effect.
Is read from the RAM 26 in FIG.
The data is transferred to the SP 22 and stored in the coefficient memory (P) 203.

As shown in FIG. 7, the work memory (W) 204 temporarily saves input waveform signals, various parameters, waveform signals created in the DSP 22, output waveforms, and the like. This is a working memory to be kept.

The delay offset memory (T) 205
Is a register for storing an offset value of an address of the delay memory (E) 105, which will be described later. The offset value is read out from the RAM 26 of FIG.

The delay memory (E) 106 has its output and input connected in a ring via registers (EI) 230 and (EO) 229, a counter value SC incremented at each sampling timing, and a delay offset The value obtained by adding the offset value from the memory 205 by the adder 227 is used as an address. The delay time of data written at a certain offset value is expressed by the difference between the offset delay and the read address offset delay. Therefore, by appropriately setting the offset value stored in the delay offset memory 205, an optimum delay time can be easily set, and a desired variable frequency component can be obtained.

Data is read from and written to the delay memory 106 via a register (EO) 229 and a register (EI) 230, and an address is specified via a register (EA) 228.

The input register (PI) 206 corresponds to A in FIG.
The digital tone signal from the D converter 21 is stored, and the signal is supplied to each unit via the internal bus 207. The output of the coefficient memory (P) 203, the output of the work memory (W) 204, and the output of the input register (PI) 206 are input to the gate terminals of the gates 208 to 211 together with the output from each register described later. Outputs from the registers 211 are (M0) 212 and (M1) 21
3, (A0) 214 and (A1) 215.

Registers (M0) 212, (M1) 213
Stores the data in the middle of the operation supplied to the multiplier 216, and the registers (A 0) 214 and (A 1) 215 store the data in the middle of the operation supplied to the adder / subtractor 217.

The output of the register (M1) 213 and the output of a register (SR) 224 described later are connected to the gate 2
18 to the multiplier 216. Further, the output of the register (A0) 214 and the output of the register (MR) 221 described later are input to the adder / subtractor 217 via the gate 219, and the output of the register (AI) 215 and the output of the register (AR) 222 described later. Output is gate 2
The signal is input to the adder / subtractor 217 via the line 20.

The result of the multiplication by the multiplier 216 is stored in a register (M
R) 221, and the output of the register (MR) 221 is supplied to the gate 209 and the gate 219. The operation result of the adder / subtractor 217 is stored in a register (AR) 22.
2 and the output of the register (AR) 222 is supplied to the register (SR) 224 via a clipper circuit 223 for preventing overflow (overflow).
The output F of the sign bit of the register (AR) 222
(AR) is given to the control circuit 202.

The output of the register (SR) 224 is
The calculation result of the sound processing is stored in the work memory (W) 204 via the internal bus 207. When the above calculation result is stored in the work memory (W) 204 and a series of processing is completed, the data stored in the memory becomes
The data is transferred to the output register (OR) 225 and output from the register to the DA converter 23 in FIG.

Next, the DSP 22 having the configuration shown in FIG.
Will be described with reference to the operation flowcharts of FIGS. These operations are performed in DS
P22 is realized as a process of executing a microprogram stored in the program memory 201.

In each operation flowchart, for example, W
(INP) indicates the contents of data (variable or constant) stored in the work memory (W) 204 in FIG. 5 and having a name of INP. Similarly, for example, W (ZR0), P (CE
0) are stored in the work memory (W) 204 and the coefficient memory (P) 203 in FIG.
Shall indicate the contents of the data. Here, the addresses, names and contents of the coefficients (constants) or variables stored in each memory on each memory are shown in FIG. 6 and FIG.

FIG. 8 is a general flowchart. The processing of each step will be described briefly with reference to FIGS. In FIG. 8, first, an input process for temporarily storing input musical tone waveform data is performed (step S81). Subsequently, a series of envelopes for generating the absolute value of the input processed tone waveform data, smoothing the absolute-valued waveform data, and generating three coefficients based on the level of the smoothed waveform data. The processing is performed (step S82). Next, a phase shifter process for changing the phase of the input musical tone waveform data using the coefficients generated from the envelope is performed (step S83). Then, high-pass filter processing for removing the low-frequency component of the phase-shifted waveform data is performed (step S
84). Subsequently, a process of mixing the high-pass filtered waveform data and the input musical tone waveform data at a mixing ratio determined based on the coefficients generated from the above-described envelope is performed (step S85). Then, the mixed musical sound waveform data is output (step S8).
6).

FIG. 9 is a flowchart of the above input processing. In the figure, an input tone signal is stored in a register (P
I) is input to the work memory (W) 204 from the register (PI) 206 and is input to the work memory (W) 204.
Is output (step S901).

Thus, the input musical sound data W (INP)
Are stored in the work memory (W) 204 of the DSP 22 in FIG. Next, FIGS. 10 to 12 are flowcharts of the envelope extraction processing of FIG. Note that constants and the like are also read from the RAM 26 in FIG.
2 and stored in advance.

In FIG. 10, first, a constant W (ZR0) is read from the work memory (W) 204 and stored in the register (A0) 214, and further, the input musical sound data W (INP) is read. Register (A1) 21
5 (step S101).

Subsequently, the constant "0" of the register (A0) 214 is subtracted from the input musical sound data W (INP) of the register (A1) 215, and the result is stored in the register (AR) 222.
Is stored in Thereby, the register (A1) 215
Is input to the register (AR) 222 as it is without changing the value. Although not specifically shown, the most significant bit information F (AR) of the data obtained in the register (AR) 222 at this time is given to the control circuit 202 as code flag data (step S10).
2). Thereby, processing equivalent to the function of the adder / subtractor 301 in FIG. 3 is realized.

Next, the constant W (ZR0) is read out again from the work memory (W) 204, and is read from the register (A1) 2.
15 and the input tone data W (INP) is also read out and stored in the register (A0) 214 (similarly, step S102).

Subsequently, the code flag data F (AR) given to the control circuit 202 in step S102 is "1", that is, the value of the input musical sound data W (INP) obtained in the register (AR) 222 is negative. Is determined (step S103). Thereby, processing equivalent to the function of the positive / negative detector 304 in FIG. 3 is realized.

In step S103, if the sign flag data F (AR) is "0", the input tone data W (IN
The value of P) is positive, in this case the register (A1) 2
The register (A0) is added to the constant “0” held in
The input musical tone data W (INP) held in 214 is added, and as a result, the input musical tone data W (INP) is directly stored in the register (AR) 222 (step S104). Thereby, processing equivalent to the function of the adder / subtractor 302 in FIG. 3 is realized.

If the sign flag data F (AR) is "1" in step S103, in this case, the register (A1) 215 is changed from the constant "0" to the register (A).
0) The input tone data W (INP) of 214 is subtracted,
As a result, the value of the input musical sound data W (INP) is converted from negative to positive and stored in the register (AR) 222 (step S105). Thereby, the adder / subtractor 303 in FIG.
Is realized.

Subsequent to step S104 or S105, the input tone data W (INP) obtained by converting all the values obtained in the register (AR) 222 into positive values is transferred to the register (SR) 224 (step S104). S106) Further, the work memory (W) 2 output from the register (SR) 224 as full-wave rectified waveform data W (EP0)
04 (step S107).

Thus, the input musical sound data W (INP)
Are rectified to positive values every sample, and are written to the work memory (W) 204 as full-wave rectified waveform data W (EP0).

Subsequently, the first low-pass filter coefficient P (CE0) is read from the coefficient memory (P) 203, stored in the register (M0) 212, and further read from the work memory (W) 204. The full-wave rectified waveform data W (EP0) is read out, and the register (M1) 21
3 (hereinafter, step S108 in the flowchart of FIG. 11).

Next, the register (M1) 213 is added to the low-pass filter coefficient P (CE0) of the register (M0) 212.
Is multiplied by the full-wave rectified waveform data W (EP0), and the result of the multiplication is stored in the register (MR) 221 (step S109). Thereby, processing equivalent to the function of the multiplier 307 in FIG. 3 is realized.

Subsequently, the low-pass filter delay output data W (CL0) is read from the work memory (W) 204 and stored in the register (M1) 213 (same as step S109). Thereby, the one-sample delay unit (Z
^-1 ) Processing equivalent to the output function of 310 is realized.

Subsequently, the coefficient memory (P) 203
, The second low-pass filter coefficient P (CE1) is read out, and stored in the register (M0) 212 (also step S109).

Then, the multiplication result obtained in the register (MR) 221 is transferred to the register (AR) 222, and the second low-pass filter coefficient P (CE 1) of the register (M 0) 212 and the register (M 1) 213 is multiplied by the low-pass filter delay output data W (CL0), and the multiplication result is stored in the register (MR) 221 (step S110). Thereby, the multiplier 3 of FIG.
Processing equivalent to the function 09 is realized.

Next, again, the work memory (W) 204
, The low-pass filter delay output data W (CL0) is read out, stored in the register (M1) 213, and the third low-pass filter coefficient P (CE2) is read out from the coefficient memory (P) 203, M0) 2
12 (also step S110).

The result of multiplication of the second low-pass filter coefficient P (CE1) obtained by the register (MR) 221 and the low-pass filter delay output data W (CL0) is transferred to the register (AR) 222. The multiplication result of the first low-pass filter coefficient P (CE0) and the full-wave rectified waveform data W (EP0) is added, and the addition result is stored in the register (AR) 222 (step S11).
1). Thereby, processing equivalent to the function of the adder 308 in FIG. 3 is realized.

Subsequently, the third low-pass filter coefficient P (CE2) of the register (M0) 212 and the register (M1)
213 low-pass filter delay output data W (CL0)
And the result of the multiplication is stored in a register (MR) 221.
(Also in step S111). Thereby, processing equivalent to the function of the multiplier 312 in FIG. 3 is realized.

Next, the contents obtained in the register (AR) 222 in step S111 are stored in the register (SR).
224 and the register (MR) 221
Of the third low-pass filter coefficient P (CE
2) is added to the result of multiplication of the low-pass filter delay output data W (CL0), and the content held in the register (AR) 222 is added.
22 (step S112). Thereby, processing equivalent to the function of the adder 311 in FIG. 3 is realized.

Subsequently, the content obtained in step S111 held in the register (SR) 224 is the low-pass filter delay output data W (CL) for the next sample.
0) is written to the work memory (W) 204 (step S113). Thereby, processing equivalent to the data capturing function of the one-sample delay unit (Z ⁻¹ ) 310 in FIG. 3 is realized.

The contents obtained in the register (AR) 222 are output to the register (SR) 224, and output from the register (SR) 224 to the work memory (W) 204 as low-pass filter output data W (CL1). Is performed (step S114).

Thus, full-wave rectified waveform data W (EP
0), the envelope of the input tone data W (INP) is obtained, and this is the low-pass filter output data W (CL).
1) is stored in the work memory (W) 204.

Subsequently, the first envelope coefficient P
(CE3) is stored in the register (M0) 212, and the low-pass filter output data W (CL1) is stored in the register (M0).
1) Stored in 213 (hereinafter, the flowchart of FIG. 12, step S115).

Next, the first offset data W (OF
0) is stored in the register (A1) 215, and the first envelope coefficient P (CE3) of the register (M0) 212 is stored.
Is multiplied by the low-pass filter output data W (CL1) of the register (M1) 213, and the result of the multiplication is given to the register (MR) 221 (step S116). Thereby, processing equivalent to the function of the multiplier 313 in FIG. 3 is realized.

Subsequently, the low-pass filter output data W (CL1) is written into the register (M1) 213 again.
This time, the second envelope coefficient P (CE4) is written to the register (M0) 212 (also in step S11).
6).

Next, from the first offset data W (OF0) of the register (A1) 215, the register (MR) 2
21, the first envelope coefficient P (CE
3) is subtracted from the multiplication result of the low-pass filter output data W (CL1), and the subtraction result is stored in the register (AR) 2
22 (step S117). This allows
Processing equivalent to the function of the adder / subtractor 316 in FIG. 3 is realized.

Further, the second envelope coefficient P (CE4) of the register (M0) 212 and the register (M0)
1) Low-pass filter output data W (CL1) of 213
And the result of the multiplication is stored in a register (MR) 221.
(Also step S117). Thereby, processing equivalent to the function of the multiplier 314 in FIG. 3 is realized.

Next, the second offset data W (OF)
1) is stored in the register (A1) 215, the low-pass filter output data W (CL1) is stored in the register (M1) 213, and the third envelope coefficient P (CE5) is stored in the register (M0) 212 (also in the step). S11
7).

Subsequently, the content obtained in the register (AR) 222 is transferred to the register (SR) 224, and the second envelope coefficient P (CE4) obtained in the register (MR) 221 and the low-pass The result of the multiplication with the filter output data W (CL1) is added to the register (A1) 21
The second offset data W (OF1) of No. 5 is added, and the addition result is stored in the register (AR) 222 (step S118). Thereby, the adder / subtractor 3 in FIG.
Processing equivalent to the seventeenth function is realized.

Subsequently, the third value of the register (M0) 212
Envelope coefficient P (CE5) and register (M1) 2
The low-pass filter output data W (CL1) of No. 13 is multiplied, and the multiplication result is written into the register (MR) 221 (also step S118). Thereby, processing equivalent to the function of the multiplier 315 in FIG. 3 is realized.

Next, the third offset data W (OF2) is stored in the register (A1) 215 (step S118). Then, the register (S
R) 224 is output to the data bus 207 and stored in the work memory (W) 204 as first envelope data W (EV0). Then, the content of the register (AR) 222 is transferred to the register (SR) 224, and the multiplication of the third envelope coefficient P (CE5) obtained in the register (MR) 221 and the low-pass filter output data W (CL1) is performed. In the result, register (A1)
215 is added to the third offset data W (OF2), and the addition result is stored in the register (AR) 222 (step S119). Thus, processing equivalent to the function of the adder / subtractor 318 in FIG. 3 is realized.

Next, the contents transferred to the register (SR) 224 are output to the data bus 207, and are used as the second envelope data W (EV1) as the work memory (W).
204. Further, a register (AR) 222
Is transferred to the register (SR) 224 (step S120).

Then, the transferred contents are output from register (SR) 224 to data bus 207,
Is stored in the work memory (W) 204 as the envelope data W (EV2) (step S121).

Thus, the input tone data W (INP)
Low-pass filter output data W (CL
1), three types of envelope data W (EV
0), W (EV1) and W (EV2) are generated and stored at predetermined addresses of the work memory (W) 204 (see FIG. 7).

Next, the phase shifter process of FIG. 8 will be described with reference to the flowchart of FIG. In the figure, first, the envelope data W (EV0) is stored in the register (M0) 212, and further the delay data T (PH) read from the delay memory (E) 105.
0) is stored in the register (M1) 213 (step S1301). Thereby, the m-th order sample delay unit (Z
^-m ) Processing equivalent to the output function of 321 is realized.

Subsequently, the envelope data W (EV0) of the register (M0) 212 is multiplied by the delay data T (PH0) of the register (M1) 213, and the result of the multiplication is stored in the register (MR) 221. (Step S1
302). Thereby, processing equivalent to the function of the multiplier 323 in FIG. 3 is realized.

Next, the input musical tone data W (INP) is stored in the register (A1) 215 (also in step S1).
1302). Then, the content obtained in the register (MR) 221 is added to the input musical sound data W (INP) in the register (A1) 215, and the addition result is stored in the register (AR) 222 (step S1303).
Thereby, processing equivalent to the function of the adder 319 in FIG. 3 is realized.

The contents stored in the register (AR) 222 are transferred to the register (SR) 224 (step S1304). Then, the transferred content is stored in the register (SR) 22 as the next delay data T (PH1).
4 through a data bus 207 to a work memory (W) 2
04 (step S1305). As a result, processing equivalent to the data capturing function of the m-th order sample delay unit (Z- ^m ) 321 in FIG. 3 is realized.

The delay data T (PH1) of the register (SR) 224 is also stored in the register (M1) 213, and the envelope data W (EV)
0) is stored in the register (M0) 212 (step S1306).

Next, the envelope data W (EV0) of the register (M0) 212 and the register (M1) 213
Is multiplied by the delay data T (PH1), and the multiplication result is stored in the register (MR) 221 (step S).
1307). Thereby, processing equivalent to the function of the multiplier 320 in FIG. 3 is realized.

Subsequently, the delay data T (PH1) is read out from the delay memory (E) 105 and is read from the register (A).
1) is stored in 215 (also in step S130)
7). Then, the content obtained in the register (MR) 221 is subtracted from the delay data T (PH1) in the register (A1) 215, and the subtraction result is stored in the register (AR).
222 (step S1308). Thereby, processing equivalent to the function of the adder / subtractor 322 in FIG. 3 is realized.

The contents obtained in the register (AR) 222 are transferred to the register (SR) 224 (Step S).
1309) Then, the data is output as all-pass output data W (AP0) from the register (SR) 224 and written into the work memory (W) 204 (step S13).
10).

As a result, the input musical sound data W (INP)
Are phase-shifted according to the envelope data W (EV0) and have waveform variation components added thereto, and the all-pass output data W
It is stored in the work memory (W) 204 as (AP0).

Next, the high-pass filtering processing of FIG. 8 will be described with reference to the flowchart of FIG.
First, the first high-pass filter coefficient P (KE0) is read from the coefficient memory (P) 203, and the register (M
0) 212 and further stored in the work memory (W) 2
04, the above-mentioned all-pass output data W (AP0) is read and stored in the register (M1) 213 (step S1401).

Next, the register (M1) is added to the first high-pass filter coefficient P (KE0) of the register (M0) 212.
213 is multiplied by the all-pass output data W (AP0), and the multiplication result is stored in the register (MR) 221 (step S1402). Thereby, processing equivalent to the function of the multiplier 324 in FIG. 3 is realized.

Subsequently, the high-pass filter delay output data W (FL0) is read out from the work memory (W) 204 and stored in the register (M1) 213 (similarly, step S1402). Thus, processing equivalent to the output function of one-sample delay unit (Z ⁻¹ ) 326 in FIG. 3 is realized.

Subsequently, the coefficient memory (P) 203
, The second high-pass filter coefficient P (KE1) is read out, and stored in the register (M0) 212 (similarly, step S1402).

The multiplication result obtained in the register (MR) 221 is transferred to the register (AR) 222, and the second high-pass filter coefficient P (KE1) of the register (M0) 212 and the register (M1) 213 is multiplied by the high-pass filter delay output data W (FL0), and the multiplication result is stored in the register (MR) 221 (step S1403). Thereby, processing equivalent to the function of the multiplier 328 in FIG. 3 is realized.

Next, again, the work memory (W) 204
, The high-pass filter delay output data W (FL0) is read out, stored in the register (M1) 213, and the third high-pass filter coefficient P (KE2) is read out from the coefficient memory (P) 203. M0) 2
12 (also step S1403).

Then, the second high-pass filter coefficient P
(KE1) and the high-pass filter delay output data W (FL
0) and the contents obtained in the register (MR) 221 and the first high-pass filter coefficient P (KE
0) and the result obtained by multiplying the all-pass output data W (AP0) and transferred to the register (AR) 222 are added, and the addition result is added to the register (AR) 22.
2 (step S1404). This allows
Processing equivalent to the function of the adder 325 in FIG. 3 is realized.

Subsequently, the third high-pass filter coefficient P (KE2) of the register (M0) 212 and the register (M1)
213 high-pass filter delay output data W (FL0)
And the result of the multiplication is stored in a register (MR) 221.
(Similarly, step S1404). Thereby, processing equivalent to the function of the multiplier 329 in FIG. 3 is realized.

Next, the contents obtained in the register (AR) 222 are transferred to the register (SR) 224, and the contents held in the register (AR) 222 are obtained in the register (MR) 221. The multiplication result of the third high-pass filter coefficient P (KE2) and the high-pass filter delay output data W (FL0) is added, and the addition result is stored in the register (AR) 222 (step S1405). Thereby, processing equivalent to the function of the adder 327 in FIG. 3 is realized.

Subsequently, the contents transferred to the register (SR) 224 are stored in the work memory (W) 2 as the high-pass filter delay output data W (FL0) for the next sample.
04 (step S1406). Thus, processing equivalent to the data capturing function of the one-sample delay unit (Z ^-1 ) 326 in FIG. 3 is realized.

Then, the contents obtained in the register (AR) 222 are output to the register (SR) 224 (also in step S1406), and the contents of the register (SR) 224 are output.
Is output to the work memory (W) 204 as high-pass filter output data W (FL1) (step S14).
07).

As a result, data obtained by removing a predetermined low-frequency component from the input all-pass output data W (AP0) becomes high-pass filter output data W (AP0).
(FL1) is stored in the work memory (W) 204.

Next, the mixing process of FIG. 8 will be described with reference to the flowchart of FIG. In the figure, first, the second envelope data W (EV1) is read from the work memory (W) 204, and the register (M0) 2
12 and furthermore, the input tone data W (INP)
Is read and stored in the register (M1) 213 (step S1501).

Next, the second envelope data W (EV1) of the register (M0) 212 and the register (M1) 2
The result is multiplied by the input musical sound data W (INP) of thirteen, and the multiplication result is stored in the register (MR) 221 (step S1502). Thereby, processing equivalent to the function of the multiplier 330 in FIG. 3 is realized.

Subsequently, from the work memory (W) 204,
The high-pass filter output data W (FL1) is read and stored in the register (M1) 213, and the third envelope data W (EV2) is read and stored in the register (M0) 212 (similarly). Step S
1502).

Then, the multiplication result obtained in the register (MR) 221 is transferred to the register (AR) 222, and the third envelope data W (EV2) of the register (M0) 212 and the register (M1) 213 Is multiplied by the high-pass filter output data W (FL1), and the multiplication result is stored in the register (MR) 221 (step S1503). Thereby, the multiplier 331 of FIG.
Is realized.

Next, the contents of the register (MR) 221 are transferred to the register (AR) 222 as a result of multiplication of the second envelope data W (EV1) and the input musical sound data W (INP). The contents are added,
The addition result is stored in the register (AR) 222 (step S1504). Thereby, the adder 3 of FIG.
The processing equivalent to the function of 33 is realized.

The result obtained in the register (AR) 222 is transferred to the register (SR) 224,
224 is written into the work memory (W) 204 as output waveform data W (MIX) (step S150)
6).

Next, the output processing of FIG. 8 will be described with reference to the flowchart of FIG. The output waveform data W (M) once stored in the work memory (W) 204 as described above
IX) is read out by the control circuit 202 and transferred to the register (OR) 225 (step S160).
1), from this register (OR) 225, the DA converter 23
Is output to

In this embodiment, the input tone data W
(INP) is obtained from the envelope of the input musical sound data W (INP), but is not limited to the envelope. For example, LFO (low freq)
A coefficient can be calculated using an output from a uency oscillator or the like.

[0136]

According to the present invention, the high-frequency range is changed while varying the phase of the input musical tone to be modulated and the mixing ratio of the shifted musical tone and the original musical tone according to the input level of the original musical tone. Overtones can be emphasized.

Therefore, it is possible to obtain a sharp effect of high frequency overtones that slightly change in accordance with the strength of the performance operation, thereby obtaining a sense of unity between the performance operation and the effect sound.
More realistic and comfortable performances can be added.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of an electronic stringed musical instrument according to an embodiment.

FIG. 2 is a block diagram illustrating an internal configuration of an electronic circuit unit.

FIG. 3 is a functional block diagram of the present invention.

FIG. 4 is a phase characteristic diagram of an all-pass filter.

FIG. 5 is a configuration diagram of a DSP.

FIG. 6 is a diagram showing an internal configuration of a coefficient memory (P).

FIG. 7 is a diagram showing an internal configuration of a work memory (W).

FIG. 8 is a general flowchart showing the operation of the DSP.

FIG. 9 is a flowchart of a DSP input process.

FIG. 10 is a flowchart (part 1) of an envelope extraction process of the DSP.

FIG. 11 is a flowchart (part 2) of an envelope extraction process of the DSP.

FIG. 12 is a flowchart (part 3) of an envelope extraction process of the DSP.

FIG. 13 is a flowchart of a phase shifter process of the DSP.

FIG. 14 is a flowchart of a high-pass filter process of the DSP.

FIG. 15 is a flowchart of a mixing process of the DSP.

FIG. 16 is a flowchart of a DSP output process.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Pickup 2 Differential amplifier 3 Electronic part 4 Sound source 5 Variable resistor for volume 6 Output jack 21 Analog / digital converter (AD) 22 Digital signal processor (DSP) 23 Digital / analog converter (DA) 24 CPU (central Arithmetic processing unit) 25 ROM (read only memory) 26 RAM (random access memory) 3-1 Envelope extraction processing block of input tone signal 3-2 Phase shift processing block for input tone signal 3-3 Phase shift processing High-pass filtering processing block for input tone signal 3-4 Mixing processing block of input tone signal and tone signal subjected to high-pass filtering processing

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G10H 1/06-1/16 G10H 1/00 G10H 1/053 G10H 3/00-3/26 G10K 15/04 302

Claims (3)

(57) [Claims] 1. A phase varying means for adding a change to the phase of an input audio signal and outputting the same, a level detection means for detecting an input level of the input audio signal, and a detection signal from the level detection means. Phase control means for varying the degree of phase shift of the output signal from the phase variable means, filtering means for subjecting the signal from the phase variable means to high-pass filtering and outputting, and a signal from the filtering means and the input. Mixing means for mixing and outputting the received audio signal, and a mixing ratio of the input audio signal mixed with the mixing means and the signal from the filtering means based on the detection signal from the level detection means. And a mixing ratio control means for varying the mixing ratio. 2. The level detection means extracts a predetermined signal that changes smoothly with time from the input audio signal, and determines an input level of the input audio signal based on the extracted signal. The effect adding device according to claim 1, wherein the effect is detected. 3. A phase changing means for changing the phase of an input audio signal and outputting the same, extracting an envelope of the input audio signal, and extracting the envelope of the input audio signal based on the extracted envelope. Level detection means for detecting an input level; phase control means for varying a phase shift degree of an output signal from the phase variable means based on a detection signal from the level detection means; and a high-pass signal from the phase variable means. Filtering means for filtering and outputting; mixing means for mixing and outputting the signal from the filtering means and the input audio signal; and the input audio signal mixed by the mixing means and the filtering Mixing ratio control means for varying the mixing ratio with the signal from the means based on the detection signal from the level detection means; An effect adding device for an electronic musical instrument, comprising: