JP3115527B2 - Semiconductor surface patterning method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for patterning a semiconductor surface for forming a periodic pattern on a surface of a semiconductor substrate.

[0002]

2. Description of the Related Art Conventionally, in the field of semiconductor manufacturing, a photo-etching process (PEP) has been employed to form a fine pattern on a substrate surface. In this PEP, a photoresist is applied on a substrate, the resist is exposed and patterned by light or an electron beam, and the substrate is selectively etched or selectively grown using the photoresist as a mask.

However, this type of method requires a high-level exposure technique and requires many steps. Further, the minimum processing dimension is at most about 50 nm. Therefore, realization of a technique for forming a pattern of a finer size with a simple process is demanded.

[0004]

As described above, the conventional PE
In the fine processing technology using P, the minimum processing size is about 50 nm in addition to the complexity of the process, and there is a demand for a fine processing technology with a finer minimum processing size.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor surface capable of forming a finer pattern without requiring a complicated process such as PEP. Is to provide a patterning method.

[0006]

[Means for Solving the Problems]

(Summary) In order to solve the above problems, the present invention employs the following configuration. That is, the present invention provides a semiconductor surface patterning method for forming a periodic pattern on a surface of a semiconductor substrate, wherein gallium is deposited on a surface of a silicon substrate having periodic atomic steps, and a part thereof is heated and evaporated. Forming a periodically arranged gallium adsorption region and a gallium desorption region, and then supplying oxygen gas to the substrate surface to oxidize the gallium adsorption region and the gallium desorption region. The method includes a step of performing heat treatment to form a silicon oxide coating layer periodically, and a step of performing heat treatment after depositing silicon on the surface of the substrate to desorb silicon oxide. (Operation) According to the present invention, a silicon oxide layer having a uniform width and thickness can be formed periodically or locally. Periodic pattern formation can be obtained using a silicon substrate obtained by cutting a silicon single crystal at a slight inclination from a low index plane. According to this method, a periodic pattern having a fine pitch that cannot be formed by the conventional PEP can be formed.

[0007] Silicon oxide can serve as a mask for various silicon micromachining processes. When silicon or the like is grown by a gas source molecular beam epitaxial growth (GSMBE) method or a chemical vapor deposition (CVD) method, the silicon is selectively grown only on silicon without growing on silicon oxide. Also serves as a growth mask.

Accordingly, various semiconductor elements can be manufactured by performing selective etching and selective growth utilizing this. In the case of removing silicon oxide, the silicon oxide film can be removed by heating a silicon thin film of several atomic layers after volume.

As described above, according to the present invention, fine processing can be performed in a small number of steps without using an advanced exposure technique. In addition, by adjusting the atomic step interval, fine processing on a nanometer scale of 50 nm or less can be easily performed.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing the embodiments of the present invention, the basic principle of the present invention will be described. The atomic step interval on the silicon (Si) substrate surface can be freely controlled from a size of 10 nm or less to a size on the order of microns. Here, the atomic step is
It means a step of a monoatomic layer, and a flat surface (called a terrace) at an atomic level is formed between atomic steps. For example, if a substrate (off-substrate) slightly inclined from the low index plane is used, atomic steps with a pitch of 10 nm or less can be formed uniformly.

In addition, after periodically patterning with a photoresist, etching is performed to form holes periodically, and when heated to a temperature at which the atomic steps move, step bunching occurs, and the atomic steps are pinned at the holes. It is also known that uniform and periodic atomic steps are formed in a wide range [Reference: Proceedings of the 55th Annual Conference of the Japan Society of Applied Physics, Scientific Supporting Committee, Vol.
7].

By using the thus-formed substrate having the atomic steps uniformly arranged and using a chemical reaction formed along the ends of the atomic steps, the surface can be processed to a size of 10 nm or less. As a chemical reaction formed along an atomic step edge, a phenomenon in which a Ga adsorbed substance is desorbed from a step edge when a Si (111) surface on which Ga is adsorbed is heated to 650 ° C. is known. ： H.Nakahara and
M. Ichikawa, AppliedPhysics Letters vol. 61, p.153
1 (1992)]. This process results in a surface structure in which the Ga adsorption surface 11 and the Si surface 12 are alternately arranged on the same terrace along the atomic steps as shown in FIG.

After exposing the substrate surface to oxygen gas,
When heated at about 700 ° C., as shown in FIG.
Due to the difference in vapor pressure between the oxide and the Si oxide, the Ga oxide is selectively desorbed, and the Si oxide 13 is formed along the steps. That is, a surface structure is formed in which the Si oxides 13 and the Si surfaces 12 are alternately arranged on the same terrace along the atomic steps. The width of the formed Si oxide is determined by the process of desorbing the Ga adsorbate before exposure to oxygen gas.
It can be controlled by the substrate heating time. Further, the thickness of the Si oxide can be controlled by the oxygen gas exposure time. In addition,
When the Si substrate 10 is heated to 400 ° C. during exposure to oxygen gas, the oxidation efficiency increases.

The Si oxide thus formed is
It can be used as a mask in a silicon micromachining process. In this case, since the thickness is on the order of several angstroms, there is no mask blur caused by the presence of the thickness. Further, the GSMBE method or the CVD method
It can also be used as a mask for selective growth when growing such as. Therefore, extremely fine processing can be performed in a small number of steps without using an advanced exposure technique.

Next, a method for removing the Si oxide and forming a fine structure will be described. After depositing Si on the Si oxide 21 as shown in FIG.
When the substrate 20 is heated to about 800 ° C., the Si oxide 21 and S
Since Si atoms are excessively present at the interface of the i deposition layer 22, SiO is formed at this portion. SiO is SiO ₂
Since the vapor pressure is higher than that of the Si oxide mainly composed of Si, desorption proceeds selectively from the interface, and the Si oxide in the Si deposited layer 22 is finally removed. Si substrate 2
By depositing Si on the entire surface of the substrate 0 and then heating the substrate, as shown in FIG. 2 (b), the Si oxide region evaporates to a depth of about 1 nm periodically arranged on the substrate surface. Grooves 23 are formed.

The periodic uneven structure having the dimensional accuracy of several angstrom level formed as described above can be used as a substrate for forming a silicon fine structure.
In this case, a highly accurate semiconductor element can be manufactured without generating defects induced by a normal etching process.

Hereinafter, embodiments of the present invention will be described. (First Embodiment) FIG. 3 is a perspective view showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention, and particularly shows an example of a light emitting diode. First, clean p-type Si (11
1) After adsorbing Ga on the vicinal substrate 30, the substrate surface is heated to 650 ° C. to obtain a substrate surface in which Ga adsorption surfaces and Si surfaces are alternately arranged on the same terrace along the atomic steps. The width of the desorption region on the Ga adsorption surface is set to 5 nm by controlling the substrate heating time. Next, the substrate is exposed to an oxygen gas of 5 × 10 ⁻⁵ Pa while being heated to 400 ° C. Subsequently, by heating the substrate at 700 ° C. for 10 minutes, the Si clean surface as shown in FIG.
A structure in which oxides are alternately arranged along steps is obtained. The width of the Si oxide is about 5 nm.

Next, when disilane and diborane are supplied by the CVD method to grow p-type Si, the silicon does not grow on the Si oxide but grows only on the Si. When the growth is completed when the thickness reaches 5 nm, a p-type Si layer 32 having a width of 5 nm is formed as shown in FIG. The carriers confined in the fine wire are quantized, and the quantized electron energy level becomes larger than the band gap of Si.

Subsequently, disilane and phosphine are supplied by the CVD method to grow an n-type Si layer 33 on the p-type Si layer 32, thereby forming a pn junction quantum wire of silicon. Next, as shown in FIG. 3B, the space between the fine wires is filled with a silicon oxide film 34 by a plasma CVD method or the like, and a transparent electrode 35 is formed on the surface, whereby a light emitting diode can be formed. The emission wavelength of this light emitting diode is in the visible light range due to the quantum size effect.

(Second Embodiment) FIG. 4 shows a second embodiment of the present invention.
FIG. 5 is a perspective view illustrating a manufacturing process of the semiconductor device according to the embodiment, and particularly illustrates an example of manufacturing a quantum wire. A groove 41 as shown in FIG. 4A is formed by the same process as shown in FIG. As shown in the first embodiment, a clean Si (111) vicinal Si substrate 40 in which the width of the atomic steps is uniformly set to 10 nm, and a 5 nm wide S
The width of the groove 41 is reduced to 5 nm by forming the i-oxide film.
Can be controlled. Further, the depth of the groove 41 can be controlled with an accuracy of 3.1 angstrom thickness of the atomic layer on the Si (111) plane by the thickness of the Si layer to be deposited.

On this substrate 40, a 1.2 nm thick S
By alternately laminating the iGe layers 42 and the Si layers 43, the SiGe layers arranged in a lattice as shown in FIG.
Fine wires can be produced. In a quantum wire having such a structure, electrons and holes are confined in a two-dimensional direction,
In addition, since a good interface is formed, a highly efficient semiconductor element can be obtained by using it as an active layer of a light emitting device or a conductive layer of an electronic device. In the above-described embodiment, an example in which a SiGe mixed crystal having a smaller band gap than Si is used as a material for forming a quantum well is described. However, the material is not limited to SiGe. GaSb in quantum well
Similar effects can be obtained by using such a compound semiconductor.

(Third Embodiment) FIG. 5 shows a third embodiment of the present invention.
FIG. 21 is a perspective view showing a manufacturing step of the semiconductor element according to the embodiment. First, a semi-insulating Si (100) S
The i-substrate 50 is heated in an ultra-high vacuum to obtain a clean surface in which the intervals between the atomic steps are uniform at 10 nm. Then G
After adsorbing a, the width of the Ga desorption region is set to 5 nm by controlling the substrate heating time. The substrate is exposed to an oxygen gas of 5 × 10 ⁻⁵ Pa while being heated to 400 ° C. Subsequently, by heating the substrate at 700 ° C. for 10 minutes,
As shown in FIG. 1, a structure is obtained in which Si clean surfaces and Si oxides are alternately arranged along steps. The width of the Si oxide is about 5 nm.

Next, after depositing a Si thin film having a thickness of about 3 Å on the Si substrate 50, a Ge thin film is deposited. Next, by heating the substrate at about 800 ° C., the region of the Si oxide is removed by the same process as described with reference to FIG. 2, and SiGe is formed in the region of the clean Si surface. Finally, as shown in FIG. 5A, a fine line structure of the SiGe layer 51 having a width of 5 nm periodically arranged on the substrate surface is formed.

Next, Si is epitaxially grown, and this SiGe thin wire (SiGe layer 51) is
As shown in FIG. 5B, SiGe quantum wires that are periodically arranged are formed. A highly efficient semiconductor element can be obtained by using the quantum wire having such a structure as an active layer of a light emitting device or a conductive layer of an electronic device, as in the case of FIG. 4B.

When the structure shown in FIG. 5A is formed, Ge is deposited after depositing Si. However, Ge may be deposited directly on Si oxide without depositing Si. A similar structure can be made. However, in this case, a quantum wire of Ge is formed instead of SiGe.

The present invention is not limited to the above embodiments. In the embodiment, the temperature at which the oxygen gas is adsorbed is 400 ° C., but the temperature is not limited to 400 ° C., and it may be about 600 ° C. or less at which gallium desorption occurs. Further, the case where the gallium adsorption surface has an adsorption amount of 1/3 molecular layer (1 molecular layer = 7.8 × 10 ¹⁴ atoms / cm ² ) has been described, but may be 1/3 molecular layer or more.

[0027]

As described above in detail, according to the present invention, after supplying oxygen gas to the surface of a silicon substrate having a gallium adsorption surface at a predetermined position, the substrate is subjected to a heat treatment, whereby the silicon substrate is heated. A silicon oxide layer can be formed at a predetermined position on the surface. Therefore, fine processing of the substrate surface can be performed in a small number of steps without using an advanced exposure technique.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a substrate surface processing step for explaining a basic principle of the present invention.

FIG. 2 is a perspective view showing a substrate surface processing step for explaining the basic principle of the present invention.

FIG. 3 is a schematic view illustrating a manufacturing process of the semiconductor device according to the first embodiment.

FIG. 4 is a perspective view showing a manufacturing process of a semiconductor device according to a second embodiment.

FIG. 5 is a perspective view showing a manufacturing process of a semiconductor device according to a third embodiment.

[Explanation of symbols]

10, 20, 30, 40, 50 silicon substrates, 11
Gallium adsorption surface, 12 silicon surface, 13, 21, 31
Silicon oxide, 22 silicon deposition layer, 23, 41
Groove, 32 p-type silicon layer, 33 n-type silicon layer, 3
4 silicon oxide film, 35 electrodes, 42,51 SiG
e layer (quantum wire), 43,52 Si layer.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shigemitsu Maruno 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Inside Mitsubishi Electric Corporation (72) Inventor Shinobu Fujita 1-1-1, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Shares (72) Inventor Heiji Watanabe 5-7-1 Shiba, Minato-ku, Tokyo NEC Corporation (72) Inventor Masakazu Ichikawa 1-1280 Higashi-Koigabo, Kokubunji-shi, Tokyo Hitachi, Ltd. Central In the laboratory (56) References JP-A-5-47659 (JP, A) JP-A-8-274024 (JP, A) JP-A-9-82939 (JP, A) JP-A-8-97152 (JP, A) ) Patent 2714703 (JP, B2) Patent 2831953 (JP, B2) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/316 H01L 21/20 H01L 21/203 H01L 21/205 H01L 29 / 06

Claims (7)

(57) [Claims] An oxygen gas is supplied to a surface of a silicon substrate having a gallium adsorption surface and a silicon surface so that a silicon oxide layer is formed only on the silicon surface.
A method of patterning a semiconductor surface, wherein the substrate is subjected to a heat treatment. A step of supplying oxygen gas to a surface of a silicon substrate having a gallium adsorption surface and a silicon surface, and then heating the substrate so that a silicon oxide layer is formed only on the silicon surface. And a step of subjecting the substrate to heat treatment so that only the silicon oxide layer is removed after crystal growth on the surface of the substrate. 3. A step of periodically arranging a gallium adsorption surface and a silicon surface on a surface of a silicon substrate having periodic atomic steps, and heating the substrate after supplying oxygen gas to the surface of the substrate. And a step of periodically forming a silicon surface and a silicon oxide layer on the surface of the substrate along the atomic steps. 4. A step of periodically arranging a gallium adsorption surface and a silicon surface on a surface of a silicon substrate having periodic atomic steps, and heating the substrate after supplying oxygen gas to the surface of the substrate. And periodically forming a silicon surface and a silicon oxide layer on the surface of the substrate along the atomic steps, and selectively growing a semiconductor layer on the surface of the substrate using the silicon oxide layer as a mask. A method for patterning a semiconductor surface, comprising: 5. A step of periodically arranging a gallium adsorption surface and a silicon surface on a surface of a silicon substrate having periodic atomic steps, and heating the substrate after supplying oxygen gas to the surface of the substrate. And periodically forming a silicon surface and a silicon oxide layer on the surface of the substrate along the atomic steps; and selectively etching the substrate using the silicon oxide layer as a mask to form a groove. ,
A method of patterning a semiconductor surface, comprising a step of selectively growing a semiconductor layer in a groove of the substrate. 6. A step of periodically arranging a gallium adsorption surface and a silicon surface on a surface of a silicon substrate having periodic atomic steps, and heating the substrate after supplying oxygen gas to the surface of the substrate. And periodically forming a silicon surface and a silicon oxide layer on the surface of the substrate along the atomic steps, and then, after crystal growth on the surface of the substrate, only the silicon oxide layer is removed. A method of patterning a semiconductor surface, the method comprising: heating the substrate and growing a semiconductor layer having periodic irregularities corresponding to the silicon oxide layer on the surface of the substrate. 7. A step of periodically arranging a gallium adsorption surface and a silicon surface on a surface of a silicon substrate having periodic atomic steps, and heating the substrate after supplying oxygen gas to the surface of the substrate. And periodically forming a silicon surface and a silicon oxide layer on the surface of the substrate along the atomic steps, and then, after crystal growth on the surface of the substrate, only the silicon oxide layer is removed. Heat treating the substrate to grow a semiconductor layer having periodic irregularities corresponding to the silicon oxide layer on the surface of the substrate, and then alternately growing a heterogeneous semiconductor layer on the substrate A method for patterning a semiconductor surface, comprising: