JP3114980B2 - Delay circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a digital signal delay circuit suitable for integration, in which a MOS field effect transistor current source charges a capacitor according to the state of a digital signal, or When a circuit configuration is used in which a ramp voltage is generated by discharging the accumulated charge and a delay time is set using the time until the ramp voltage reaches the threshold voltage of the logic circuit, manufacturing process fluctuations, power supply voltage fluctuations And a delay circuit in which delay time variation due to temperature variation is small.

<Prior Art> Digital circuits in the fields of personal computers, digital measuring instruments, and the like require a delay circuit for delaying a digital signal by a certain time in order to adjust the timing between control signals. Conventionally, as this type of delay circuit, LC
Many hybrid ICs with delay elements and input / output buffer logic gate ICs are used, but with the miniaturization, thinning, and price reduction of devices, it is strongly desired to realize delay circuits that can be monolithically integrated. It is rare.

This type of delay circuit, suitable for integration, generates a ramp voltage by charging or discharging a capacitor with a MOS field-effect transistor current source and uses the time it takes for this ramp voltage to reach the threshold voltage of the logic circuit. A circuit system that sets the delay time by using a delay time has been considered.

FIG. 14 shows a conventional delay circuit of this kind. 14th
In the figure, M ₁ is a first MOS field effect transistor, M ₂
Is a second MOS field-effect transistor, C is a capacitor, Q
₁ is a logic circuit, V _BIAS is a DC bias voltage, V _DD is a DC power supply voltage, V _IN is a digital input signal to be a delayed signal, V
_OUT is a delay signal provided as a logical output.

In the example shown, the first MOS field effect transistor M ₁ is formed of a P-channel device, along with a digital input signal V _IN is to be delayed signal is directed to the gate G _1, the source S ₁ is the power supply It is connected to a power supply line that supplies voltage _VDD .

Second MOS field effect transistor M ₂ is an N-channel device, with its drain D ₂ is connected in common to a drain D ₁ of the first MOS field effect transistor M _1, a source S ₂ is at ground It is connected to a certain power line. The gate G ₂ DC bias voltage V _BIAS is applied.

Capacitor C, the node a as a drain common connection point of the first and second MOS field effect transistors M ₁ and M ₂
And one of the power supply lines, the ground.

Logic circuit Q ₁ is, outputs a logical output corresponding to the accumulated charge amount of the capacitor C as a delay signal V _OUT. In the example of Figure 14 is a logic circuit Q ₁ is an inverter, the low level when the voltage level of the node a is higher than the threshold voltage V _TH, the high-level output respectively which when low.

FIG. 15 shows an example of operation waveforms of the delay circuit shown in FIG. In operation waveform example of Figure 15, when the digital input signal V _IN is at the low level, the first MOS field effect transistor M ₁ and the second MOS field effect transistor M ₂ are both serving as an active state. At this time, the voltage at the node a is the power supply voltage
V _DD is set between the first MOS field-effect transistor M ₁ and the second MOS
A divided by the value in a field effect transistor M _2. First
The ratio of the MOS field-effect transistor gate width W and the channel length L of the M ₁ (W / L) is a second MOS field effect transistor
If sufficiently large relative to that of M ₂ (since the first MOS field effect transistor the gate-source voltage of M ₁ is greater than that of the second MOS field effect transistor M _2), the node a
Is a high level (approximately V _DD ) as shown in FIG.
become.

In this state, as shown in FIG. 15 (a), when the digital input signal V _IN is at a high level at t _o, since the first MOS field effect transistor M ₁ is a cut-off state, stored in the capacitor C charge begins to be discharged through the second MOS field effect transistor M _2. Second MOS field effect transistor M ₂ is a direct current to the gate G ₂ bias voltage V
_BIAS is applied and its drain-source voltage V
_In a saturation region where the relationship between _DS , the gate-source voltage V _GSN (= V _BIAS ) and the threshold voltage V _TN satisfies the following condition: V _DS ≧ V _GSN −V _TN , the device operates as a fairly good constant current source. Therefore, when the digital input signal _VIN becomes high level, the voltage at the node a starts to decrease at a substantially constant slope as shown in FIG. 15 (b). Voltage at node a is monitored by the logic circuit Q _1, which is an inverter, the voltage crosses the threshold voltage V _TH of the inverters t ₁
At this time, the inverter output V _OUT changes from a low level to a high level as shown in FIG. 15 (c).

In the above operation, the time until the rising edge of the digital input signal V _IN is transmitted to the inverter output is the delay time Td. The delay time Td obtained by the conventional example of FIG. 14 is given by the following equation.

In _{Td = (V DD -V TH)} · C / I DN above equation, V _TH is the threshold voltage of the logic circuit Q _1, when the logic circuit Q ₁ is are composed of CMOS inverters given by: Can be

V _TH = (βV _DD + βV _TP + V _Tn ) / (1 + β) β = [(L _n · W _p · μ _p ) / (L _p · W _n · μ _n )] ^1/2 where V _Tn (positive ), L _n and W _n are each C
The threshold voltage, the channel length and the gate width of the N-channel element constituting the MOS inverter, μ _n are the mobilities of electrons which are carriers of the N-channel element, and V _Tp (negative value), L _p and W _p are , Respectively, the threshold voltage, the channel length and the gate width of the P-channel element constituting the CMOS inverter, and μ _p are the mobilities of holes serving as carriers of the P-channel element. As is clear from the above formula,
The threshold voltage V _TH depends on the power supply voltage V _DD . For example, β =
1. Assuming that V _Tn = | V _Tp |, V _TH = 0.5 V _DD .

In the above equation of the delay time Td, I _DN is the second M
The drain current of the OS field effect transistor M _2, approximately given by the following equation.

I _DN = (W _N / L _N ) (μ _{N Co} / 2) (V _GSN −V _TN ) ² where V _TN , L _N and W _N are the threshold values of the second MOS field effect transistor M ₂ , respectively. voltage, channel length and gate width, the mu _N electron mobility is the second carrier of the MOS field effect transistor M _2, is C _o is a gate capacitance per unit area of the second MOS field effect transistor M ₂ .

<Problem to be Solved by the Invention> However, the above-described conventional delay circuit has the following problems.

(A) As is clear from the above formula of the drain current I _DN , when the carrier mobility μ _N changes, the drain current I _{N
The DN} changes, and the delay time Td changes. Carrier mobility μ
_N changes in a direction to decrease as the temperature rises. For this reason, the delay circuit shown in FIG. 14 has a problem that the delay time Td becomes longer as the temperature rises.

As is apparent from the equation (b) supra threshold voltage V _TH, MOS
In the manufacturing process of the field-effect transistor, the channel lengths L _n , L _p , the gate widths W _n , W _p , of the N-channel device and the P-channel device are changed due to fluctuations in manufacturing process conditions.
When the mobility μ _n , μ _p , threshold voltage V _Tn , V _Tp, etc. change,
Accordingly, the threshold voltage _VTH of the CMOS inverter fluctuates. Further, as apparent from the equation of the drain current I _DN supra, in a manufacturing process of a MOS field-effect transistor,
When the channel length L _N , the gate width W _N , the gate capacitance C ₀ , and the threshold voltage V _TN change due to a change in the manufacturing process conditions, the drain current I _{DN of the second} MOS field-effect transistor M ₂ changes accordingly. I do. For this reason, there is a problem that the delay time Td fluctuates due to variations in the manufacturing process.

(C) As is apparent from the above expression of the delay time Td, the delay time Td is proportional to the DC power supply voltage V _DD and the value of the threshold voltage V _TH of the inverter (V _DD −V _TH ). When V _DD changes, there arises a problem that the delay time Td changes.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a delay circuit which solves the above-mentioned problems of the prior art, is suitable for integration, and has little delay time fluctuation due to manufacturing process fluctuation, temperature fluctuation and power supply voltage fluctuation. .

<Means for Solving the Problems> In order to solve the problems described above, the present invention provides a first MOS field effect transistor, a second MOS field effect transistor, an operational amplifier, a resistor, a capacitor, and a logic circuit. And a bias circuit, wherein the first MOS field-effect transistor has a gate to which a digital input signal as a delayed signal is guided,
A source is guided to one of the power supply lines, and the second MOS field-effect transistor has a drain guided to the drain of the first MOS field-effect transistor and a source connected to one of the power supply lines via the resistor. The operational amplifier includes an inverting input terminal, a non-inverting input terminal, and an output terminal, and the inverting input terminal is connected to the second MO.
The output terminal is connected to the source of the S field effect transistor, the output terminal is connected to the gate of the second MOS field effect transistor, and the capacitor is connected between the drain of the first MOS field effect transistor and a power supply line. The logic circuit has a threshold voltage, and converts the voltage between the terminals of the capacitor into a binary signal based on the threshold voltage,
A circuit for outputting a delay digital signal, wherein the bias means extracts an operational amplifier, a means for generating a temperature-insensitive voltage, a means for generating a voltage proportional to temperature, and a threshold voltage of the logic circuit Means, a voltage generating means, the voltage generating means, the non-inverting of the operational amplifier the DC voltage obtained by the operation of each voltage extracted or generated by each means, and the power supply voltage It is characterized in that it is given to the input terminal.

<Operation> The inverting input terminal of the operational amplifier is connected to the source of the second MOS field-effect transistor connected to the power supply line via a resistor, and the output terminal is guided to the gate of the second MOS field-effect transistor. Since a DC voltage is supplied to the non-inverting input terminal, the operational amplifier is connected to the source of the second MOS field-effect transistor so that the inverting input terminal is at the same potential as the non-inverting input terminal. The gate between the gate and the source of the second MOS field-effect transistor is biased so that the voltage at one end of the resistor is equal to the DC voltage supplied to the non-inverting input terminal.

The DC voltage supplied to the non-inverting input terminal of the operational amplifier is a DC voltage output from the voltage generator. The DC voltage output from the voltage generating means is a DC voltage obtained by calculating a voltage proportional to temperature, a voltage insensitive to temperature, a threshold voltage of a logic circuit, and a power supply voltage. Therefore, the voltage at one end of the resistor connected to the source of the second MOS field-effect transistor becomes a voltage proportional to the temperature,
The gate-source of the second MOS field-effect transistor is biased so as to be equal to the DC voltage obtained by calculating the temperature-insensitive voltage, the threshold voltage of the logic circuit, and the power supply voltage.

As a result, the discharge current or the charge current flowing through the second MOS field-effect transistor at the reference temperature is determined by the DC voltage obtained by the calculation of the threshold voltage of the logic circuit and the power supply voltage and the second MOS field-effect transistor. The current is determined by the ratio of the resistance value of the resistor connected to the source, and the fluctuation of the power supply voltage and the fluctuation of the threshold voltage of the logic circuit accompanying the fluctuation are offset by the discharge current or the charging current corresponding to these fluctuations. Therefore, the delay time is not affected by the power supply voltage fluctuation.

Further, the DC voltage supplied to the non-inverting input terminal of the operational amplifier is a voltage component that is insensitive to a power supply voltage obtained by subtracting a temperature-insensitive voltage from a voltage proportional to temperature and is only proportional to temperature (temperature-dependent voltage component). Voltage component whose value becomes zero at the reference temperature) and the voltage between the terminals of the resistor increases with the temperature, so that it is integrated by a polycrystalline silicon layer, a diffusion layer, etc. The decrease in the discharge current or charge current due to the increase in the resistance value due to the rise in the temperature of the resistor is compensated by the increase in the voltage between the terminals of the resistor that specifies the discharge current or the charge current. Is obtained.

Further, since the process variation element of the delay time is only the resistance value of the resistor and the capacitance value of the capacitor due to the above-described canceling action, the delay time is reduced by the variation of the gate capacitance of the MOS field effect transistor, the threshold voltage, and the like. It is not affected by fluctuations in the characteristics of the field effect transistor and fluctuations in the threshold voltage of the logic circuit. For this reason, the influence of the manufacturing process fluctuation on the delay time fluctuation is reduced.

As a result, fluctuations in delay time due to temperature fluctuations, manufacturing process fluctuations, and power supply voltage fluctuations can be reduced.

<Embodiment> FIG. 1 shows an embodiment of the present invention. In the figure, the fourteenth
The same reference numerals as those in the drawings indicate identical components. First MOS field effect transistor M ₁ is formed of an N-channel device, along with a digital input signal V _IN is to be delayed signal is directed to the gate G _1, connected to a ground source S ₁ is at one of the power line Have been.

Second MOS field effect transistor M ₂ is formed of a P-channel device, the drain D with ₂ are connected in common to a drain D ₁ of the first MOS field effect transistor M _1, a source S ₂ is the resistance R _c Power supply voltage V which is one of the power supply lines through
Connected to _DD .

The operational amplifier _A0 has a non-inverting input terminal (+), an inverting input terminal (-), and an output terminal. The inverting input terminal (-) is connected to the source S of the _second MOS field-effect transistor M2.
Is connected to _2, the output terminal is connected to the gate G ₂ of the second MOS field effect transistor M _2.

1 is a bias means. Biasing means 1, and means 101 for generating a dead voltage V _a to the temperature, and means 102 for generating a voltage V _b proportional to the temperature, the means 103 for extracting the threshold voltage V _TH of the logic circuit Q _1, the voltage And generating means 104.

The voltage generating means 104 includes a voltage V _a , V _b and V _TH extracted or generated by each of the means 101 to 103 and a power supply voltage V
The DC voltage V _X obtained by the calculation of the _DD, the operational amplifier
Give to the non-inverting input terminal of A ₀ (+). In an embodiment,
The voltage generator 104 includes an operational amplifier A ₁₁ and a voltage synthesizer A ₁₂ .

Operational amplifier A ₁₁ is constituted the adder circuit, the inverting input terminal (-) is connected via a resistor R ₁₁ to the output terminal of the voltage synthesis unit A _12, the non-inverting input terminal (+) of the resistor R ₁₂
And a power supply line for supplying a power supply voltage V _DD through the resistor R _13, and to the ground via a resistor R ₁₃ . The output terminal is the inverting input terminal (-) through the feedback resistor _Rf1.
It is connected to, and is connected to the non-inverting input terminal of the operational amplifier A ₀ (+). _Set the resistance values of resistors R ₁₁ and R ₁₃ to _Ra1
Then, the resistance values of the feedback resistor R _f1 and the resistor R ₁₂ are (K ₁ R
_a1 ). K ₁ is a constant.

The voltage synthesizing section A ₁₂ forms an addition / subtraction circuit, and each means 1
DC voltage V _a supplied from 01-103, with respect to V _b and V _TH, and outputs the synthesized DC voltage V ₀₁ to be _{V 01 = V TH + V b} + V a.

DC voltage V ₀₁ outputted from the voltage combining unit A _12, the inverting input terminal of the operational amplifier A ₁₁ - is supplied to the (). Operational amplifier A _11, a non-inverting input terminal (+) to the resistor R ₁₃ ground level supplied via the (0 volts), the inverting input terminal (-) Synthesis DC voltage supplied via the resistor R ₁₁ while calculating the difference between V _01, the result of the calculation, by superimposing the supply voltage V _DD supplied to the non-inverting input terminal via a resistor R _12, and outputs the DC voltage V _X from its output terminal . DC voltage V _X becomes _{V X = V DD -K 1 V} 01.

DC voltage V _X which is output from the operational amplifier A ₁₁ is supplied to a non-inverting input terminal of the operational amplifier A ₀ (+). The operational amplifier A ₀ is the resistance R the voltage of the power supply line to the unconnected side terminals _c are biased between a second gate and source of the MOS field-effect transistor M ₂ so as to be equal to the DC voltage V _X.

FIG. 2 shows an example of operation waveforms of the delay circuit shown in FIG. In operation waveform example of Figure 2, when the digital input signal V _IN is at the high level, the first MOS field effect transistor M ₁ and the second MOS field effect transistor M ₂ both become active state. At this time, if the ratio of the first MOS field effect transistor M ₁ of the gate width W and the channel length L (W / L) is sufficiently large relative to that of the second MOS field effect transistor M _2, the first MOS field the gate-source voltage of effect transistor M ₁ and the second MOS field effect transistor M ₂
Therefore, the node a is at a low level (about 0 V) as shown in FIG. 2 (b).

In this state, as shown in FIG. 2 (b), when the digital input signal V _IN goes low at t _0, since the first MOS field effect transistor M ₁ is cut off, the capacitor C and the second It begins to be charged by the MOS field-effect transistor M _2. Therefore, the digital input signal V _IN
Goes low, the voltage at node a becomes
As shown in FIG. Voltage at node a is at t ₁ the voltage is monitored by the logic circuit Q ₁ constituted by inverter crosses the threshold voltage V _TH of the inverter, so the inverter output V _OUT is shown in FIG. 2 (c) Transition from high level to low level.

In the above operation, t ₀ until the falling edge of the digital input signal V _IN is transmitted to the inverter output V _OUT.
It is the time delay time Td of o'clock t ₁ from the time, Td = a _{(V TH · C) / I} DP. In the above equation, I _DP is the value of the second MOS field effect transistor M ₂
, And becomes a charging current for the capacitor C.

Here, since the DC voltage V _X to the non-inverting input terminal (+) of the operational amplifier A ₀ from the operational amplifier A ₁₁ constituting the voltage generating means 104 is supplied, an operational amplifier A ₀ is the power of the resistance R _c voltage side not connected to the line, the gate-DC voltage V _X becomes equal as in the second MOS field effect transistor M ₂
Bias between sources. Thus, the voltage across the terminals of the resistor R _c is a (V _DD -V _X). Therefore, the resistance R _C and the second MOS
Charging current I _DP through the field effect transistor M _{2 is, I DP = (V DD -V} X) / R c , and the delay time Td is given by the following equation.

Td = V _TH · C / I _DP = V _TH · C / ｛(V _DD −V _X ) / R _c ＝ = V _TH · R _c · C / (V _DD −V _X ) = C · R ₀ · ｛ 1 + α (T−T ₀ )｝ · V _TH / (V _DD −
V _X ) (1) where α is the temperature coefficient of the resistance R _c and α = (1 / R _c ) (∂R _c / ∂T)> 0 R ₀ is the resistance R _c at the reference temperature T ₀ Is the value of. Therefore, in order to suppress the fluctuation of the delay time Td due to the power supply voltage and the temperature / fluctuation, (V _DD -V _X ) is set to a voltage proportional to V _TH and the temperature coefficient of (V _DD -V _X ) is reduced. it may be selected the same as the temperature coefficient α of resistance R _c. That is,
In the equation (1), the denominator (V _DD -V _X ) is a value (K ₁ V _TH ) having a positive temperature gradient of K ₀ [V / ° C.] and being proportional to the threshold voltage V _TH at the reference temperature T _0. DC voltage V _X such that, i.e., the DC voltage V _X may if generated so as to satisfy the following equation (2). K ₁ is a constant.

(V _DD −V _X ) = K ₁ {V _TH + K ₀ (T−T ₀ )} (2) When the above equation (2) is substituted into equation (1), the delay time Td
Is given by the following equation.

_{Td = C · R 0 · {} 1 + α (T-T 0)} · V TH / [K 1 {V TH + K 0 (T-T 0)}] = C · R 0 · {1 + α (T-T 0) ｝ · V _TH / [K ₁ V _TH ｛1 + β (T−T ₀ )｝] (3) where β = K ₀ / V _TH where K ₀ = α · V _TH and α = β Then, the delay time Td becomes Td = C · R ₀ / K ₁ (4), which is independent of temperature fluctuations, power supply voltage fluctuations, and manufacturing process fluctuations.

The bias means 1 sets conditions that satisfy the above equations (2) to (4). Figure 3 is a diagram showing a specific example of the biasing means 1 for generating the satisfying DC voltage V _X.

The means 101 for generating a temperature-insensitive voltage comprises an operational amplifier A
₂₁ , two diode-connected bipolar transistor pairs Q ₁₁ and Q ₂₁ having different emitter areas, and resistors R ₃₁ and R ₃₂
And the R _33, and an operational amplifier A _22. The operational amplifier A _21, a non-inverting input terminal (+) is connected to the emitter of the bipolar transistor Q _11, the inverting input terminal (-) is connected to the connection point between the resistor R ₃₁ and the resistor R _32.

The operational amplifier A ₂₂ is an inverting input terminal (-) is connected to the output terminal of the operational amplifier A ₂₁ via the resistor R _41, the non-inverting input (+) is connected via a resistor R ₄₂ to the power supply voltage V _DD Rutotomoni is connected to ground through a resistor R _43. The output terminal is connected to the inverting input terminal (-) via the feedback resistor _Rf3 . When the resistance value of the resistor R _41, R ₄₂ and R _a2, resistors R _43, R _f3 is selected to be (K ₂ R _a2).

Means 102 for generating a voltage V _b proportional to the temperature includes an operational amplifier A _31, and two bipolar transistors pair Q _31, Q ₄₁ having different emitter areas which are diode-connected, the resistor R
_51, and R ₅₂ and R _53, and an operational amplifier A _32.
The operational amplifier A _31, a non-inverting input terminal (+) is connected to the emitter of the bipolar transistor Q _31, the inverting input terminal (-) is connected to the connection point between the resistor R ₅₁ and the resistor R _52. The operational amplifier A ₃₂ is an inverting input terminal (-) is connected to the output terminal of the operational amplifier A ₃₁ via the resistor R _61, the non-inverting input (+) is connected via a resistor R ₆₂ to the power supply voltage V _DD together, they are connected to ground via a resistor R _63. The output terminal is connected to the inverting input terminal (-) via the feedback resistor _Rf4 . Resistor R ₆₁ to R ₆₃ and a feedback resistor R _f4 are selected to be substantially equal to the resistance value R _a3.

Means 103 for extracting the threshold voltage V _TH of the logic circuit Q ₁ is provided with a logic circuit Q _51, and an operational amplifier A _41. Logic circuit Q
₅₁ is a logic circuit Q ₁ (first circuit) disposed on the output side of the delay circuit.
(Refer to the figure), and the output is connected to the input. The output voltage of the full feedback inverter output and the input is connected, because equal to the threshold voltage of the inverter, the logic circuit Q ₅₁ threshold voltage V _TH is substantially equal to the threshold voltage V _TH of the logic circuit Q ₁ is extracted Is done. Extracted threshold voltage V _TH is supplied to the non-inverting input terminal of the operational amplifier A ₄₁ (+). The operational amplifier A ₄₁ is being unity feedback connection constitute the impedance converter gain 1, the threshold voltage V _TH, which is input to the non-inverting input terminal (+)
Is output with low impedance.

The voltage generation means 104 includes operational amplifiers A ₁₁ and A ₁₂ . Operational amplifier A ₁₂ is an inverting input terminal (-) connected to the output terminal of the operational amplifier A ₂₂ which constitute the means 101 for generating a dead voltage V _a to a temperature through the resistor R _21, the non-inverting input terminal ( +) with is connected to the output terminal of the operational amplifier a ₃₂ which constitute the means 102 for generating a voltage V _b proportional to temperature via the resistor R _22, the threshold voltage V of the logic circuit via the resistor R ₂₃
It is connected to the output terminal of the operational amplifier A ₄₁ which constitute the means 103 for extracting _TH. R _f2 is a feedback resistor. Resistance R ₂₁ ~
R ₂₃ and feedback resistor R _f2 is selected to be substantially equal to the resistance value R _a4.

In the above circuit configuration, the output voltage V ₁ of the operational amplifier A ₂₁ of the means 101 and the output voltage V ₂ of the operational amplifier A ₃₁ of the means 102
Are given by the following equations, respectively.

V ₁ = V _DD- ｛V _BE1 + V _P1 (T)｝ (5) V ₂ = V _DD- ｛V _BE3 + V _P2 (T)｝ (6) where V _P1 (T) = (kT / q) (R 32 / R 31) ln [(I 1 / I 2) (S 2 / S 1)] = (kT / q) (R 32 / R 31) ln [(R 32 / R _{33) (S 2 / S 1} )] V P2 (T) = (kT / q) (R 52 / R 51) ln [(I 3 / I 4) (S 4 / S 3)] = (kT / q ) (R ₅₂ / R ₅₁ ) ln [(R ₅₂ / R ₅₃ ) (S ₄ / S ₃ )] k: Boltzmann constant T: absolute temperature q: electron charge S ₁ : emitter area S of bipolar transistor Q _{11 2:} emitter area of the bipolar transistor Q ₂₁ S _3: emitter area of the bipolar transistor Q ₃₁ S _4: emitter area of the bipolar transistor Q ₄₁ V _BE1: base-emitter voltage V of the bipolar transistor Q _{11 BE3:} the bipolar transistor Q ₃₁ Here, the base-emitter voltages V _BE1 and V _BE3 are −
A voltage with a negative temperature coefficient of about 2 mV / ° C.
_P1 (T) and _VP2 (T) are voltages proportional to the absolute temperature T.

In this embodiment, the operational amplifiers A ₂₁ and A ₃₁ are respectively set to zero and K ₀ (= αV _TH ) with respect to the power supply voltage V _DD.
In order to generate a voltage having a temperature gradient of [mV / ° C.], that is, to provide the output voltages V ₁ and V ₂ of the operational amplifiers A ₂₁ and A ₃₁ , the second right side of the above equations (5) and (6) So that the temperature gradients of the terms are zero and K ₀ (= αV _TH ) [mV / ° C.], respectively.
Determine each circuit constant. In section 101, conditions the operational amplifier A ₂₁ is a temperature gradient generates a voltage of zero supply voltage V _DD as a reference, from supra _{(5), (∂V BE1 / ∂T) +} (∂V P1 ( T) / ∂T) = 0 (∂V _BE1 / ∂T) + (k / q) (R ₃₂ / R ₃₁ ) · ln [(R ₃₂ / R ₃₃ ) (S ₂ / S ₁ )] = 0 is there.

Now, assuming that (∂V _BE1 / ∂T) =-2 [mV / ° C], and if R ₃₂ = R ₃₃ S ₂ / S ₁ = 10 is selected, the resistance ratio (R ₃₂ / R ₃₁ ) becomes R ₃₂ / R ₃₁ = − (∂V _BE1 / ∂T) / [(k / q) ln ｛(R ₃₂ / R ₃₃ ) · (S ₂ / S ₁ )｝] = 2.0 / [(0.085) ln ( 10)] = 10, the temperature fluctuation of V _BE1 + V _P1 (T) can be made zero. Under these conditions, the reference temperature T _{0 is set} to 300K (absolute temperature), and the base-emitter voltage at this reference temperature T ₀
Assuming that V _BE1 is 0.7 V, V _BE1 (T ₀ ) + V _P1 (T ₀ ) = 0.7 + (0.085 · 10 ⁻³ ) (300) (10) ln (10) = 1.3 [V] Since this value does not change due to changes in temperature and power supply voltage, if this value is defined as a constant voltage V _REF1 , V ₁ = V _DD −V _REF1 .

On the other hand, in the means 102, the operational amplifier A _31
The condition for generating a voltage having a temperature gradient of K ₀ [mV / ° C.) based on _DD is given by (式 V _BE3 / ∂T) + ｛∂V _P2 (T) / ∂T from the above equation (6). ｝ = K ₀ (∂V _BE3 / ∂T) + (k / q) (R ₅₂ / R ₅₁ ) ・ ln [(R ₅₂ / R ₅₃ ) (S ₄ / S ₃ )] = K ₀ . Here, K ₀ = αV _TH . As a specific example, α
= 800 _[ppm / ℃], assuming _{V TH = 2.5V, K 0 =} αV TH = 2.0 because it is [mV / ℃], (∂V BE3 / ∂T) = - a 2 [mV / ℃] assuming, when _{R 52 = R 53, S 4} / S 3 = 20, the resistance ratio that satisfies the above conditions (R ₅₂ / R ₅₁₎ is _{R 52 / R 51 = {K} 0 -∂V BE3 / ∂T } / [(k / q) ln {(R 52 / R 53) · (S 4 / S 3)}] = {2.0 - (- 2.0) a} / (0.085) ln (20 ) = 16. Therefore, R ₅₂ = R ₅₃ , S ₄ / S ₃ = 20, (R ₅₂ / R ₅₁ ) =
By selecting 16, the temperature gradient of V _BE3 + V _P2 (T) can be set to αV _TH = +2.0 [mV / ° C].

The output voltage V ₂ of the operational amplifier A ₃₁ at the unit 102, the power supply the voltage V _DD is superimposed, calculated in the operational amplifier A ₃₂ included in the differential amplifier from the power supply voltage V _DD amplifier A
Subtracting the output voltage V ₂ of _{31, V b = V DD -V} 2 = V BE3 + V P2 (T) , and the temperature gradient alpha] V _TH = + 2.0 voltage component having a _{[mV / ℃] {V BE3} + V P2 (T) Only｝ can be extracted. with this,
The temperature gradient αV _TH was obtained, but what is required here is that the temperature gradient is K ₀ (=
αV _TH ), the voltage K at which the value becomes zero at the reference temperature T _{0
Since it is 0} (T−T ₀ ), the voltage V _b (T ₀ ) at the reference temperature T ₀ must be subtracted from the voltage _Vb as an offset. Since this offset component must not have fluctuations due to temperature and power supply voltage fluctuations, the voltage V _REP1 obtained by the means 101 for generating a temperature-insensitive voltage is used.
Since the power supply voltage V _DD is superimposed on the output voltage V ₁ of the operational amplifier A ₂₁ in the means 101, the operational amplifier A ₂₂ operating as a differential amplifier outputs the output voltage V of the operational amplifier A ₂₁ from the power supply voltage V _DD. with subtracting ₁ and imparts coefficient K ₂ by the resistance ratio of the operational amplifier a resistor R ₄₁ to R ₄₃ are connected to ₂₂ and a feedback resistor _{R f3, V a = K 2} (V DD -V 1) = K 2 V _REF1 and a constant voltage (K ₂ V _REF1 ) can be obtained.
Here, V _b (T ₀₎ the output voltage V _a of the unit 101 = V _BE3 (T ₀₎
+ V _p2 (T ₀₎ coefficient K ₂ is the following relationship _{to, K 2 V REF1 = V BE3} (T 0) + V P2 (T 0) = V BE3 (T 0) + (k / q) (R 52 / R ₅₁ ) (T ₀ ) · ln [(R ₅₂ / R ₅₃ ) (S ₄ / S ₃ )]. Here, assuming that V _BE3 (T ₀ ) = 0.7 V and R ₅₂ = R ₅₃ S ₄ / S ₃ = 20 R ₅₂ / R ₅₁ = 16 V _REF1 = 1.3 V, the resistance ratio that satisfies the above condition K ₂ is determined as follows.

K ₂ V _REF1 = V _BE3 (T ₀ ) + (k / q) (R ₅₂ / R ₅₁ ) (T ₀ ) · ln [R ₅₂ / R ₅₃ ) (S ₄ / S ₃ )] = 1.9 K ₂ = _{1.9 / V REF1 = 1.9 / 1.3} = 1.5 operational amplifier a ₁₂ constitutes a subtracting circuit, the output voltage V ₀₁ is given by the following equation.

_{V 01 = V TH + (V} b -V a) = V TH + {V BE3 (T) + V P2 (T)} - {V BE3 (T 0) + V P2 (T 0)} V TH + αV TH (T -T ₀₎ That is, means from the output voltage V _b of the operational amplifier a ₁₂ with means 102
101 output voltage V _a of subtracted, the calculation result _{(V b -V a) = αV} TH threshold voltage V _TH of the (T-T ₀₎ to the logic circuit Q ₅₁ is superimposed. Threshold voltage V
_TH is obtained by full feedback to an output of the logic circuit Q ₅₁ as described above.

Operational amplifier A ₁₁ constitutes a subtracting circuit, the output voltage V _X is Ataeraru the following equation.

V _X = V _DD -K ₁ V ₀₁ = V _DD -K ₁ {V _TH + αV _TH (T−T ₀ )} = V _DD −K ₁ V _TH {1 + α (T−T ₀ )} That is, the operational amplifier A ₀ noninverting conditions required for the DC voltage V _X which is supplied to the input terminal of the (first reference drawing), voltage (V
Since _DD -V _X) is that it becomes _{K 1 V TH {1 + α} (T-T 0)}, calculated by amplifier A _11, a ground level supplied to the non-inverting input terminal via a resistor R ₁₃ (0V )
The difference between the output voltage V ₀₁ of the operational amplifier A ₁₂ is supplied to the inverting input terminal via a resistor R ₁₁ and the coefficient K ₁ by the resistance ratio of resistor (-V ₀₁₎ R ₁₁ ~R ₁₃ and a feedback resistor R _f1 And the power supply voltage V _DD supplied to the non-inverting input terminal via the resistor R ₁₂ is superimposed on this voltage (−K ₁ V ₀₁ ), so that the DC voltage V _X (= V _DD −K ₁ V ₀₁ ). By supplying the operational amplifier non-inverting input terminal of the A ₀ constituting the delay circuit shown this to Figure 1 (+), temperature fluctuations, less delay circuit delay time varies due to manufacturing process variations and supply voltage fluctuations can get.

In the above embodiment, the coefficient K ₁ is applied by the resistance ratio of the operational amplifier A resistor R ₁₁ is connected to the ₁₁ to R ₁₃ and a feedback resistor R _f1 to ensure the amplitude of the ramp voltage, second
Consider the MOS field effect transistor M ₂ dimensions and (W / L) output voltage range of the operational amplifier A _0, so that the voltage effect at the resistor R _c is as small as possible, be K ₁ <1 desirable.

The npn bipolar transistors Q ₁₁ , Q ₂₁ , Q ₃₁ and Q ₄₁ used in the above embodiment are manufactured in the same process as the source / drain of the N-channel MOS field effect transistor.
By using an n ⁺ diffusion layer as an emitter, a P well as a base, and an N-type substrate as a collector, it can be easily manufactured by a P well C-MOS process.

FIG. 4 is an electric circuit diagram of still another embodiment of the delay circuit according to the present invention. In the figure, the same reference numerals as those in FIG. 1 indicate the same components. In this embodiment, the first MOS field effect transistor M ₁ is formed of a P-channel device, the digital input signal V _IN is to be delayed signal is directed to the gate G _1, the source S _1
Are connected to the power supply voltage V _DD .

Together with the second MOS field effect transistor M ₂ is an N-channel device, its drain D ₂ is connected in common to a drain D ₁ of the first MOS field-effect transistors M _1,
Source S ₂ is connected to ground via a resistor R _c.

In this embodiment, when the digital input signal V _IN is first MOS field effect transistor M ₁ at a low level is conductive, charges in the capacitor C are accumulated, the digital input signal V _IN is at the high level 1 when MOS field effect transistor M ₁ of becomes cutoff, the second MOS field effect transistor the charge accumulated through M ₂ to the capacitor C is discharged, the lamp voltage is formed. Voltage between terminals of capacitor C due to the above-mentioned charge / discharge (voltage at node a)
But is converted into a binary signal by the threshold voltage V _TH of the logic circuit Q _1, it is outputted as a delayed digital signal. Therefore,
The operation waveform of each part of the circuit in this embodiment is the same as in FIG.

Similar to Example biasing means 1 shown in FIG. 1, a means 101 for generating a dead voltage V _a to the temperature, and means 102 for generating a voltage V _b proportional to the temperature, the threshold voltage of the logic circuit Q ₁ V _TH
, And voltage generating means 104. However, in this embodiment, the means 101 and the means 102
Is a voltage V _a insensitive to temperature based on the power supply voltage V _DD , a voltage V _b proportional to temperature ｛a voltage (V _DD
−V _a ) and the voltage (V _DD −V _b )｝.

The operational amplifier _A0 has a non-inverting input terminal (+), an inverting input terminal (-), and an output terminal. The inverting input terminal (-) is connected to the source S of the _second MOS field-effect transistor M2.
Is connected to _2, the output terminal is connected to the gate G ₂ of the second MOS field effect transistor M _2.

The voltage generating means 104 is obtained by calculating each of the voltages (V _DD -V _a ), (V _DD -V _b ) and V _TH extracted or generated by each of the means 101 to 103, and the power supply voltage V _DD. the DC voltage V _X and gives to the non-inverting input terminal of the operational amplifier a ₀ (+). In the embodiment, the voltage generating means 104 is an operational amplifier.
A ₁₁ and a voltage synthesizing unit A ₁₂ are provided.

Operational amplifier A ₁₁ is constituted the adder circuit, the inverting input terminal (-) is supplied with the threshold voltage V _TH of the logic which is extracted by means 103 via the resistor R _11, the non-inverting input terminal (+) it is is connected through a resistor R ₁₂ to the power supply voltage V _DD, is connected to ground through a resistor R _13. Output feedback resistors R _f1 the inverting input terminal via (-) is connected to, it is guided to the voltage combining unit A _12. When the resistance value of the resistor R _11, R ₁₂ and R _a1, the feedback resistor R _f1
And resistor R ₁₃ is chosen to be the resistance value (K ₁ R _a1). K ₁ is a constant. The operational amplifier A ₁₁ is connected to the power supply voltage V _DD supplied to the non-inverting input terminal (+) through the resistor R _12.
(V _DD −V _TH ) between the threshold voltage V _TH of the logic circuit supplied to the inverting input terminal (−) through the resistor R ₁₁
The resistance R by applying the coefficient K ₁ by the resistance ratio of ₁₁ to R ₁₃ and a feedback resistor R _f1, and outputs the DC voltage K ₁ from the output terminal (V _DD -V _TH).

The voltage synthesizing unit A ₁₂ forms an addition / subtraction circuit, and means 10
1. Each DC voltage (V _DD −
Regarding V _a ), (V _DD −V _b ) and the DC voltage K ₁ (V _DD −V _TH ) output from the operational amplifier A ₁₁ , V _X = K ₁ (V _DD −V _TH ) + (V _DD − V _a ) − (V _DD −V _b ) V _X = K ₁ (V _DD −V _TH ) + V _b −V _{a The} combined DC voltage V _X is output.

DC voltage V _X output from the voltage combining unit A ₁₂ is supplied to a non-inverting input terminal of the operational amplifier A ₀ (+). The operational amplifier A ₀ is the resistance voltage of the R _c ground unconnected side terminals are biased between a second gate and source of the MOS field-effect transistor M ₂ so as to be equal to the DC voltage V _X. The delay time Td obtained by this embodiment is given by the following equation, similarly to the delay circuit shown in FIG.

Td = (V _DD −V _TH ) · C / I _{DN In the} above equation, I _DN is the drain current of the _second MOS field-effect transistor M2, and is a discharge current for discharging the charge accumulated in the capacitor C.

Here, since the DC voltage V _X to the non-inverting input terminal of the operational amplifier A ₀ (+) from the voltage combining unit A ₁₂ which constitutes a voltage generating means 104 is supplied, an operational amplifier A ₀ is the resistance R _c side of the voltage that is not connected to the power supply line, a gate-DC voltage V _X becomes equal as in the second MOS field effect transistor M ₂
Bias between sources. Thus, since the terminal voltage of the resistor R _c is a V _X, resistance R _c and the discharge current I _DN second flowing through MOS field effect transistor M _{2 is, I DN = V X / R} c , and the delay time Td is given by the following equation.

Td = (V _DD- V _TH ) · C / I _DN = (V _DD- V _TH ) · R _c · C / V _X = C · R ₀ · {1 + α (T-T ₀ )] · (V _DD- V _TH ) / V
_X (7) where α is the number of temperatures of the resistor R _c , and α = (1 / R _c ) (∂R _c / ∂T) R ₀ is the resistance value of the resistor R _c at the reference temperature T ₀ It is.

Therefore, in order to suppress the fluctuation of the delay time Td by the source voltage and temperature variations, as well as the voltage proportional to the DC voltage V _X to (V _DD -V _TH), the resistance temperature coefficient of the DC voltage V _X R _What is necessary is just to select the same as the temperature coefficient α of _c .

That is, a direct current having a positive temperature gradient K ₀ [V / ° C.] and being proportional to the voltage (V _DD −V _TH ) of the difference between the power supply voltage and the threshold voltage at the reference temperature T ₀ as shown in Expression (8) the voltage V _X may, if possible occurrence. K ₁ is a constant.

V _X = K ₁ (V _DD −V _TH ) + K ₀ (T−T ₀ ) (8) By substituting the above equation (8) into the equation (7), the delay time Td
Is given by the following equation.

_{Td = C · R 0 · {} 1 + α (T-T 0)} · (V DD -V TH) / {K 1 (V DD -V TH) + (T-T 0)} = C · R 0 · { 1 + α (T−T ₀ )｝ · (V _DD −V _TH ) / [K ₁ (V _DD −V _TH ) · {1 + β (T−T ₀ )}] (9) where β = K ₀ / ｛ K ₁ (V _DD −V _TH )｝ Here, assuming that K ₀ = α · K ₁ (V _DD −V _TH ) and α = β, the delay time Td is Td = C · R ₀ / K ₁ · ··· (10) and becomes independent of temperature fluctuations, power supply voltage fluctuations, and manufacturing process fluctuations.

The bias means 1 sets conditions that satisfy the above equations (8) to (10). FIG. 5 is a diagram showing a specific example of a bias means 1 for generating the satisfying DC voltage V _X.

Means 101 for generating a dead voltage V _a to a temperature of the power supply voltage V _DD as a reference, the operational amplifier A ₂₁ and the diode-connected two pnp bipolar transistor pair having different emitter area Q _11, Q _21, resistors R ₃₁ includes a R ₃₂ and R _33, an operational amplifier a _22. The operational amplifier A _21, a non-inverting input terminal (+) is connected to the emitter of the bipolar transistor Q _11, the inverting input terminal (-) is connected to the connection point between the resistor R ₃₁ and the resistor R _32.

The operational amplifier A ₂₂ is an inverting input terminal (-) is connected to the output terminal of the operational amplifier A ₂₁ via the resistor R _41, together with the non-inverting input terminal (+) is connected to ground via a resistor R ₄₂ It is connected to the power supply voltage V _DD via a resistor R _43.
The output terminal is the inverted input terminal (-) through the feedback resistor _Rf3.
It is connected to the. When the resistance value of the resistor R _41, R ₄₂ and R _a2, resistors R _43, R _f3 is chosen such that (K ₂ R _a2).

Means for generating a voltage V _b proportional to the temperature based on the power supply voltage V _DD 102 includes an operational amplifier A _31, and two pnp bipolar transistor pair Q _31, Q ₄₁ having different emitter areas which are diode-connected, the resistor R _51, and R ₅₂ and R _53, and an operational amplifier a _32. The operational amplifier A _31, a non-inverting input terminal (+) is connected to the emitter of the bipolar transistor Q _31, the inverting input terminal (-) is connected to the connection point between the resistor R ₅₁ and the resistor R _52. The operational amplifier A ₃₂ is an inverting input terminal (-) connected to the output terminal of the operational amplifier A ₃₁ via the resistor R _61, together with the non-inverting input terminal (+) is connected to ground via a resistor R _62, It is connected to the power supply voltage V _DD via a resistor R _63. The output terminal is connected to the inverting input terminal (-) via the feedback resistor _Rf4 . Resistance R _{61 to} R ₆₃
And feedback resistor R _f4 are substantially equal in this example
It has been selected to be _a3 .

Means 103 for extracting the threshold voltage V _TH of the logic circuit Q ₁ is provided with a logic circuit Q _51, and an operational amplifier A _41. Logic circuit Q
₅₁ is a logic circuit Q ₁ (fourth circuit) arranged on the output side of the delay circuit.
(Refer to the figure), and the output is connected to the input. The output voltage of the full feedback inverter output and the input is connected, because equal to the threshold voltage of the inverter, the logic circuit Q _51, the threshold voltage V _TH is substantially equal to the threshold voltage V _TH of the logic circuit Q ₁ is Is extracted. Extracted threshold voltage V _TH is supplied to the non-inverting input terminal of the operational amplifier A ₄₁ (+). The operational amplifier A ₄₁ is connected in a unity feedback manner to form an impedance converter having a gain of 1, and has a threshold voltage V input to a non-inverting input terminal (+).
Outputs _TH with low impedance.

The voltage generation means 104 includes operational amplifiers A ₁₁ and A ₁₂ . Operational amplifier A _11, as described with reference to FIG. 4, the inverting input terminal (-) connected to the output terminal of the operational amplifier A ₄₁ which constitute the means 103 via the resistor R _11, the non-inverting input terminal (+ ) of which is connected to the power supply voltage V _DD via a resistor R _12, it is connected to ground via a resistor R _13. R _f1 is a feedback resistor. When the resistance value of the resistor R ₁₁ and R ₁₂ and R _a1, the resistance value of the resistor R ₁₃ and R _f1 is chosen to be (K ₁ R _a1). The operational amplifier A ₁₂ is a hydrochloric acid amplifier whose inverting input terminal (−) constitutes means 102 via a resistor R _21.
Connected to the output terminal of the A _32, together with the non-inverting input terminal (+) is connected to the output terminal of the operational amplifier A ₂₂ which constitute the means 101 via the resistor R _22, the operational amplifier A through a resistor R _23
11 output terminals. R _f2 is a feedback resistor. Resistor R ₂₁ to R ₂₃ and a feedback resistor R _f2 is selected to be substantially equal to the resistance value R _a4.

In the above circuit configuration, the output voltage V ₁ of the operational amplifier A ₂₁ of the means 101 and the output voltage V ₂ of the operational amplifier A ₃₁ of the means 102
Are given by the following equations, respectively.

V ₁ = | V _BE1 | + V _P1 (T) (11) V ₂ = | V _BE3 | + V _P2 (T) (12) where V _P1 (T) = (kT / q) _{(R 32 / R 31) ln} [(I 1 / I 2) (S 2 / S 1)] = (kT / q) (R 32 / R 31) ln [(R 32 / R 33) (S 2 / S ₁ )] V _P2 (T) = (kT / q) (R ₅₂ / R ₅₁ ) ln [(I ₃ / I ₄ ) (S ₄ / S ₃ )] = (kT / q) (R ₅₂ / R _{51) ln [(R 52 /} R 53) (S 4 / S 3)] K: Boltzmann constant T: absolute temperature q: electron charge amount S _1: emitter area of the bipolar transistor Q ₁₁ S _2: bipolar transistor Q ₂₁ emitter area S _3: emitter area of the bipolar transistor Q ₃₁ S _4: emitter area of the bipolar transistor Q ₄₁ V _BE1: base-emitter voltage V of the bipolar transistor Q _{11 BE3:} base-emitter voltage of the bipolar transistor Q ₃₁ wherein in the base-emitter voltage | V _BE1 | and | V _BE3 | negative of about -2 mV / ° C. A voltage with a degree coefficient, V
_P1 (T) and _VP2 (T) are voltages proportional to the absolute temperature T.

In the present embodiment, the operational amplifier A constituting the means 101
_The operational amplifier A ₃₁ constituting the means ₂₁ and the means 102 has a temperature gradient of zero with respect to the ground and K ₀ ｛= αK ₁ (V _DD
−V _TH ) [mV / ° C] Determine circuit constants to generate voltages V ₁ and V ₂ , respectively. In section 101, the condition for zero temperature gradient of the output voltage V ₁ of the operational amplifier A _21, from the supra _{(11), (∂ | V BE1 | /} ∂T) + (∂V P1 (T) / ∂T) = 0 (∂ | V _BE1 | / ∂T) + (k / q) (R ₃₂ / R ₃₁ ) · ln [(R ₃₂ / R ₃₃ ) (S ₂ / S ₁ )] = 0 . Now, assuming that (∂ | V _BE1 | / ∂T) = -2 [mV / ° C] to show a specific example of determining the circuit constants, it was assumed that R ₃₂ = R ₃₃ S ₂ / S ₁ = 10 was selected. Then, the resistance ratio (R ₃₂ / R ₃₁ ) is changed to R ₃₂ / R ₃₁ = − (∂ | V _BE1 | / ∂T) / [(k / q) ・ ln ｛(R ₃₂ / R ₃₃ ) (S ₂ / If S ₁ )｝] = 2.0 / [(0.085) ln (10)] = 10, the temperature fluctuation of V ₁ = | V _BE1 | + V _P1 (T) can be made zero. Under this condition, the reference temperature T _{0 is set} to 300K
(Absolute temperature), and assuming that the base-emitter voltage | V _BE1 | at this temperature T ₀ is 0.7 V, | V _BE1 (T) | + V _P1 (T ₀ ) = 0.7 + (0.085 · 10 ⁻³⁾ ) (300) (10) ln (10) = 1.3 [V]. Since this value does not change with temperature, assuming that this is a constant voltage V _REF1 , V ₁ = V _REF1 .

On the other hand, in the means 102, the output voltage V ₂ of the operational amplifier A ₃₁
The conditions for making the temperature gradient of K ₀ [mV / ° C] are as described in (12) above.
From the equation, (∂ | V _BE3 | / ∂T) + ｛∂V _P2 (T) / ∂T｝ = K ₀ (∂ | V _BE3 | / ∂T) + (k / q) (R ₅₂ / R ₅₁ Ln [(R ₅₂ / R ₅₃ ) (S ₄ / S ₃ )] = K ₀ . Here, K ₀ = αK ₁ (V _DD −V _TH ). As specific examples, α = 800 [ppm / ° C], K ₁ = 0.4, V _DD = 5.0 V, V _TH =
Assuming 2.5 V, K ₀ = αK ₁ (V _DD −V _TH ) = 0.8 [mV / ° C.] _Therefore , it is assumed that (∂ | V _BE3 | / ∂T) = − 2 [mV / ° C.] , R ₅₂ = the R _53, and _{S 4 / S 3 = 20,} R 52 / R 51 = {K 0 -∂V BE3 / ∂T} / [(k / q) · ln {(R 52 / R 53 ) (S ₄ / S ₃ )}] = {0.8 − (− 2.0)} / {(0.085) ln (20)} = 11. Therefore, R ₅₂ = R ₅₃ , S ₄ / S ₃ = 20, (R ₅₂ / R ₅₁ ) = 11
The temperature gradient of | V _BE3 | + V _P2 (T) can be set to αK ₁ (V _DD −V _TH ) = + 0.8 [mV / ° C.].

Operational amplifier A ₃₂ of the means 102, the non-inverting input terminal (+) to the ground level supplied via the resistor R ₆₂ (0 volts), the inverting input terminal - is supplied via the resistor R ₆₁ in () while calculating the difference between the voltage V _2, the result of the calculation,
Supply voltage V to be supplied to the non-inverting input terminal via a resistor R ₆₃
Superimpose _DD . As a result, the output voltage (V _DD −V _b ) of the means 102 in the present embodiment becomes V _DD −V _b = V _DD −V ₂ = V _DD − {| V _BE3 | + V _P2 (T)}. temperature gradient a voltage V _DD as a reference .alpha.k ₁ (V _DD -
| V _BE3 | + V _P2 (T) having (V _TH ) = + 0.8 [mV / ° C.] can be extracted. As a result, the temperature gradient αK ₁ (V _DD −V _TH ) is obtained, but what is required here is the temperature gradient K ₀ ｛= αK ₁ (as shown in the second term on the right side of the equation (8). V _DD at -V _TH)}, the reference temperature T _0, since the voltage K ₀ whose value is zero (T-T _0), the voltage V _b (T ₀ at a reference temperature T ₀ from the voltage V _b ) Must be subtracted as an offset. Since this offset component must not fluctuate due to temperature and power supply voltage fluctuations, a means 10 for generating a temperature-insensitive voltage
Use the voltage V _REF1 obtained in step 1. Since the output voltage V ₁ of the operational amplifier A ₂₁ of the unit 101 has a ground reference, an operational amplifier A _22, via a resistor R ₄₂ non-inverted input terminal to the ground level is supplied (0V) resistor R The output voltage V _{1 of the} operational amplifier A ₂₁ supplied to the inverting input terminal via ₄₁
To the difference (−V ₁ ), the coefficient K ₂ by the resistance ratio of the resistors R _{41 to} R ₄₃ connected to the operational amplifier A ₂₂ and the feedback resistor R _f3.
When the power supply voltage V _DD supplied to the non-inverting input terminal via the resistor R ₄₃ is superimposed, the output voltage (V _DD −V _a ) of the means 101 becomes V _DD −V _a = V _DD −K ₂ V ₁ = V _DD −K ₂ V _REF1 , and the constant voltage K ₂ V _REF1 can be extracted based on the power supply voltage V _DD . Here, V _a is V _b (T ₀ ) = | V
_BE3 (T ₀ ) | −V _P2 (T ₀ ). Resistance ratio K ₂ the following _{relationship, K 2 V REF1 = | V} BE3 (T 0) | + V P2 (T 0) = | V BE3 (T 0) | + (k / q) (R 52 / R 51) (T ₀ ) · ln [(R ₅₂ / R ₅₃ ) (S ₄ / S ₃ )] Here, assuming that | V _BE3 (T ₀ ) | = 0.7 V and R ₅₂ = R ₅₃ S ₄ / S ₃ = 20 R ₅₂ / R ₅₁ = 11 V _REF1 = 1.3 V, the resistance ratio K ₂ becomes It is determined as follows.

K ₂ V _REF1 = | V _BE3 (T ₀ ) | + (k / q) (R ₅₂ / R ₅₁ ) (T ₀ ) · ln [(R ₅₂ / R ₅₃ ) (S ₄ / S ₃ )] = 1.54 _{[V] K 2 = 1.54 /} V REF1 = 1.54 / 1.3 = 1.2 operational amplifier a ₁₂ constitutes a voltage synthesis unit, the output voltage V _X is given by the following equation.

V _X = K ₁ (V _DD −V _TH ) + (V _DD −V _a ) − (V _DD −V _b ) = K ₁ (V _DD −V _TH ) + (V _b −V _a ) = K ₁ ( V _DD −V _TH ) + ｛| V _BE3 (T) | + V _P2 (T)｝ − ｛| V _BE3 (T ₀ ) | + V _P2 (T ₀ )｝ = K ₁ (V _DD −V _TH ) + αK _{1 (V DD -V TH) (T} -T 0) that is, the output voltage at the operational amplifier _{A 12} (V _DD -V _a) from the output voltage (V _DD -V _b) is subtracted, the calculation result (V _b -
_{V a) = αK 1 (V} DD -V TH) ( output voltage K ₁ of T-T ₀₎ to the operational amplifier A ₁₁ (V _DD -V _TH) is superimposed. Operational amplifier A ₁₂
By supplying the output voltage V _X to the non-inverting input terminal of the operational amplifier A ₀ which constitute the delay circuit shown in FIG. 4 (+), temperature variations, the delay time variation due to manufacturing process variations and supply voltage variations A small delay circuit can be obtained.

The pnp bipolar transistors Q ₁₁ , Q
₂₁ , Q ₃₁ , and Q ₄₁ are formed by using a p ⁺ diffusion layer manufactured in the same process as the source / drain of the P-channel MOS field-effect transistor as an emitter, using an N-well as a base, and using a P-type substrate as a collector. It can be easily manufactured by an N-well C-MOS process.

The embodiment shown in FIGS. 1 and 3 is an N-well C-MO
The embodiment shown in FIGS. 4 and 5 is suitable for an S process, and is suitable for a P-well C-MOS process.

FIG. 6 shows still another embodiment of the delay circuit according to the present invention. The feature of this embodiment is to have a current mirror circuit B ₁ to be displayed by a dotted line packaging frame.

In this embodiment, it consists of a first MOS field effect transistor M ₁ and the second MOS field effect transistor M ₂ are both N-channel devices biased by the operational amplifier A ₀ to the digital input signal V _IN is supplied I have.

The current mirror circuit B ₁ represents includes a third MOS field effect transistor M _3, and a fourth MOS field effect transistor M _4. Third MOS field effect transistor M ₃ represents a P-channel device, a gate G ₃ and the drain D ₃ are connected in common, a source connected S ₃ is to the power supply voltage V _DD, the drain D ₃ of the second drain D of the MOS field-effect transistor M ₂
Connected to _two .

The 4 MOS field effect transistor M ₄ of a P-channel device, so as to constitute a third MOS field effect transistor M ₃ and the current mirror, the gate G ₄ is of the third MOS field effect transistor M ₃ gate G is connected to ₃ are biased, the drain D ₄ is connected to the drain D ₁ of the first MOS field effect transistor M _1.

The operation waveform of each part of the circuit in this embodiment is the same as that in FIG. That is, when the digital input signal V _IN given to the gate G ₁ of the _first MOS field-effect transistor M ₁ is at a high level, the first MOS field-effect transistor M ₁ conducts, and the charge stored in the capacitor C is discharged. As a result, the node a becomes low level (about 0 V). Next, the digital input signal V
When _IN goes low, the first MOS field effect transistor M ₁ becomes cut-off, the 4 MOS field effect transistor M ₄ of the active state because it is biased by a third MOS field effect transistor M ₃ It is in. 4th MO
S field effect transistor M _4, since it constitutes a third MOS field effect transistor M ₃ and the current mirror, the fourth
The MOS field effect transistor M _4, a second MOS field effect transistor M _2, a current proportional to the current flowing through the third MOS field effect transistor M ₃ and the resistor R _c flows, which capacitor C is charged by, A lamp voltage is formed.

The configuration and circuit operation of the bias means 1 are the same as those in FIGS. 4 and 5, and this embodiment also provides a delay circuit with less delay time fluctuation due to temperature fluctuation, manufacturing process fluctuation and power supply voltage fluctuation. Can be

FIG. 7 shows still another embodiment of the delay circuit according to the present invention. This embodiment shows a configuration example of a current mirror circuit B ₂ when the first and second MOS field effect transistors M ₁ and M ₂ is P-channel device. The third and fourth MOS field-effect transistors M ₃ and M ₄ constituting the current mirror circuit B ₂ are both constituted by N-channel elements.

The operation waveform of each part of the circuit in this embodiment is the same as in FIG. That is, when the digital input signal V _IN supplied to the gate G ₁ of the _first MOS field-effect transistor M ₁ is at a low level, the first MOS field-effect transistor M ₁ conducts, the capacitor C is charged, and the node a is high level (about
V _DD ). Next, the digital input signal V _IN becomes high level, when the first MOS field effect transistor M ₁ is cut off, the charge accumulated in the capacitor C is of the 4 MO
Is discharged through S field effect transistor M _4, the lamp voltage is formed. The discharge current at this time, the current mirror action of the third MOS field effect transistor M ₃ and the fourth MOS field-effect transistor M _4, a second MOS field effect transistor M _2, the third MOS field effect transistor M _Three
And a value proportional to the current flowing through the resistor R _c.

The configuration and circuit operation of the bias means 1 are the same as those shown in FIGS. 1 and 3. According to this embodiment, a delay circuit having a small delay time fluctuation due to temperature fluctuation, manufacturing process fluctuation and power supply voltage fluctuation can be obtained. Can be

In the embodiment of Figure 6 and Figure 7, a third MOS field effect transistor M ₃ fourth MOS field effect transistor M
₄ and the current mirror circuit, but the resistance R _c and the second
Can also the configuration of the MOS field effect transistor M ₂ and the third MOS field effect transistor M ₃ current multiple current mirror circuit through the transmission to the fourth MOS field-effect transistor M ₄ the same effect It is.
For example, in the delay circuit shown in FIGS.
And a fifth MOS field-effect transistor forming a first current mirror circuit, and a sixth MOS charge-effect transistor whose drain and drain are commonly connected to each other. 4 M
A second current mirror circuit can be configured with the OS field effect transistor. At this time, the gate and source of the fifth MOS field-effect transistor are connected to the gate and source of the third MOS field-effect transistor, respectively, and the gate and source of the sixth MOS field-effect transistor are connected to the fourth MOS field-effect transistor. And the gate and source of the sixth MOS field effect transistor are commonly connected.

According to these embodiments having a current mirror circuit, when a plurality of delay circuits are arranged on the same semiconductor chip, the first MOS field effect transistor M ₁ , the fourth MOS field effect transistor M ₄ , the capacitor C And logic circuit Q ₁
And a current generating circuit including an operational amplifier A ₀ , a resistor R _c , second and third MOS field-effect transistors M ₂ and M ₃ , and a means for generating a temperature-insensitive voltage The bias means 1 including the means 101 for generating a voltage proportional to the temperature, the means 103 for extracting the threshold voltage of the logic circuit 103 and the voltage generating means 104 can be commonly used for all the delay circuits. The area and power consumption can be reduced.

FIG. 8 shows still another embodiment according to the present invention, and FIG. 9 shows an operation waveform example thereof. The feature of this embodiment is that the digital input signal V _IN is branched into two paths of inversion and non-inversion using inverters INV ₁ and INV ₂ , and a first circuit for delaying a rising edge and a falling edge in each path are provided. the second constitutes a circuit for delaying the output of the first circuit and the second circuit, reproduce the same pulse width and the input signal V _iN by synthesizing a flip-flop FF of the logic circuit Q _1, or It is intended to set an arbitrary output signal pulse width.

The first circuit and the second circuit in this embodiment are the first circuit and the second circuit.
It has the same configuration as the embodiment shown in the figure.

The first circuit includes a first MOS field-effect transistor M ₁₁ ,
The first MOS transistor M ₂₁ includes a second MOS field-effect transistor M ₂₁ , a resistor R ₁₀ , an operational amplifier A ₁₀ and a capacitor C _1.
The inverter IN to the gate G ₁₁ of the OS field effect transistor M ₁₁
The digital input signal V _IN inverted by V ₁ is input.

The second circuit includes a first MOS field-effect transistor M ₁₂ ,
Second MOS field effect transistor M _22, resistors R _20, is configured to include an operational amplifier A ₂₀ and the capacitor C _2.
The gate G ₁₂ of the first MOS field effect transistor M _12,
Digital input signal V inverted by inverter INV ₁
The _IN, and further inverted by the inverter INV _2, resulting in the digital input signal V _IN that the non-inverted is supplied.

Logic circuit Q ₁ is, the flip-flop FF and an inverter INV ₃
It is comprised including. The flip-flop FF is 2
This is an RS flip-flop composed of _two NOR gates NOR ₁ and NOR ₂ and operates with the output high level of the first circuit as a set signal and the output high level of the second circuit as a reset signal.

Each inverting input terminal of the operational amplifier A _10, A ₂₀ (-), the resistance
Each source S ₂₁ , of the second MOS field-effect transistors M ₂₁ and M ₂₂ connected to the power supply voltage V _DD via R ₁₀ and R ₂₀ , respectively.
Are connected to S _22, each output terminal is connected to the gate G _21, G ₂₂ of the second MOS field effect transistors M _21, M _22.

The non-inverting input terminals (+) of the operational amplifiers A ₁₀ and A ₂₀ are commonly connected to the bias unit 1.

FIG. 10 shows a specific example of the bias means 1 used in this embodiment. As in FIG. 3, the bias means 1 of this embodiment includes a means 101 for generating _a temperature-insensitive voltage Va, _a means 102 for generating a voltage _Vb proportional to temperature, and a threshold voltage V _{TH of} a logic circuit.
Each voltage produced or extracted by means 103, and their respective means for extracting, voltage generating means for generating a DC voltage V _X, which calculates a power supply voltage supplied to the non-inverting input terminal of the operational amplifier A ₀ It consists of 104. Of these means 101, 102, 104 are exactly the same configuration as FIG. 3, but includes logic circuit Q ₁ is a flip-flop FF in the present embodiment, the threshold voltage V _TH for converting a lamp voltage to the logic output since the threshold voltage of the NOR gate NOR _1, NOR ₂ constituting the flip-flop FF, means 104 is configured to include a logic gate NOR _1, NOR ₂ equivalent NOR gates Q _51. The NOR
Gate Q _51, together with the one input is connected to ground and an output connected to the other input. Since the threshold voltages of all the feedback NOR gate having an output connected to the input becomes the threshold voltage of the NOR gate, the threshold when the logic circuit Q _51, the flip-flop FF is set or reset to a logic circuit Q ₁ Threshold voltage V substantially equal to the voltage
_TH is extracted.

The operation will be described with reference to FIG. 8 and FIG. Ninth
As shown in FIG. 9A, when the digital input signal V _IN goes to the high level at t ₀ , the node c, which is the output terminal of the inverter INV ₁ , has the low level as shown in FIG. 9B. , An inverted signal appears. This inverted signal is
Since applied to the gate G ₁₁ of the first MOS field effect transistor M ₁₁ of the first circuit, the operation described in FIGS. 1 and 2, as shown in FIG. 9 (c), to the node d ,
Ramp waveform to start charging at t ₀ is the rising edge of the digital input signal V _IN is obtained. Then, the lamp voltage crosses the threshold voltage V _TH having a flip-flop FF t ₁ at the flip-flop FF is set, as shown in FIG. 9 (f), the output V _OUT of the high level from the inverter INV ₃ is obtained . Time delay from time t ₀ of the above until t ₁ becomes the rise delay time Td _LH.

On the other hand, as shown in FIG. 9 (a), at t ₂ delayed from the time t ₀ by the pulse width of the digital input signal V _IN, becomes a low level falls the digital input signal V _IN, FIG. 9 (d as shown in), the node e, which is the output end of the inverter INV _2, the non-inverted signal of the state transition to the same low level appears. This non-inverted signal is output from the first MOS of the second circuit.
Since applied to the gate G ₁₂ of the field effect transistor M _12, the node f, as shown in FIG. 9 (e), the digital input signal V _IN falling edge at which t ₂ during ramp waveform starts charging the Is obtained. Then, at t ₃ the ramp voltage crosses the threshold voltage _TH having the flip-flop FF, the flip-flop FF is reset, a result, the output V _OUT of the inverter INV ₃ has a low level as shown in FIG. 9 (f) Become. time delay from the time t ₂ to time t ₃ becomes the fall delay time Td _HL.

In this embodiment, the resistance values of the resistors R ₁₀ and R ₂₀ and the capacitor
The rise delay time Td is determined by selecting the capacitance values of C ₁ and C _2.
It is possible to equalize the _LH and fall delay time Td _HL, it is possible to obtain a delayed output signal V _OUT of the same pulse width as the digital input signal V _IN. Also, if necessary,
By setting the rising and falling delay times Td _LH and Td _HL independently of each other, an output signal _VOUT having an arbitrary pulse width can be obtained.

Therefore, according to this embodiment, as in each of the above embodiments,
Delay time fluctuations due to temperature fluctuations, power supply voltage fluctuations and manufacturing process fluctuations are compensated and mitigated, and a delay circuit that provides an output signal V _OUT having the same pulse width as the digital input signal V _IN or an arbitrary pulse width is obtained.

As the first circuit and the second circuit of the embodiment shown in FIG. 8, for example, a delay circuit shown in FIG. 6 including a current mirror circuit can be used. At this time, the operational amplifier A ₀ , the resistor R _c , and the second MOS field-effect transistor M
Current generating circuit composed of _second and third MOS field effect transistor M ₃ are, it can be common for the first circuit and the second circuit, power consumption can be reduced and reduction of the occupied area.

FIG. 11 shows still another embodiment of the delay circuit according to the present invention, and FIG. 12 shows an example of the operation waveform. In this embodiment, similarly to the embodiment shown in FIG. 8, a first circuit which branches the digital input signal V _IN into two paths of non-inversion and inversion by using an inverter INV ₁ and delays a rising edge in each path. And a second circuit for delaying the falling edge, wherein the outputs of the first and second circuits are
By synthesizing a flip-flop FF of the logic circuit Q _1, the delayed output signal, the digital input signal
It is intended to reproduce the same pulse width as V _IN or to set an arbitrary output signal pulse width. This embodiment is characterized in that the first circuit and the second circuit have the same configuration as that of the embodiment shown in FIG.
That is, it is composed of ND gate.

The first circuit is composed of an operational amplifier A ₁₀ , a resistor R ₁₀ , a first MOS
The first M transistor includes a field-effect transistor M ₁₁ , a second MOS field-effect transistor M _21, and a capacitor C _1.
Digital input signal V _IN is input to the gate G ₁₁ of the OS field effect transistor M _11.

The second circuit is composed of an operational amplifier A ₂₀ , a resistor R ₂₀ , a first MOS
The first M transistor includes a field-effect transistor M ₁₂ , a second MOS field-effect transistor M _22, and a capacitor C _2.
Inverter to the gate G ₁₂ of the OS field-effect transistor M ₁₂
A digital input signal V _IN inverted at INV ₁ is provided.

Logic circuit Q ₁ is, the flip-flop FF and an inverter INV ₃
It is comprised including. The flip-flop FF is 2
This is an RS flip-flop composed of a plurality of NAND gates NAND ₁ and NAND ₂ , and operates using the output low level of the first circuit as a set signal and the output low level of the second circuit as a reset signal.

Each inverting input terminal of the operational amplifier A _10, A ₂₀ (-), the resistance
The respective output terminals are connected to the respective sources S ₂₁ and S ₂₂ of the second MOS field-effect transistors M ₂₁ and M ₂₂ which are grounded via R ₁₀ and R ₂₀ respectively. _21, is connected to the gate G _21, G ₂₂ of M _22.

The non-inverting input terminals (+) of the operational amplifiers A ₁₀ and A ₂₀ are commonly connected to the bias unit 1.

FIG. 13 shows a specific example of the bias means 1 used in this embodiment. As in FIG. 5, the bias means 1 of this embodiment includes a means 101 for generating _a temperature-insensitive voltage Va, _a means 102 for generating a voltage _Vb proportional to temperature, and a threshold voltage V
Means 103 for extracting _TH, and voltage generating means for generating a DC voltage V _X supplied with each voltage and the power supply voltage generated or extracted into the non-inverting input terminal of the operational to operational amplifier A ₀ by respective means It consists of 104. Of these means 101, 102, 104 are exactly the same configuration as FIG. 5 but includes a logic circuit Q ₁ is a flip-flop FF in the present embodiment, the threshold voltage V _TH for converting a lamp voltage to the logic output Since the threshold voltages of the NAND gates NAND ₁ and NAND ₂ constituted by the flip-flops FF are used, the means 104 becomes the logic gates NAND ₁ and NAND 2.
And it is configured to include a ₂ equivalent NAND gate Q _51. The
NAND gate Q _51, together with the one input is connected to the power supply voltage V _DD, the output is connected to the other input. Since the output voltage of the all feedback NAND gate whose output is connected to the input becomes the threshold voltage of the NAND gate, the logic circuit Q ₅₁
Accordingly, the threshold voltage substantially equal to the threshold voltage V _TH when the flip-flop FF of the logic circuit Q ₁ is being set or reset is extracted.

The operation will be described with reference to FIGS. 11 and 12. Twelfth
As shown in FIG. 7A, when the digital input signal V _IN goes high at t ₀ , the digital input signal V _IN
IN is the first MOS field-effect transistor M ₁₁ of the first circuit.
Since given to the gate G _11, the operation described in the embodiment shown in FIG. 4, as shown in Figure 12 (b), at t ₀ is the rising edge of the digital input signal V _IN to the node d A ramp waveform for starting discharge is obtained. The ramp voltage is the threshold voltage of the flip-flop FF
At t ₁ across V _IN , the flip-flop FF is set,
As shown in Fig. 12 (e), the output V _OUT of high level is obtained from the inverter INV _3. Time delay from time t ₀ of the above until t ₁ is the rise delay time Td _LH.

On the other hand, as shown in Figure 12 (a), at t ₂ delayed from the time t ₀ by the pulse width of the digital input signal V _IN, it becomes a low level falls the digital input signal V _IN, the output of the inverter INV ₁ FIG. 12 (c)
As shown in the figure, an inverted signal that makes a state transition to a high level appears. This inverted signal is applied to the gate G ₁₂ of the first MOS field effect transistor M ₁₂ of the second circuit,
The node f, as shown in Fig. 12 (d), the ramp waveform to start t ₂ during discharge is the falling edge of the digital input signal V _IN is obtained. Then, at t ₃ when the ramp voltage crosses the threshold voltage V _TH of the flip-flop FF,
Reset flip-flop FF, the result, as shown in Fig. 12 (e), the output V _OUT at a low level from the inverter INV ₃ is obtained. time delay from the time t ₂ to time t ₃ becomes the fall delay time Td _HL.

In this embodiment, the resistance values of the resistors R ₁₀ and R ₂₀ and the capacitor
By selecting the capacitance values of C ₁ and C ₂ , the delay time Td _LH and the delay time Td _HL can be made equal, so that an output signal V _OUT having the same pulse width as the digital input signal V _IN can be obtained. If necessary, the rising and falling delay times Td _LH and Td _HL can be set independently of each other to obtain an output signal V _OUT having an arbitrary pulse width.

Therefore, according to the present embodiment, similarly to the embodiment shown in FIG. 8, the delay time fluctuation due to temperature fluctuation, power supply voltage fluctuation and manufacturing process fluctuation is compensated and mitigated, and the same pulse as the input digital signal _VIN is used. A delay circuit that provides an output signal _VOUT having a width or an arbitrary pulse width is obtained.

As the first circuit and the second circuit of the embodiment shown in FIG. 11, for example, the delay circuit shown in FIG. 7 including a current mirror circuit can be used. At this time, the operational amplifier A ₀ , the resistor R _c , and the second MOS field-effect transistor M
_Second and third current generating circuit constituted by MOS field-effect transistor M ₃ of, for the first circuit and the second circuit can be common, power consumption can be reduced and the area occupied.

A plurality of delay circuits of the embodiment shown in FIG. 8 and the embodiment shown in FIG. 11 are connected in cascade, and the output signal _VOUT of the previous stage is used as the digital input signal _VIN of the next stage, so that A tapped delay circuit having the output signal _VOUT as a tap output can be configured.

When a delay circuit with taps is configured using the delay circuit shown in FIG. 8, the NOR gate NOR _{1 of the} flip-flop FF is used.
The output signal (the input signal of the inverter INV ₃₎ and the next stage of the digital input signal V _IN, an output signal of the inverter INV ₁ to the gate G ₁₂ of the first MOS field effect transistor M ₁₂ of the first circuit, the inverter the output signal of the INV ₂ to the gate G ₁₁ of the first MOS field effect transistor M ₁₁ of the first circuit, be configured to direct each tap output (inverter INV ₃
This is effective for preventing the load-related delay time generated by the load capacitance of (output) from being transmitted to the next stage.

Similarly, when a delay circuit with taps is formed using the delay circuit shown in FIG. 11, the output signal of the NAND gate NAND ₂ of the flip-flop FF (the input signal of the inverter INV ₃ ) is converted to the digital input signal V of the next stage. and _iN, the input signal V _iN to the gate G ₁₂ of the first MOS field effect transistor M ₁₂ of the second circuit, the output signal of the inverter INV ₁ of the first circuit 1 of the MOS field effect transistor M ₁₁ to the gate G _11, if configured to direct each tap output (inverter INV ₃
This is effective in preventing the additional delay time caused by the load capacitance of (output) from being transmitted to the next stage.

<Effect of the Invention> As described above, the delay circuit according to the present invention has the first
Depending on the state of the delayed digital input signal supplied to the gate of the MOS field effect transistor, the capacitor is charged or accumulated by the second MOS field effect transistor current source whose source is guided to the power supply line via a resistor. A lamp voltage is generated by discharging the electric charge, and a circuit configuration is provided in which a delay time is set using the time until the lamp voltage reaches a threshold value, and between the gate and the source of the second MOS field-effect transistor. Means for providing an appropriate bias voltage, the means for generating a temperature insensitive voltage, the means for generating a voltage proportional to temperature, the means for extracting a threshold voltage of the logic circuit, and the voltage generator. And an operational amplifier. The inverting input terminal of the operational amplifier is connected to the source of the second MOS field-effect transistor. The terminal is connected to the gate of the second MOS field-effect transistor, and the voltage generating means converts the DC voltage obtained by calculating each voltage extracted or generated by each means and the power supply voltage into the non-inverting voltage of the operational amplifier. Because it is configured to be applied to the input terminal, it is suitable for integration,
It is possible to provide a delay circuit with less delay time fluctuation due to manufacturing process fluctuation, temperature fluctuation and power supply voltage fluctuation.

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram showing an embodiment of a delay circuit according to the present invention, FIGS. 2 and 3 are diagrams showing an example of operation waveforms and a concrete example of bias means in this embodiment, and FIG. FIG. 5 is an electric circuit diagram showing still another embodiment of the delay circuit according to the present invention; FIG. 5 is a diagram showing a specific example of the bias means;
FIG. 7 and FIG. 7 are electric circuit diagrams showing still another embodiment of the delay circuit according to the present invention. FIG. 8 is an electric circuit diagram showing still another embodiment of the delay circuit according to the present invention. (A) ~
(F) and FIG. 10 are diagrams showing an example of operation waveforms and a specific example of bias means in this embodiment. FIG. 11 is an electric circuit diagram showing still another embodiment of the delay circuit according to the present invention.
13 (a) to 13 (e) and FIG. 13 are diagrams showing an example of operation waveforms and specific examples of bias means in this embodiment, FIG. 14 is a circuit diagram of a conventional delay circuit, and FIGS. 15 (a) to 15 ( (c) is a diagram showing an example of the operation waveform. M ₁ … first MOS field effect transistor M ₂ … second MOS field effect transistor M ₃ … third MOS field effect transistor M ₄ … fourth MOS field effect transistor C …… capacitor, Q ₁ Logic circuit 1 Bias means A ₀ Operational amplifier 101 Means for generating a voltage insensitive to temperature 102 Means for generating a voltage proportional to temperature 103 Threshold voltage of a logic circuit is extracted Means 104 ... Voltage generating means

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Yasutomo Yamanoi 1-13-1 Nihonbashi, Chuo-ku, Tokyo Inside TDK Corporation

Claims (5)

(57) [Claims] 1. A first MOS field-effect transistor and a second MOS field-effect transistor.
A delay circuit including a MOS field-effect transistor, an operational amplifier, a resistor, a capacitor, a logic circuit, and a bias circuit, wherein the first MOS field-effect transistor has, at its gate, a digital signal that is a delayed signal. The input signal is guided, the source is guided to one of the power supply lines, and the drain of the second MOS field effect transistor is guided to the drain of the first MOS field effect transistor, and the source is the resistor. The operational amplifier includes an inverting input terminal, a non-inverting input terminal, and an output terminal, and the inverting input terminal is connected to the second MOS.
The output terminal is connected to the gate of the second MOS field effect transistor, and the capacitor is connected between a common drain connection point of the MOS field effect transistor and the power supply line. The logic circuit has a threshold voltage, is a circuit that converts a voltage between the terminals of the capacitor into a binary signal based on the threshold voltage, and outputs the binary signal, as a delayed digital signal, the bias circuit, A circuit that generates a voltage that is insensitive to temperature, a circuit that generates a voltage proportional to temperature, a circuit that extracts a threshold voltage of the logic circuit, and a voltage generation circuit, wherein the voltage generation circuit is proportional to temperature. From the sum of the voltage generated by the circuit for generating the threshold voltage and the voltage extracted by the circuit for extracting the threshold voltage of the logic circuit, An operation for reducing the voltage generated by the circuit that generates the voltage, a difference between the voltage obtained by the operation and the voltage obtained from the power supply voltage is calculated to generate a DC voltage, and the DC voltage is calculated. The delay circuit is provided to the non-inverting input terminal of the operational amplifier. 2. A first MOS field effect transistor and a second MOS field effect transistor.
A delay circuit including a MOS field-effect transistor, an operational amplifier, a resistor, a capacitor, a logic circuit, a bias circuit, and a current mirror circuit, wherein the first MOS field-effect transistor is connected to a gate. A digital input signal that is a delay signal is guided, and a source is guided to one of the power supply lines. The second MOS field-effect transistor has a source guided to one of the power supply lines via the resistor. The operational amplifier includes an inverting input terminal, a non-inverting input terminal, and an output terminal, wherein the inverting input terminal is connected to the second MOS transistor.
The output terminal is connected to a source of a field-effect transistor, the output terminal is connected to a gate of the second MOS field-effect transistor, and the capacitor is connected between a drain of the first MOS field-effect transistor and a power supply line. The logic circuit has a threshold voltage, is a circuit that converts a voltage between the terminals of the capacitor into a binary signal based on the threshold voltage, and outputs the binary signal as a delayed digital signal. A circuit that generates a voltage insensitive to, a circuit that generates a voltage proportional to temperature, a circuit that extracts a threshold voltage of the logic circuit, and a voltage generation circuit, wherein the voltage generation circuit is proportional to temperature. Generates a temperature-insensitive voltage from the sum of the voltage generated by the circuit that generates the voltage and the voltage extracted by the circuit that extracts the threshold voltage of the logic circuit Performing a calculation to reduce the voltage generated by the circuit, and calculating a difference between the voltage obtained by the calculation and the voltage obtained from the power supply voltage to generate a DC voltage;
Applying the DC voltage to the non-inverting input terminal of the operational amplifier, the current mirror circuit includes a third MOS field-effect transistor and a fourth MOS field-effect transistor, and the third MOS field-effect transistor Has a gate and a drain commonly connected, a source connected to one of the power supply lines, a drain connected to a drain of the second MOS field-effect transistor, The third MOS
A delay circuit, wherein a gate is biased to form a current mirror with a field effect transistor, and a drain is connected to a drain of the first MOS field effect transistor. 3. A first MOS field-effect transistor and a second MOS field-effect transistor.
A delay circuit including a MOS field-effect transistor, an operational amplifier, a resistor, a capacitor, a logic circuit, and a bias circuit, wherein the first MOS field-effect transistor has, at its gate, a digital signal that is a delayed signal. The input signal is guided, the source is guided to one of the power supply lines, and the drain of the second MOS field effect transistor is guided to the drain of the first MOS field effect transistor, and the source is the resistor. The operational amplifier includes an inverting input terminal, a non-inverting input terminal, and an output terminal, and the inverting input terminal is connected to the second MOS.
The output terminal is connected to the gate of the second MOS field effect transistor, and the capacitor is connected between a common drain connection point of the MOS field effect transistor and the power supply line. The logic circuit has a threshold voltage, is a circuit that converts a voltage between the terminals of the capacitor into a binary signal based on the threshold voltage, and outputs the binary signal, as a delayed digital signal, the bias circuit, A circuit that generates a temperature-insensitive voltage based on a power supply voltage, a circuit that generates a voltage proportional to temperature based on the power supply voltage, and a circuit that extracts a threshold voltage of the logic circuit based on the power supply voltage And a voltage generation circuit, wherein the voltage generation circuit generates a voltage proportional to temperature, a voltage generated by the circuit, and a threshold voltage of the logic circuit. A DC voltage is generated by subtracting the voltage generated by the circuit that generates the temperature-insensitive voltage from the sum of the voltage extracted by the circuit and the DC voltage generated by the circuit that generates the temperature-insensitive voltage. The delay circuit is provided to the non-inverting input terminal. 4. A first MOS field-effect transistor and a second MOS field-effect transistor.
A delay circuit including a MOS field-effect transistor, an operational amplifier, a resistor, a capacitor, a logic circuit, a bias circuit, and a current mirror circuit, wherein the first MOS field-effect transistor is connected to a gate. A digital input signal that is a delay signal is guided, and a source is guided to one of the power supply lines. The second MOS field-effect transistor has a source guided to one of the power supply lines via the resistor. The operational amplifier includes an inverting input terminal, a non-inverting input terminal, and an output terminal, wherein the inverting input terminal is connected to the second MOS transistor.
The output terminal is connected to a source of a field-effect transistor, the output terminal is connected to a gate of the second MOS field-effect transistor, and the capacitor is connected between a drain of the first MOS field-effect transistor and a power supply line. The logic circuit has a threshold voltage, is a circuit that converts a voltage between terminals of the capacitor into a binary signal based on the threshold voltage, and outputs the binary signal, and the bias circuit includes a power supply. A circuit that generates a temperature-insensitive voltage based on the voltage, a circuit that generates a voltage proportional to the temperature based on the power supply voltage, and a circuit that extracts a threshold voltage of the logic circuit based on the power supply voltage And a voltage generation circuit, wherein the voltage generation circuit extracts a voltage generated by the circuit that generates a voltage proportional to temperature and a threshold voltage of the logic circuit. A DC voltage is generated by performing an operation of subtracting the voltage generated by the circuit that generates a temperature-insensitive voltage from the sum of the threshold voltage extracted by the circuit and the DC voltage. The current mirror circuit includes a third MOS field-effect transistor and a fourth MOS field-effect transistor, and the third MOS field-effect transistor has a gate and a drain connected in common. And a source is connected to one of the power supply lines, a drain is connected to a drain of the second MOS field effect transistor, and the fourth MOS field effect transistor is connected to the third MOS field effect transistor.
A delay circuit, wherein a gate is biased to form a current mirror with a field effect transistor, and a drain is connected to a drain of the first MOS field effect transistor. 5. The delay circuit according to claim 1, wherein said circuit for generating a voltage proportional to temperature includes a pair of diode-connected bipolar transistors and said bipolar transistor. A delay circuit comprising: an operational amplifier receiving each output of the transistor.